diff options
| author | Devin Heitmueller <dheitmueller@kernellabs.com> | 2010-06-27 18:12:42 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-12-29 08:16:34 -0200 |
| commit | 301c9f26d7ded6e274a99c3a447a9a36790a3f3e (patch) | |
| tree | 4e4efca609605c0c6755bd4393e03abe941ca502 /drivers/media/dvb/frontends/au8522_decoder.c | |
| parent | d2c194ce4781d62bf671aa6b65a2fccb39feb50e (diff) | |
[media] au8522: Handle differences in comb filter config for s-video input
Tweak the comb filter config when in s-video mode to match the Hauppauge
Windows driver values (based on register dumps).
This work was sponsored by GetWellNetwork Inc.
Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb/frontends/au8522_decoder.c')
| -rw-r--r-- | drivers/media/dvb/frontends/au8522_decoder.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/drivers/media/dvb/frontends/au8522_decoder.c b/drivers/media/dvb/frontends/au8522_decoder.c index 5ec86970640..b537891a4cc 100644 --- a/drivers/media/dvb/frontends/au8522_decoder.c +++ b/drivers/media/dvb/frontends/au8522_decoder.c @@ -278,10 +278,18 @@ static void setup_decoder_defaults(struct au8522_state *state, u8 input_mode) AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS); au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS); - au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH, - AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS); - au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH, - AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS); + if (input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 || + input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24) { + au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH, + AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO); + au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH, + AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO); + } else { + au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH, + AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS); + au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH, + AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS); + } au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS); au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH, |