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authorFelix Fietkau <nbd@openwrt.org>2012-04-19 21:18:26 +0200
committerJohn W. Linville <linville@tuxdriver.com>2012-04-23 15:35:31 -0400
commit7c5adc8d83c344dbad251091879baf1244007564 (patch)
tree05494972ed0de7a8f9e0f634276400b597a126c2 /drivers/net/wireless/ath/ath9k/hw.c
parent3e61d3f9b2f6381f6f30d3d0ff874251a3491d05 (diff)
ath9k_hw: fix and clean up PHY activation delay
The delay calculation is the same for all chips, however some parts of the code missed the extra delay factor for half/quarter. Clean up the code and move the delay calculation to a common place. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 4dddffd7c40..e576a92f18a 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -191,6 +191,22 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
}
EXPORT_SYMBOL(ath9k_hw_wait);
+void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
+ int hw_delay)
+{
+ if (IS_CHAN_B(chan))
+ hw_delay = (4 * hw_delay) / 22;
+ else
+ hw_delay /= 10;
+
+ if (IS_CHAN_HALF_RATE(chan))
+ hw_delay *= 2;
+ else if (IS_CHAN_QUARTER_RATE(chan))
+ hw_delay *= 4;
+
+ udelay(hw_delay + BASE_ACTIVATE_DELAY);
+}
+
void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
int column, unsigned int *writecnt)
{