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authorJiang Liu <jiang.liu@huawei.com>2012-07-24 17:20:33 +0800
committerBjorn Helgaas <bhelgaas@google.com>2012-08-23 10:11:16 -0600
commit479e0d485eaab452cf248cd1a9520015023b35b2 (patch)
tree648ad71d7bd2838678f66d055fcaae654b5e4ddc /drivers/staging/rtl8192e
parent532c5f69e223ec846511fa4a14fa1fc8bca142a2 (diff)
rtl8192e: Use PCI Express Capability accessors
Use PCI Express Capability access functions to simplify rtl8192e driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/staging/rtl8192e')
-rw-r--r--drivers/staging/rtl8192e/rtl8192e/rtl_pci.c8
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_pci.c b/drivers/staging/rtl8192e/rtl8192e/rtl_pci.c
index ddadcc3e4e7..5abbee37cdc 100644
--- a/drivers/staging/rtl8192e/rtl8192e/rtl_pci.c
+++ b/drivers/staging/rtl8192e/rtl8192e/rtl_pci.c
@@ -31,12 +31,10 @@ static void rtl8192_parse_pci_configuration(struct pci_dev *pdev,
struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
u8 tmp;
- int pos;
- u8 LinkCtrlReg;
+ u16 LinkCtrlReg;
- pos = pci_find_capability(priv->pdev, PCI_CAP_ID_EXP);
- pci_read_config_byte(priv->pdev, pos + PCI_EXP_LNKCTL, &LinkCtrlReg);
- priv->NdisAdapter.LinkCtrlReg = LinkCtrlReg;
+ pcie_capability_read_word(priv->pdev, PCI_EXP_LNKCTL, &LinkCtrlReg);
+ priv->NdisAdapter.LinkCtrlReg = (u8)LinkCtrlReg;
RT_TRACE(COMP_INIT, "Link Control Register =%x\n",
priv->NdisAdapter.LinkCtrlReg);