diff options
| author | Jingoo Han <jg1.han@samsung.com> | 2012-04-16 09:33:12 +0900 |
|---|---|---|
| committer | Florian Tobias Schandinat <FlorianSchandinat@gmx.de> | 2012-04-16 04:19:00 +0000 |
| commit | 8affaf5c7698c627b133bfcafd9869ef17faff31 (patch) | |
| tree | b8bb79b3f8709ec1fb1d99e100c22711a72ffd23 /drivers/video/exynos/exynos_dp_reg.h | |
| parent | 8f802da33a842bc9e511d2a9c8259fbee8a6d17e (diff) | |
video: exynos_dp: add analog and pll control setting
This patch adds analog and pll control setting. This control setting
is used for DP TX PHY block to set the values as below. It is beneficial
to improve analog characteristics.
- TX terminal registor is 50 Ohm.
- Reference clock of PHY is 24 MHz.
- Power source for TX digital logic is 1.0625 V.
- Power source for internal clock driver is 1.0625 V.
- PLL VCO range setting is 600 uA.
- Power down ring osc is turned off.
- AUX terminal resistor is 50 Ohm.
- AUX channel current is 8 mA and multiplied by 2.
- TX channel output amplitude is 400 mV.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Diffstat (limited to 'drivers/video/exynos/exynos_dp_reg.h')
| -rw-r--r-- | drivers/video/exynos/exynos_dp_reg.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/video/exynos/exynos_dp_reg.h b/drivers/video/exynos/exynos_dp_reg.h index 42f608e2a43..125b27cd57a 100644 --- a/drivers/video/exynos/exynos_dp_reg.h +++ b/drivers/video/exynos/exynos_dp_reg.h @@ -24,6 +24,12 @@ #define EXYNOS_DP_LANE_MAP 0x35C +#define EXYNOS_DP_ANALOG_CTL_1 0x370 +#define EXYNOS_DP_ANALOG_CTL_2 0x374 +#define EXYNOS_DP_ANALOG_CTL_3 0x378 +#define EXYNOS_DP_PLL_FILTER_CTL_1 0x37C +#define EXYNOS_DP_TX_AMP_TUNING_CTL 0x380 + #define EXYNOS_DP_AUX_HW_RETRY_CTL 0x390 #define EXYNOS_DP_COMMON_INT_STA_1 0x3C4 @@ -166,6 +172,29 @@ #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) +/* EXYNOS_DP_ANALOG_CTL_1 */ +#define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) + +/* EXYNOS_DP_ANALOG_CTL_2 */ +#define SEL_24M (0x1 << 3) +#define TX_DVDD_BIT_1_0625V (0x4 << 0) + +/* EXYNOS_DP_ANALOG_CTL_3 */ +#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) +#define VCO_BIT_600_MICRO (0x5 << 0) + +/* EXYNOS_DP_PLL_FILTER_CTL_1 */ +#define PD_RING_OSC (0x1 << 6) +#define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) +#define TX_CUR1_2X (0x1 << 2) +#define TX_CUR_8_MA (0x2 << 0) + +/* EXYNOS_DP_TX_AMP_TUNING_CTL */ +#define CH3_AMP_400_MV (0x0 << 24) +#define CH2_AMP_400_MV (0x0 << 16) +#define CH1_AMP_400_MV (0x0 << 8) +#define CH0_AMP_400_MV (0x0 << 0) + /* EXYNOS_DP_AUX_HW_RETRY_CTL */ #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) |