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authorMark Brown <broonie@sirena.org.uk>2008-02-27 15:34:56 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-02-29 22:47:30 +0000
commitd862ccc570c875e1454fc57ed00f5a1081985b26 (patch)
tree1322831adf6c0a1f9b86f3424ceffe03147ef615 /include
parentceee4f98f73bb7a1f6ee6710b9ebffd0ecb8c0ca (diff)
[ARM] 4843/1: Add GCR_CLKBPB for PXA3xx
The PXA3xx AC97 controller has an additional control bit GCR_CLKBPB which must be used during cold reset. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index ac175b4d10c..2357a73340d 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -520,6 +520,9 @@
#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
#define GCR __REG(0x4050000C) /* Global Control Register */
+#ifdef CONFIG_PXA3xx
+#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
+#endif
#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */