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author | Andrey Konovalov <andrey.konovalov@linaro.org> | 2013-05-05 02:40:36 +0400 |
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committer | Andrey Konovalov <andrey.konovalov@linaro.org> | 2013-05-05 02:40:36 +0400 |
commit | 314864b5a538c5ec1f871d814974edc37bdc676e (patch) | |
tree | f0d341e6eae1cd5c4ca6180aeb29a00e21ff8a8e /tools/gator/daemon/events-Krait-architected.xml | |
parent | e5f042c6edebec55bb20a5e399f892766ac65411 (diff) | |
parent | 8417d689429075fe59d92af4036e25424b13ea9c (diff) |
Merge branch 'tracking-integration-linux-vexpress' into merge-linux-linaro-lsklsk-20130505.0
Diffstat (limited to 'tools/gator/daemon/events-Krait-architected.xml')
-rw-r--r-- | tools/gator/daemon/events-Krait-architected.xml | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tools/gator/daemon/events-Krait-architected.xml b/tools/gator/daemon/events-Krait-architected.xml new file mode 100644 index 00000000000..4254666f794 --- /dev/null +++ b/tools/gator/daemon/events-Krait-architected.xml @@ -0,0 +1,22 @@ + <counter_set name="Krait_cnt" count="4"/> + <category name="Krait" counter_set="Krait_cnt" per_cpu="yes" supports_event_based_sampling="yes"> + <event counter="Krait_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> + <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> + <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> + <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> + <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/> + <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/> + <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/> + <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/> + <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/> + <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/> + <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/> + <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/> + <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/> + <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/> + <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/> + <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/> + <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/> + <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/> + <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/> + </category> |