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-rw-r--r--arch/arm/boot/dts/sunxi.dtsi82
1 files changed, 0 insertions, 82 deletions
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
deleted file mode 100644
index 8b36abea9f2..00000000000
--- a/arch/arm/boot/dts/sunxi.dtsi
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright 2012 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
- interrupt-parent = <&intc>;
-
- cpus {
- cpu@0 {
- compatible = "arm,cortex-a8";
- };
- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- osc: oscillator {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x01c20000 0x300000>;
- ranges;
-
- timer@01c20c00 {
- compatible = "allwinner,sunxi-timer";
- reg = <0x01c20c00 0x90>;
- interrupts = <22>;
- clocks = <&osc>;
- };
-
- wdt: watchdog@01c20c90 {
- compatible = "allwinner,sunxi-wdt";
- reg = <0x01c20c90 0x10>;
- };
-
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sunxi-ic";
- reg = <0x01c20400 0x400>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
- uart0: uart@01c28000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28000 0x400>;
- interrupts = <1>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clock-frequency = <24000000>;
- status = "disabled";
- };
-
- uart1: uart@01c28400 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28400 0x400>;
- interrupts = <2>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clock-frequency = <24000000>;
- status = "disabled";
- };
- };
-};