diff options
Diffstat (limited to 'arch/arm/mach-cns3xxx')
| -rw-r--r-- | arch/arm/mach-cns3xxx/Kconfig | 12 | ||||
| -rw-r--r-- | arch/arm/mach-cns3xxx/Makefile | 8 | ||||
| -rw-r--r-- | arch/arm/mach-cns3xxx/cns3420vb.c | 6 | ||||
| -rw-r--r-- | arch/arm/mach-cns3xxx/cns3xxx.h (renamed from arch/arm/mach-cns3xxx/include/mach/cns3xxx.h) | 34 | ||||
| -rw-r--r-- | arch/arm/mach-cns3xxx/core.c | 131 | ||||
| -rw-r--r-- | arch/arm/mach-cns3xxx/devices.c | 5 | ||||
| -rw-r--r-- | arch/arm/mach-cns3xxx/include/mach/debug-macro.S | 19 | ||||
| -rw-r--r-- | arch/arm/mach-cns3xxx/include/mach/irqs.h | 24 | ||||
| -rw-r--r-- | arch/arm/mach-cns3xxx/include/mach/timex.h | 12 | ||||
| -rw-r--r-- | arch/arm/mach-cns3xxx/include/mach/uncompress.h | 53 | ||||
| -rw-r--r-- | arch/arm/mach-cns3xxx/pcie.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-cns3xxx/pm.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-cns3xxx/pm.h (renamed from arch/arm/mach-cns3xxx/include/mach/pm.h) | 0 |
13 files changed, 147 insertions, 163 deletions
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig index 9ebfcc46feb..dbf0df8bb0a 100644 --- a/arch/arm/mach-cns3xxx/Kconfig +++ b/arch/arm/mach-cns3xxx/Kconfig @@ -1,8 +1,20 @@ +config ARCH_CNS3XXX + bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6 + select ARM_GIC + select CPU_V6K + select GENERIC_CLOCKEVENTS + select MIGHT_HAVE_CACHE_L2X0 + select MIGHT_HAVE_PCI + select PCI_DOMAINS if PCI + help + Support for Cavium Networks CNS3XXX platform. + menu "CNS3XXX platform type" depends on ARCH_CNS3XXX config MACH_CNS3420VB bool "Support for CNS3420 Validation Board" + depends on ATAGS help Include support for the Cavium Networks CNS3420 MPCore Platform Baseboard. diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile index 11033f1c2e2..a1ff1084869 100644 --- a/arch/arm/mach-cns3xxx/Makefile +++ b/arch/arm/mach-cns3xxx/Makefile @@ -1,3 +1,5 @@ -obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o -obj-$(CONFIG_PCI) += pcie.o -obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o +obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o +cns3xxx-y += core.o pm.o +cns3xxx-$(CONFIG_ATAGS) += devices.o +cns3xxx-$(CONFIG_PCI) += pcie.o +cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index a71867e1d8d..ce096d678aa 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c @@ -31,9 +31,8 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <mach/cns3xxx.h> -#include <mach/irqs.h> -#include <mach/pm.h> +#include "cns3xxx.h" +#include "pm.h" #include "core.h" #include "devices.h" @@ -247,6 +246,7 @@ static void __init cns3420_map_io(void) MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") .atag_offset = 0x100, + .nr_irqs = NR_IRQS_CNS3XXX, .map_io = cns3420_map_io, .init_irq = cns3xxx_init_irq, .init_time = cns3xxx_timer_init, diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/cns3xxx.h index b1021aafa48..a0f5b60662a 100644 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +++ b/arch/arm/mach-cns3xxx/cns3xxx.h @@ -20,22 +20,16 @@ #define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */ #define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */ -#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000 #define CNS3XXX_PPE_BASE 0x70001000 /* HANT */ -#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000 #define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */ -#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000 #define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */ -#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000 #define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */ -#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000 #define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */ -#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000 #define SMC_MEMC_STATUS_OFFSET 0x000 #define SMC_MEMIF_CFG_OFFSET 0x004 @@ -74,13 +68,10 @@ #define SMC_PCELL_ID_3_OFFSET 0xFFC #define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ -#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000 #define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ -#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000 #define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ -#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000 #define RTC_SEC_OFFSET 0x00 #define RTC_MIN_OFFSET 0x04 @@ -112,22 +103,16 @@ #define CNS3XXX_UART0_BASE_VIRT 0xFB002000 #define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ -#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 #define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */ -#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000 #define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */ -#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000 #define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */ -#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000 #define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */ -#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000 #define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */ -#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 #define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ #define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000 @@ -150,42 +135,31 @@ #define TIMER_FREERUN_CONTROL_OFFSET 0x44 #define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */ -#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000 #define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */ -#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000 #define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */ -#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000 #define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */ -#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000 #define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */ -#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000 #define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ #define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ #define CNS3XXX_SATA2_SIZE SZ_16M -#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000 #define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */ -#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000 #define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */ -#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000 #define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */ -#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000 #define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */ -#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000 #define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ #define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ -#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000 #define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ #define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000 @@ -239,7 +213,6 @@ #define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000) #define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ -#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 /* * Misc block @@ -553,6 +526,8 @@ int cns3xxx_cpu_clock(void); /* * ARM11 MPCore interrupt sources (primary GIC) */ +#define IRQ_TC11MP_GIC_START 32 + #define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0) #define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1) #define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2) @@ -624,9 +599,4 @@ int cns3xxx_cpu_clock(void); #define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64) -#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX) -#undef NR_IRQS -#define NR_IRQS NR_IRQS_CNS3XXX -#endif - #endif /* __MACH_BOARD_CNS3XXX_H */ diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index 52e4bb5cf12..e38b279f402 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c @@ -13,12 +13,18 @@ #include <linux/clockchips.h> #include <linux/io.h> #include <linux/irqchip/arm-gic.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/usb/ehci_pdriver.h> +#include <linux/usb/ohci_pdriver.h> +#include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> #include <asm/mach/irq.h> #include <asm/hardware/cache-l2x0.h> -#include <mach/cns3xxx.h> +#include "cns3xxx.h" #include "core.h" +#include "pm.h" static struct map_desc cns3xxx_io_desc[] __initdata = { { @@ -32,16 +38,6 @@ static struct map_desc cns3xxx_io_desc[] __initdata = { .length = SZ_4K, .type = MT_DEVICE, }, { - .virtual = CNS3XXX_GPIOA_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_GPIOB_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { .virtual = CNS3XXX_MISC_BASE_VIRT, .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE), .length = SZ_4K, @@ -266,3 +262,116 @@ void __init cns3xxx_l2x0_init(void) } #endif /* CONFIG_CACHE_L2X0 */ + +static int csn3xxx_usb_power_on(struct platform_device *pdev) +{ + /* + * EHCI and OHCI share the same clock and power, + * resetting twice would cause the 1st controller been reset. + * Therefore only do power up at the first up device, and + * power down at the last down device. + * + * Set USB AHB INCR length to 16 + */ + if (atomic_inc_return(&usb_pwr_ref) == 1) { + cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); + cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); + cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); + __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), + MISC_CHIP_CONFIG_REG); + } + + return 0; +} + +static void csn3xxx_usb_power_off(struct platform_device *pdev) +{ + /* + * EHCI and OHCI share the same clock and power, + * resetting twice would cause the 1st controller been reset. + * Therefore only do power up at the first up device, and + * power down at the last down device. + */ + if (atomic_dec_return(&usb_pwr_ref) == 0) + cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); +} + +static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { + .power_on = csn3xxx_usb_power_on, + .power_off = csn3xxx_usb_power_off, +}; + +static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { + .num_ports = 1, + .power_on = csn3xxx_usb_power_on, + .power_off = csn3xxx_usb_power_off, +}; + +static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = { + { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata }, + { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata }, + { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL }, + { "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL }, + {}, +}; + +static void __init cns3xxx_init(void) +{ + struct device_node *dn; + + cns3xxx_l2x0_init(); + + dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci"); + if (of_device_is_available(dn)) { + u32 tmp; + + tmp = __raw_readl(MISC_SATA_POWER_MODE); + tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ + tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ + __raw_writel(tmp, MISC_SATA_POWER_MODE); + + /* Enable SATA PHY */ + cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0); + cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1); + + /* Enable SATA Clock */ + cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA); + + /* De-Asscer SATA Reset */ + cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA)); + } + + dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci"); + if (of_device_is_available(dn)) { + u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); + u32 gpioa_pins = __raw_readl(gpioa); + + /* MMC/SD pins share with GPIOA */ + gpioa_pins |= 0x1fff0004; + __raw_writel(gpioa_pins, gpioa); + + cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); + cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO)); + } + + pm_power_off = cns3xxx_power_off; + + of_platform_populate(NULL, of_default_bus_match_table, + cns3xxx_auxdata, NULL); +} + +static const char *cns3xxx_dt_compat[] __initdata = { + "cavium,cns3410", + "cavium,cns3420", + NULL, +}; + +DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx") + .dt_compat = cns3xxx_dt_compat, + .nr_irqs = NR_IRQS_CNS3XXX, + .map_io = cns3xxx_map_io, + .init_irq = cns3xxx_init_irq, + .init_time = cns3xxx_timer_init, + .init_machine = cns3xxx_init, + .restart = cns3xxx_restart, +MACHINE_END diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c index 1e40c99b015..7da78a2451f 100644 --- a/arch/arm/mach-cns3xxx/devices.c +++ b/arch/arm/mach-cns3xxx/devices.c @@ -16,9 +16,8 @@ #include <linux/compiler.h> #include <linux/dma-mapping.h> #include <linux/platform_device.h> -#include <mach/cns3xxx.h> -#include <mach/irqs.h> -#include <mach/pm.h> +#include "cns3xxx.h" +#include "pm.h" #include "core.h" #include "devices.h" diff --git a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S deleted file mode 100644 index d04c150baa1..00000000000 --- a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Debugging macro include header - * - * Copyright 1994-1999 Russell King - * Copyright 2008 Cavium Networks - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - - .macro addruart,rp,rv,tmp - mov \rp, #0x00009000 - orr \rv, \rp, #0xf0000000 @ virtual base - orr \rp, \rp, #0x10000000 - .endm - -#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-cns3xxx/include/mach/irqs.h b/arch/arm/mach-cns3xxx/include/mach/irqs.h deleted file mode 100644 index 2ab96f8085c..00000000000 --- a/arch/arm/mach-cns3xxx/include/mach/irqs.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2000 Deep Blue Solutions Ltd. - * Copyright 2003 ARM Limited - * Copyright 2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_IRQS_H -#define __MACH_IRQS_H - -#define IRQ_LOCALTIMER 29 -#define IRQ_LOCALWDOG 30 -#define IRQ_TC11MP_GIC_START 32 - -#include <mach/cns3xxx.h> - -#ifndef NR_IRQS -#error "NR_IRQS not defined by the board-specific files" -#endif - -#endif diff --git a/arch/arm/mach-cns3xxx/include/mach/timex.h b/arch/arm/mach-cns3xxx/include/mach/timex.h deleted file mode 100644 index 1fd04217cac..00000000000 --- a/arch/arm/mach-cns3xxx/include/mach/timex.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Cavium Networks architecture timex specifications - * - * Copyright 2003 ARM Limited - * Copyright 2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#define CLOCK_TICK_RATE (50000000 / 16) diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h deleted file mode 100644 index 7a030b99df8..00000000000 --- a/arch/arm/mach-cns3xxx/include/mach/uncompress.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2003 ARM Limited - * Copyright 2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#include <asm/mach-types.h> -#include <mach/cns3xxx.h> - -#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) -#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) -#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30)) -#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18)) - -/* - * Return the UART base address - */ -static inline unsigned long get_uart_base(void) -{ - if (machine_is_cns3420vb()) - return CNS3XXX_UART0_BASE; - else - return 0; -} - -/* - * This does not append a newline - */ -static inline void putc(int c) -{ - unsigned long base = get_uart_base(); - - while (AMBA_UART_FR(base) & (1 << 5)) - barrier(); - - AMBA_UART_DR(base) = c; -} - -static inline void flush(void) -{ - unsigned long base = get_uart_base(); - - while (AMBA_UART_FR(base) & (1 << 3)) - barrier(); -} - -/* - * nothing to do - */ -#define arch_decomp_setup() diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c index 31132831416..c7b204bff38 100644 --- a/arch/arm/mach-cns3xxx/pcie.c +++ b/arch/arm/mach-cns3xxx/pcie.c @@ -20,7 +20,7 @@ #include <linux/interrupt.h> #include <linux/ptrace.h> #include <asm/mach/map.h> -#include <mach/cns3xxx.h> +#include "cns3xxx.h" #include "core.h" enum cns3xxx_access_type { diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c index 36458080332..79e3d47aad6 100644 --- a/arch/arm/mach-cns3xxx/pm.c +++ b/arch/arm/mach-cns3xxx/pm.c @@ -11,8 +11,8 @@ #include <linux/io.h> #include <linux/delay.h> #include <linux/atomic.h> -#include <mach/cns3xxx.h> -#include <mach/pm.h> +#include "cns3xxx.h" +#include "pm.h" #include "core.h" void cns3xxx_pwr_clk_en(unsigned int block) diff --git a/arch/arm/mach-cns3xxx/include/mach/pm.h b/arch/arm/mach-cns3xxx/pm.h index c2588cc991d..c2588cc991d 100644 --- a/arch/arm/mach-cns3xxx/include/mach/pm.h +++ b/arch/arm/mach-cns3xxx/pm.h |