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-rw-r--r--arch/arm/mach-mvebu/Kconfig1
-rw-r--r--arch/arm/mach-mvebu/armada-370-xp.c7
-rw-r--r--arch/arm/mach-mvebu/coherency_ll.S16
3 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index e11acbb0a46..80a8bcacd9d 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -15,6 +15,7 @@ config ARCH_MVEBU
select MVEBU_CLK_GATING
select MVEBU_MBUS
select ZONE_DMA if ARM_LPAE
+ select ARCH_REQUIRE_GPIOLIB
if ARCH_MVEBU
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 42a4cb3087e..1c48890bb72 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -54,13 +54,6 @@ void __init armada_370_xp_init_early(void)
char *mbus_soc_name;
/*
- * Some Armada 370/XP devices allocate their coherent buffers
- * from atomic context. Increase size of atomic coherent pool
- * to make sure such the allocations won't fail.
- */
- init_dma_coherent_pool_size(SZ_1M);
-
- /*
* This initialization will be replaced by a DT-based
* initialization once the mvebu-mbus driver gains DT support.
*/
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 53e8391192c..5476669ba90 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -32,15 +32,21 @@ ENTRY(ll_set_cpu_coherent)
/* Add CPU to SMP group - Atomic */
add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET
- ldr r2, [r3]
+1:
+ ldrex r2, [r3]
orr r2, r2, r1
- str r2, [r3]
+ strex r0, r2, [r3]
+ cmp r0, #0
+ bne 1b
/* Enable coherency on CPU - Atomic */
- add r3, r0, #ARMADA_XP_CFB_CFG_REG_OFFSET
- ldr r2, [r3]
+ add r3, r3, #ARMADA_XP_CFB_CFG_REG_OFFSET
+1:
+ ldrex r2, [r3]
orr r2, r2, r1
- str r2, [r3]
+ strex r0, r2, [r3]
+ cmp r0, #0
+ bne 1b
dsb