diff options
Diffstat (limited to 'arch/mips/include/asm/netlogic/xlr')
| -rw-r--r-- | arch/mips/include/asm/netlogic/xlr/iomap.h | 22 | ||||
| -rw-r--r-- | arch/mips/include/asm/netlogic/xlr/msidef.h | 84 | ||||
| -rw-r--r-- | arch/mips/include/asm/netlogic/xlr/pic.h | 69 | ||||
| -rw-r--r-- | arch/mips/include/asm/netlogic/xlr/xlr.h | 13 |
4 files changed, 137 insertions, 51 deletions
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h index 2e3a4dd5304..2e768f032e8 100644 --- a/arch/mips/include/asm/netlogic/xlr/iomap.h +++ b/arch/mips/include/asm/netlogic/xlr/iomap.h @@ -106,26 +106,4 @@ #define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 #define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 -#ifndef __ASSEMBLY__ -#include <linux/types.h> -#include <asm/byteorder.h> - -typedef volatile __u32 nlm_reg_t; -extern unsigned long netlogic_io_base; - -/* FIXME read once in write_reg */ -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#define netlogic_read_reg(base, offset) ((base)[(offset)]) -#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value)) -#else -#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)])) -#define netlogic_write_reg(base, offset, value) \ - ((base)[(offset)] = cpu_to_be32((value))) -#endif - -#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)])) -#define netlogic_write_reg_le32(base, offset, value) \ - ((base)[(offset)] = cpu_to_le32((value))) -#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset))) -#endif /* __ASSEMBLY__ */ #endif diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h new file mode 100644 index 00000000000..7e39d40be4f --- /dev/null +++ b/arch/mips/include/asm/netlogic/xlr/msidef.h @@ -0,0 +1,84 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ASM_RMI_MSIDEF_H +#define ASM_RMI_MSIDEF_H + +/* + * Constants for Intel APIC based MSI messages. + * Adapted for the RMI XLR using identical defines + */ + +/* + * Shifts for MSI data + */ + +#define MSI_DATA_VECTOR_SHIFT 0 +#define MSI_DATA_VECTOR_MASK 0x000000ff +#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & \ + MSI_DATA_VECTOR_MASK) + +#define MSI_DATA_DELIVERY_MODE_SHIFT 8 +#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT) +#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT) + +#define MSI_DATA_LEVEL_SHIFT 14 +#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT) +#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT) + +#define MSI_DATA_TRIGGER_SHIFT 15 +#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT) +#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT) + +/* + * Shift/mask fields for msi address + */ + +#define MSI_ADDR_BASE_HI 0 +#define MSI_ADDR_BASE_LO 0xfee00000 + +#define MSI_ADDR_DEST_MODE_SHIFT 2 +#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT) +#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT) + +#define MSI_ADDR_REDIRECTION_SHIFT 3 +#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) +#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) + +#define MSI_ADDR_DEST_ID_SHIFT 12 +#define MSI_ADDR_DEST_ID_MASK 0x00ffff0 +#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \ + MSI_ADDR_DEST_ID_MASK) + +#endif /* ASM_RMI_MSIDEF_H */ diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h index 5cceb746f08..868013e62f3 100644 --- a/arch/mips/include/asm/netlogic/xlr/pic.h +++ b/arch/mips/include/asm/netlogic/xlr/pic.h @@ -193,39 +193,72 @@ /* end XLS */ #ifndef __ASSEMBLY__ -static inline void pic_send_ipi(u32 ipi) + +#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ + ((irq) <= PIC_TIMER_7_IRQ)) +#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ + ((irq) <= PIC_IRT_LAST_IRQ)) + +static inline int +nlm_irq_to_irt(int irq) { - nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + if (PIC_IRQ_IS_IRT(irq) == 0) + return -1; - netlogic_write_reg(mmio, PIC_IPI, ipi); + return PIC_IRQ_TO_INTR(irq); } -static inline u32 pic_read_control(void) +static inline int +nlm_irt_to_irq(int irt) { - nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); - return netlogic_read_reg(mmio, PIC_CTRL); + return PIC_INTR_TO_IRQ(irt); } -static inline void pic_write_control(u32 control) +static inline void +nlm_pic_enable_irt(uint64_t base, int irt) { - nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + uint32_t reg; - netlogic_write_reg(mmio, PIC_CTRL, control); + reg = nlm_read_reg(base, PIC_IRT_1(irt)); + nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31)); } -static inline void pic_update_control(u32 control) +static inline void +nlm_pic_disable_irt(uint64_t base, int irt) { - nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); + uint32_t reg; - netlogic_write_reg(mmio, PIC_CTRL, - (control | netlogic_read_reg(mmio, PIC_CTRL))); + reg = nlm_read_reg(base, PIC_IRT_1(irt)); + nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31)); } -#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ - ((irq) <= PIC_TIMER_7_IRQ)) -#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ - ((irq) <= PIC_IRT_LAST_IRQ)) -#endif +static inline void +nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) +{ + unsigned int tid, pid; + + tid = hwt & 0x3; + pid = (hwt >> 2) & 0x07; + nlm_write_reg(base, PIC_IPI, + (pid << 20) | (tid << 16) | (nmi << 8) | irq); +} + +static inline void +nlm_pic_ack(uint64_t base, int irt) +{ + nlm_write_reg(base, PIC_INT_ACK, 1u << irt); +} +static inline void +nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt) +{ + nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt)); + /* local scheduling, invalid, level by default */ + nlm_write_reg(base, PIC_IRT_1(irt), + (1 << 30) | (1 << 6) | irq); +} + +extern uint64_t nlm_pic_base; +#endif #endif /* _ASM_NLM_XLR_PIC_H */ diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h index 3e6372692a0..ff4a17b0bf7 100644 --- a/arch/mips/include/asm/netlogic/xlr/xlr.h +++ b/arch/mips/include/asm/netlogic/xlr/xlr.h @@ -40,17 +40,8 @@ struct uart_port; unsigned int nlm_xlr_uart_in(struct uart_port *, int); void nlm_xlr_uart_out(struct uart_port *, int, int); -/* SMP support functions */ -struct irq_desc; -void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc); -void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc); -int nlm_wakeup_secondary_cpus(u32 wakeup_mask); -void nlm_smp_irq_init(void); -void nlm_boot_smp_nmi(void); -void prom_pre_boot_secondary_cpus(void); - -extern struct plat_smp_ops nlm_smp_ops; -extern unsigned long nlm_common_ebase; +/* SMP helpers */ +void xlr_wakeup_secondary_cpus(void); /* XLS B silicon "Rook" */ static inline unsigned int nlm_chip_is_xls_b(void) |