diff options
Diffstat (limited to 'arch')
800 files changed, 12444 insertions, 5534 deletions
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 943fe6930f7..47f63d48014 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -8,6 +8,9 @@ config ALPHA select HAVE_IRQ_WORK select HAVE_PERF_EVENTS select HAVE_DMA_ATTRS + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE + select AUTO_IRQ_AFFINITY if SMP help The Alpha is a 64-bit general-purpose processor designed and marketed by the Digital Equipment Corporation of blessed memory, @@ -68,19 +71,6 @@ config GENERIC_IOMAP bool default n -config GENERIC_HARDIRQS - bool - default y - -config GENERIC_IRQ_PROBE - bool - default y - -config AUTO_IRQ_AFFINITY - bool - depends on SMP - default y - source "init/Kconfig" source "kernel/Kconfig.freezer" diff --git a/arch/alpha/include/asm/io.h b/arch/alpha/include/asm/io.h index eda9b909aa0..56ff9650135 100644 --- a/arch/alpha/include/asm/io.h +++ b/arch/alpha/include/asm/io.h @@ -37,8 +37,9 @@ */ extern inline void __set_hae(unsigned long new_hae) { - unsigned long flags; - local_irq_save(flags); + unsigned long flags = swpipl(IPL_MAX); + + barrier(); alpha_mv.hae_cache = new_hae; *alpha_mv.hae_register = new_hae; @@ -46,7 +47,8 @@ extern inline void __set_hae(unsigned long new_hae) /* Re-read to make sure it was written. */ new_hae = *alpha_mv.hae_register; - local_irq_restore(flags); + setipl(flags); + barrier(); } extern inline void set_hae(unsigned long new_hae) diff --git a/arch/alpha/kernel/Makefile b/arch/alpha/kernel/Makefile index 1ee9b5b629b..9bb7b858ed2 100644 --- a/arch/alpha/kernel/Makefile +++ b/arch/alpha/kernel/Makefile @@ -3,8 +3,8 @@ # extra-y := head.o vmlinux.lds -EXTRA_AFLAGS := $(KBUILD_CFLAGS) -EXTRA_CFLAGS := -Werror -Wno-sign-compare +asflags-y := $(KBUILD_CFLAGS) +ccflags-y := -Werror -Wno-sign-compare obj-y := entry.o traps.o process.o init_task.o osf_sys.o irq.o \ irq_alpha.o signal.o setup.o ptrace.o time.o \ diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c index fe912984d9b..9ab234f48dd 100644 --- a/arch/alpha/kernel/irq.c +++ b/arch/alpha/kernel/irq.c @@ -44,10 +44,11 @@ static char irq_user_affinity[NR_IRQS]; int irq_select_affinity(unsigned int irq) { + struct irq_desc *desc = irq_to_desc[irq]; static int last_cpu; int cpu = last_cpu + 1; - if (!irq_desc[irq].chip->set_affinity || irq_user_affinity[irq]) + if (!desc || !get_irq_desc_chip(desc)->set_affinity || irq_user_affinity[irq]) return 1; while (!cpu_possible(cpu) || @@ -55,8 +56,8 @@ int irq_select_affinity(unsigned int irq) cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0); last_cpu = cpu; - cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu)); - irq_desc[irq].chip->set_affinity(irq, cpumask_of(cpu)); + cpumask_copy(desc->affinity, cpumask_of(cpu)); + get_irq_desc_chip(desc)->set_affinity(irq, cpumask_of(cpu)); return 0; } #endif /* CONFIG_SMP */ @@ -67,6 +68,7 @@ show_interrupts(struct seq_file *p, void *v) int j; int irq = *(loff_t *) v; struct irqaction * action; + struct irq_desc *desc; unsigned long flags; #ifdef CONFIG_SMP @@ -79,8 +81,13 @@ show_interrupts(struct seq_file *p, void *v) #endif if (irq < ACTUAL_NR_IRQS) { - raw_spin_lock_irqsave(&irq_desc[irq].lock, flags); - action = irq_desc[irq].action; + desc = irq_to_desc(irq); + + if (!desc) + return 0; + + raw_spin_lock_irqsave(&desc->lock, flags); + action = desc->action; if (!action) goto unlock; seq_printf(p, "%3d: ", irq); @@ -90,7 +97,7 @@ show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(irq, j)); #endif - seq_printf(p, " %14s", irq_desc[irq].chip->name); + seq_printf(p, " %14s", get_irq_desc_chip(desc)->name); seq_printf(p, " %c%s", (action->flags & IRQF_DISABLED)?'+':' ', action->name); @@ -103,7 +110,7 @@ show_interrupts(struct seq_file *p, void *v) seq_putc(p, '\n'); unlock: - raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags); + raw_spin_unlock_irqrestore(&desc->lock, flags); } else if (irq == ACTUAL_NR_IRQS) { #ifdef CONFIG_SMP seq_puts(p, "IPI: "); @@ -142,8 +149,10 @@ handle_irq(int irq) * handled by some other CPU. (or is disabled) */ static unsigned int illegal_count=0; + struct irq_desc *desc = irq_to_desc(irq); - if ((unsigned) irq > ACTUAL_NR_IRQS && illegal_count < MAX_ILLEGAL_IRQS ) { + if (!desc || ((unsigned) irq > ACTUAL_NR_IRQS && + illegal_count < MAX_ILLEGAL_IRQS)) { irq_err_count++; illegal_count++; printk(KERN_CRIT "device_interrupt: invalid interrupt %d\n", @@ -151,14 +160,14 @@ handle_irq(int irq) return; } - irq_enter(); /* - * __do_IRQ() must be called with IPL_MAX. Note that we do not + * From here we must proceed with IPL_MAX. Note that we do not * explicitly enable interrupts afterwards - some MILO PALcode * (namely LX164 one) seems to have severe problems with RTI * at IPL 0. */ local_irq_disable(); - __do_IRQ(irq); + irq_enter(); + generic_handle_irq_desc(irq, desc); irq_exit(); } diff --git a/arch/alpha/kernel/irq_alpha.c b/arch/alpha/kernel/irq_alpha.c index 4c8bb374eb0..2d0679b6093 100644 --- a/arch/alpha/kernel/irq_alpha.c +++ b/arch/alpha/kernel/irq_alpha.c @@ -219,31 +219,23 @@ process_mcheck_info(unsigned long vector, unsigned long la_ptr, * processed by PALcode, and comes in via entInt vector 1. */ -static void rtc_enable_disable(unsigned int irq) { } -static unsigned int rtc_startup(unsigned int irq) { return 0; } - struct irqaction timer_irqaction = { .handler = timer_interrupt, .flags = IRQF_DISABLED, .name = "timer", }; -static struct irq_chip rtc_irq_type = { - .name = "RTC", - .startup = rtc_startup, - .shutdown = rtc_enable_disable, - .enable = rtc_enable_disable, - .disable = rtc_enable_disable, - .ack = rtc_enable_disable, - .end = rtc_enable_disable, -}; - void __init init_rtc_irq(void) { - irq_desc[RTC_IRQ].status = IRQ_DISABLED; - irq_desc[RTC_IRQ].chip = &rtc_irq_type; - setup_irq(RTC_IRQ, &timer_irqaction); + struct irq_desc *desc = irq_to_desc(RTC_IRQ); + + if (desc) { + desc->status |= IRQ_DISABLED; + set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip, + handle_simple_irq, "RTC"); + setup_irq(RTC_IRQ, &timer_irqaction); + } } /* Dummy irqactions. */ diff --git a/arch/alpha/kernel/irq_i8259.c b/arch/alpha/kernel/irq_i8259.c index 83a9ac28089..956ea0ed169 100644 --- a/arch/alpha/kernel/irq_i8259.c +++ b/arch/alpha/kernel/irq_i8259.c @@ -69,28 +69,11 @@ i8259a_mask_and_ack_irq(unsigned int irq) spin_unlock(&i8259_irq_lock); } -unsigned int -i8259a_startup_irq(unsigned int irq) -{ - i8259a_enable_irq(irq); - return 0; /* never anything pending */ -} - -void -i8259a_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - i8259a_enable_irq(irq); -} - struct irq_chip i8259a_irq_type = { .name = "XT-PIC", - .startup = i8259a_startup_irq, - .shutdown = i8259a_disable_irq, - .enable = i8259a_enable_irq, - .disable = i8259a_disable_irq, - .ack = i8259a_mask_and_ack_irq, - .end = i8259a_end_irq, + .unmask = i8259a_enable_irq, + .mask = i8259a_disable_irq, + .mask_ack = i8259a_mask_and_ack_irq, }; void __init @@ -107,8 +90,7 @@ init_i8259a_irqs(void) outb(0xff, 0xA1); /* mask all of 8259A-2 */ for (i = 0; i < 16; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].chip = &i8259a_irq_type; + set_irq_chip_and_handler(i, &i8259a_irq_type, handle_level_irq); } setup_irq(2, &cascade); diff --git a/arch/alpha/kernel/irq_pyxis.c b/arch/alpha/kernel/irq_pyxis.c index 989ce46a0cf..2863458c853 100644 --- a/arch/alpha/kernel/irq_pyxis.c +++ b/arch/alpha/kernel/irq_pyxis.c @@ -40,20 +40,6 @@ pyxis_disable_irq(unsigned int irq) pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16))); } -static unsigned int -pyxis_startup_irq(unsigned int irq) -{ - pyxis_enable_irq(irq); - return 0; -} - -static void -pyxis_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - pyxis_enable_irq(irq); -} - static void pyxis_mask_and_ack_irq(unsigned int irq) { @@ -72,12 +58,9 @@ pyxis_mask_and_ack_irq(unsigned int irq) static struct irq_chip pyxis_irq_type = { .name = "PYXIS", - .startup = pyxis_startup_irq, - .shutdown = pyxis_disable_irq, - .enable = pyxis_enable_irq, - .disable = pyxis_disable_irq, - .ack = pyxis_mask_and_ack_irq, - .end = pyxis_end_irq, + .mask_ack = pyxis_mask_and_ack_irq, + .mask = pyxis_disable_irq, + .unmask = pyxis_enable_irq, }; void @@ -119,8 +102,8 @@ init_pyxis_irqs(unsigned long ignore_mask) for (i = 16; i < 48; ++i) { if ((ignore_mask >> i) & 1) continue; - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].chip = &pyxis_irq_type; + set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq); + irq_to_desc(i)->status |= IRQ_LEVEL; } setup_irq(16+7, &isa_cascade_irqaction); diff --git a/arch/alpha/kernel/irq_srm.c b/arch/alpha/kernel/irq_srm.c index d63e93e1e8b..0e57e828b41 100644 --- a/arch/alpha/kernel/irq_srm.c +++ b/arch/alpha/kernel/irq_srm.c @@ -33,29 +33,12 @@ srm_disable_irq(unsigned int irq) spin_unlock(&srm_irq_lock); } -static unsigned int -srm_startup_irq(unsigned int irq) -{ - srm_enable_irq(irq); - return 0; -} - -static void -srm_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - srm_enable_irq(irq); -} - /* Handle interrupts from the SRM, assuming no additional weirdness. */ static struct irq_chip srm_irq_type = { .name = "SRM", - .startup = srm_startup_irq, - .shutdown = srm_disable_irq, - .enable = srm_enable_irq, - .disable = srm_disable_irq, - .ack = srm_disable_irq, - .end = srm_end_irq, + .unmask = srm_enable_irq, + .mask = srm_disable_irq, + .mask_ack = srm_disable_irq, }; void __init @@ -68,8 +51,8 @@ init_srm_irqs(long max, unsigned long ignore_mask) for (i = 16; i < max; ++i) { if (i < 64 && ((ignore_mask >> i) & 1)) continue; - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].chip = &srm_irq_type; + set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq); + irq_to_desc(i)->status |= IRQ_LEVEL; } } diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c index 547e8b84b2f..fe698b5045e 100644 --- a/arch/alpha/kernel/osf_sys.c +++ b/arch/alpha/kernel/osf_sys.c @@ -951,9 +951,6 @@ SYSCALL_DEFINE2(osf_utimes, const char __user *, filename, return do_utimes(AT_FDCWD, filename, tvs ? tv : NULL, 0); } -#define MAX_SELECT_SECONDS \ - ((unsigned long) (MAX_SCHEDULE_TIMEOUT / HZ)-1) - SYSCALL_DEFINE5(osf_select, int, n, fd_set __user *, inp, fd_set __user *, outp, fd_set __user *, exp, struct timeval32 __user *, tvp) { diff --git a/arch/alpha/kernel/sys_alcor.c b/arch/alpha/kernel/sys_alcor.c index 20a30b8b965..7bef6176823 100644 --- a/arch/alpha/kernel/sys_alcor.c +++ b/arch/alpha/kernel/sys_alcor.c @@ -65,13 +65,6 @@ alcor_mask_and_ack_irq(unsigned int irq) *(vuip)GRU_INT_CLEAR = 0; mb(); } -static unsigned int -alcor_startup_irq(unsigned int irq) -{ - alcor_enable_irq(irq); - return 0; -} - static void alcor_isa_mask_and_ack_irq(unsigned int irq) { @@ -82,21 +75,11 @@ alcor_isa_mask_and_ack_irq(unsigned int irq) *(vuip)GRU_INT_CLEAR = 0; mb(); } -static void -alcor_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - alcor_enable_irq(irq); -} - static struct irq_chip alcor_irq_type = { .name = "ALCOR", - .startup = alcor_startup_irq, - .shutdown = alcor_disable_irq, - .enable = alcor_enable_irq, - .disable = alcor_disable_irq, - .ack = alcor_mask_and_ack_irq, - .end = alcor_end_irq, + .unmask = alcor_enable_irq, + .mask = alcor_disable_irq, + .mask_ack = alcor_mask_and_ack_irq, }; static void @@ -142,8 +125,8 @@ alcor_init_irq(void) on while IRQ probing. */ if (i >= 16+20 && i <= 16+30) continue; - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].chip = &alcor_irq_type; + set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq); + irq_to_desc(i)->status |= IRQ_LEVEL; } i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq; diff --git a/arch/alpha/kernel/sys_cabriolet.c b/arch/alpha/kernel/sys_cabriolet.c index 14c8898d19e..b0c916493ae 100644 --- a/arch/alpha/kernel/sys_cabriolet.c +++ b/arch/alpha/kernel/sys_cabriolet.c @@ -57,28 +57,11 @@ cabriolet_disable_irq(unsigned int irq) cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq); } -static unsigned int -cabriolet_startup_irq(unsigned int irq) -{ - cabriolet_enable_irq(irq); - return 0; /* never anything pending */ -} - -static void -cabriolet_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - cabriolet_enable_irq(irq); -} - static struct irq_chip cabriolet_irq_type = { .name = "CABRIOLET", - .startup = cabriolet_startup_irq, - .shutdown = cabriolet_disable_irq, - .enable = cabriolet_enable_irq, - .disable = cabriolet_disable_irq, - .ack = cabriolet_disable_irq, - .end = cabriolet_end_irq, + .unmask = cabriolet_enable_irq, + .mask = cabriolet_disable_irq, + .mask_ack = cabriolet_disable_irq, }; static void @@ -122,8 +105,9 @@ common_init_irq(void (*srm_dev_int)(unsigned long v)) outb(0xff, 0x806); for (i = 16; i < 35; ++i) { - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].chip = &cabriolet_irq_type; + set_irq_chip_and_handler(i, &cabriolet_irq_type, + handle_level_irq); + irq_to_desc(i)->status |= IRQ_LEVEL; } } diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c index 4026502ab70..edad5f759cc 100644 --- a/arch/alpha/kernel/sys_dp264.c +++ b/arch/alpha/kernel/sys_dp264.c @@ -115,20 +115,6 @@ dp264_disable_irq(unsigned int irq) spin_unlock(&dp264_irq_lock); } -static unsigned int -dp264_startup_irq(unsigned int irq) -{ - dp264_enable_irq(irq); - return 0; /* never anything pending */ -} - -static void -dp264_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - dp264_enable_irq(irq); -} - static void clipper_enable_irq(unsigned int irq) { @@ -147,20 +133,6 @@ clipper_disable_irq(unsigned int irq) spin_unlock(&dp264_irq_lock); } -static unsigned int -clipper_startup_irq(unsigned int irq) -{ - clipper_enable_irq(irq); - return 0; /* never anything pending */ -} - -static void -clipper_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - clipper_enable_irq(irq); -} - static void cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) { @@ -200,23 +172,17 @@ clipper_set_affinity(unsigned int irq, const struct cpumask *affinity) static struct irq_chip dp264_irq_type = { .name = "DP264", - .startup = dp264_startup_irq, - .shutdown = dp264_disable_irq, - .enable = dp264_enable_irq, - .disable = dp264_disable_irq, - .ack = dp264_disable_irq, - .end = dp264_end_irq, + .unmask = dp264_enable_irq, + .mask = dp264_disable_irq, + .mask_ack = dp264_disable_irq, .set_affinity = dp264_set_affinity, }; static struct irq_chip clipper_irq_type = { .name = "CLIPPER", - .startup = clipper_startup_irq, - .shutdown = clipper_disable_irq, - .enable = clipper_enable_irq, - .disable = clipper_disable_irq, - .ack = clipper_disable_irq, - .end = clipper_end_irq, + .unmask = clipper_enable_irq, + .mask = clipper_disable_irq, + .mask_ack = clipper_disable_irq, .set_affinity = clipper_set_affinity, }; @@ -302,8 +268,8 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax) { long i; for (i = imin; i <= imax; ++i) { - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].chip = ops; + irq_to_desc(i)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(i, ops, handle_level_irq); } } diff --git a/arch/alpha/kernel/sys_eb64p.c b/arch/alpha/kernel/sys_eb64p.c index df2090ce5e7..ae5f29d127b 100644 --- a/arch/alpha/kernel/sys_eb64p.c +++ b/arch/alpha/kernel/sys_eb64p.c @@ -55,28 +55,11 @@ eb64p_disable_irq(unsigned int irq) eb64p_update_irq_hw(irq, cached_irq_mask |= 1 << irq); } -static unsigned int -eb64p_startup_irq(unsigned int irq) -{ - eb64p_enable_irq(irq); - return 0; /* never anything pending */ -} - -static void -eb64p_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - eb64p_enable_irq(irq); -} - static struct irq_chip eb64p_irq_type = { .name = "EB64P", - .startup = eb64p_startup_irq, - .shutdown = eb64p_disable_irq, - .enable = eb64p_enable_irq, - .disable = eb64p_disable_irq, - .ack = eb64p_disable_irq, - .end = eb64p_end_irq, + .unmask = eb64p_enable_irq, + .mask = eb64p_disable_irq, + .mask_ack = eb64p_disable_irq, }; static void @@ -135,8 +118,8 @@ eb64p_init_irq(void) init_i8259a_irqs(); for (i = 16; i < 32; ++i) { - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].chip = &eb64p_irq_type; + irq_to_desc(i)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq); } common_init_isa_dma(); diff --git a/arch/alpha/kernel/sys_eiger.c b/arch/alpha/kernel/sys_eiger.c index 3ca1dbcf404..1121bc5c6c6 100644 --- a/arch/alpha/kernel/sys_eiger.c +++ b/arch/alpha/kernel/sys_eiger.c @@ -66,28 +66,11 @@ eiger_disable_irq(unsigned int irq) eiger_update_irq_hw(irq, mask); } -static unsigned int -eiger_startup_irq(unsigned int irq) -{ - eiger_enable_irq(irq); - return 0; /* never anything pending */ -} - -static void -eiger_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - eiger_enable_irq(irq); -} - static struct irq_chip eiger_irq_type = { .name = "EIGER", - .startup = eiger_startup_irq, - .shutdown = eiger_disable_irq, - .enable = eiger_enable_irq, - .disable = eiger_disable_irq, - .ack = eiger_disable_irq, - .end = eiger_end_irq, + .unmask = eiger_enable_irq, + .mask = eiger_disable_irq, + .mask_ack = eiger_disable_irq, }; static void @@ -153,8 +136,8 @@ eiger_init_irq(void) init_i8259a_irqs(); for (i = 16; i < 128; ++i) { - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].chip = &eiger_irq_type; + irq_to_desc(i)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq); } } diff --git a/arch/alpha/kernel/sys_jensen.c b/arch/alpha/kernel/sys_jensen.c index 7a7ae36fff9..34f55e03d33 100644 --- a/arch/alpha/kernel/sys_jensen.c +++ b/arch/alpha/kernel/sys_jensen.c @@ -62,30 +62,6 @@ * world. */ -static unsigned int -jensen_local_startup(unsigned int irq) -{ - /* the parport is really hw IRQ 1, silly Jensen. */ - if (irq == 7) - i8259a_startup_irq(1); - else - /* - * For all true local interrupts, set the flag that prevents - * the IPL from being dropped during handler processing. - */ - if (irq_desc[irq].action) - irq_desc[irq].action->flags |= IRQF_DISABLED; - return 0; -} - -static void -jensen_local_shutdown(unsigned int irq) -{ - /* the parport is really hw IRQ 1, silly Jensen. */ - if (irq == 7) - i8259a_disable_irq(1); -} - static void jensen_local_enable(unsigned int irq) { @@ -103,29 +79,18 @@ jensen_local_disable(unsigned int irq) } static void -jensen_local_ack(unsigned int irq) +jensen_local_mask_ack(unsigned int irq) { /* the parport is really hw IRQ 1, silly Jensen. */ if (irq == 7) i8259a_mask_and_ack_irq(1); } -static void -jensen_local_end(unsigned int irq) -{ - /* the parport is really hw IRQ 1, silly Jensen. */ - if (irq == 7) - i8259a_end_irq(1); -} - static struct irq_chip jensen_local_irq_type = { .name = "LOCAL", - .startup = jensen_local_startup, - .shutdown = jensen_local_shutdown, - .enable = jensen_local_enable, - .disable = jensen_local_disable, - .ack = jensen_local_ack, - .end = jensen_local_end, + .unmask = jensen_local_enable, + .mask = jensen_local_disable, + .mask_ack = jensen_local_mask_ack, }; static void @@ -158,7 +123,7 @@ jensen_device_interrupt(unsigned long vector) } /* If there is no handler yet... */ - if (irq_desc[irq].action == NULL) { + if (!irq_has_action(irq)) { /* If it is a local interrupt that cannot be masked... */ if (vector >= 0x900) { @@ -206,11 +171,11 @@ jensen_init_irq(void) { init_i8259a_irqs(); - irq_desc[1].chip = &jensen_local_irq_type; - irq_desc[4].chip = &jensen_local_irq_type; - irq_desc[3].chip = &jensen_local_irq_type; - irq_desc[7].chip = &jensen_local_irq_type; - irq_desc[9].chip = &jensen_local_irq_type; + set_irq_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq); + set_irq_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq); + set_irq_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq); + set_irq_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq); + set_irq_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq); common_init_isa_dma(); } diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c index 0bb3b5c4f69..2bfc9f1b1dd 100644 --- a/arch/alpha/kernel/sys_marvel.c +++ b/arch/alpha/kernel/sys_marvel.c @@ -143,20 +143,6 @@ io7_disable_irq(unsigned int irq) spin_unlock(&io7->irq_lock); } -static unsigned int -io7_startup_irq(unsigned int irq) -{ - io7_enable_irq(irq); - return 0; /* never anything pending */ -} - -static void -io7_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - io7_enable_irq(irq); -} - static void marvel_irq_noop(unsigned int irq) { @@ -171,32 +157,22 @@ marvel_irq_noop_return(unsigned int irq) static struct irq_chip marvel_legacy_irq_type = { .name = "LEGACY", - .startup = marvel_irq_noop_return, - .shutdown = marvel_irq_noop, - .enable = marvel_irq_noop, - .disable = marvel_irq_noop, - .ack = marvel_irq_noop, - .end = marvel_irq_noop, + .mask = marvel_irq_noop, + .unmask = marvel_irq_noop, }; static struct irq_chip io7_lsi_irq_type = { .name = "LSI", - .startup = io7_startup_irq, - .shutdown = io7_disable_irq, - .enable = io7_enable_irq, - .disable = io7_disable_irq, - .ack = io7_disable_irq, - .end = io7_end_irq, + .unmask = io7_enable_irq, + .mask = io7_disable_irq, + .mask_ack = io7_disable_irq, }; static struct irq_chip io7_msi_irq_type = { .name = "MSI", - .startup = io7_startup_irq, - .shutdown = io7_disable_irq, - .enable = io7_enable_irq, - .disable = io7_disable_irq, + .unmask = io7_enable_irq, + .mask = io7_disable_irq, .ack = marvel_irq_noop, - .end = io7_end_irq, }; static void @@ -304,8 +280,8 @@ init_io7_irqs(struct io7 *io7, /* Set up the lsi irqs. */ for (i = 0; i < 128; ++i) { - irq_desc[base + i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[base + i].chip = lsi_ops; + irq_to_desc(base + i)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq); } /* Disable the implemented irqs in hardware. */ @@ -318,8 +294,8 @@ init_io7_irqs(struct io7 *io7, /* Set up the msi irqs. */ for (i = 128; i < (128 + 512); ++i) { - irq_desc[base + i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[base + i].chip = msi_ops; + irq_to_desc(base + i)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq); } for (i = 0; i < 16; ++i) @@ -336,8 +312,8 @@ marvel_init_irq(void) /* Reserve the legacy irqs. */ for (i = 0; i < 16; ++i) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].chip = &marvel_legacy_irq_type; + set_irq_chip_and_handler(i, &marvel_legacy_irq_type, + handle_level_irq); } /* Init the io7 irqs. */ diff --git a/arch/alpha/kernel/sys_mikasa.c b/arch/alpha/kernel/sys_mikasa.c index ee886516981..bcc1639e8ef 100644 --- a/arch/alpha/kernel/sys_mikasa.c +++ b/arch/alpha/kernel/sys_mikasa.c @@ -54,28 +54,11 @@ mikasa_disable_irq(unsigned int irq) mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16))); } -static unsigned int -mikasa_startup_irq(unsigned int irq) -{ - mikasa_enable_irq(irq); - return 0; -} - -static void -mikasa_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - mikasa_enable_irq(irq); -} - static struct irq_chip mikasa_irq_type = { .name = "MIKASA", - .startup = mikasa_startup_irq, - .shutdown = mikasa_disable_irq, - .enable = mikasa_enable_irq, - .disable = mikasa_disable_irq, - .ack = mikasa_disable_irq, - .end = mikasa_end_irq, + .unmask = mikasa_enable_irq, + .mask = mikasa_disable_irq, + .mask_ack = mikasa_disable_irq, }; static void @@ -115,8 +98,8 @@ mikasa_init_irq(void) mikasa_update_irq_hw(0); for (i = 16; i < 32; ++i) { - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].chip = &mikasa_irq_type; + irq_to_desc(i)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq); } init_i8259a_irqs(); diff --git a/arch/alpha/kernel/sys_noritake.c b/arch/alpha/kernel/sys_noritake.c index 86503fe73a8..e88f4ae1260 100644 --- a/arch/alpha/kernel/sys_noritake.c +++ b/arch/alpha/kernel/sys_noritake.c @@ -59,28 +59,11 @@ noritake_disable_irq(unsigned int irq) noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16))); } -static unsigned int -noritake_startup_irq(unsigned int irq) -{ - noritake_enable_irq(irq); - return 0; -} - -static void -noritake_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - noritake_enable_irq(irq); -} - static struct irq_chip noritake_irq_type = { .name = "NORITAKE", - .startup = noritake_startup_irq, - .shutdown = noritake_disable_irq, - .enable = noritake_enable_irq, - .disable = noritake_disable_irq, - .ack = noritake_disable_irq, - .end = noritake_end_irq, + .unmask = noritake_enable_irq, + .mask = noritake_disable_irq, + .mask_ack = noritake_disable_irq, }; static void @@ -144,8 +127,8 @@ noritake_init_irq(void) outw(0, 0x54c); for (i = 16; i < 48; ++i) { - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].chip = &noritake_irq_type; + irq_to_desc(i)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq); } init_i8259a_irqs(); diff --git a/arch/alpha/kernel/sys_rawhide.c b/arch/alpha/kernel/sys_rawhide.c index 26c322bf89e..6a51364dd1c 100644 --- a/arch/alpha/kernel/sys_rawhide.c +++ b/arch/alpha/kernel/sys_rawhide.c @@ -121,28 +121,11 @@ rawhide_mask_and_ack_irq(unsigned int irq) spin_unlock(&rawhide_irq_lock); } -static unsigned int -rawhide_startup_irq(unsigned int irq) -{ - rawhide_enable_irq(irq); - return 0; -} - -static void -rawhide_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - rawhide_enable_irq(irq); -} - static struct irq_chip rawhide_irq_type = { .name = "RAWHIDE", - .startup = rawhide_startup_irq, - .shutdown = rawhide_disable_irq, - .enable = rawhide_enable_irq, - .disable = rawhide_disable_irq, - .ack = rawhide_mask_and_ack_irq, - .end = rawhide_end_irq, + .unmask = rawhide_enable_irq, + .mask = rawhide_disable_irq, + .mask_ack = rawhide_mask_and_ack_irq, }; static void @@ -194,8 +177,8 @@ rawhide_init_irq(void) } for (i = 16; i < 128; ++i) { - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].chip = &rawhide_irq_type; + irq_to_desc(i)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq); } init_i8259a_irqs(); diff --git a/arch/alpha/kernel/sys_rx164.c b/arch/alpha/kernel/sys_rx164.c index be161129eab..89e7e37ec84 100644 --- a/arch/alpha/kernel/sys_rx164.c +++ b/arch/alpha/kernel/sys_rx164.c @@ -58,28 +58,11 @@ rx164_disable_irq(unsigned int irq) rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16))); } -static unsigned int -rx164_startup_irq(unsigned int irq) -{ - rx164_enable_irq(irq); - return 0; -} - -static void -rx164_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - rx164_enable_irq(irq); -} - static struct irq_chip rx164_irq_type = { .name = "RX164", - .startup = rx164_startup_irq, - .shutdown = rx164_disable_irq, - .enable = rx164_enable_irq, - .disable = rx164_disable_irq, - .ack = rx164_disable_irq, - .end = rx164_end_irq, + .unmask = rx164_enable_irq, + .mask = rx164_disable_irq, + .mask_ack = rx164_disable_irq, }; static void @@ -116,8 +99,8 @@ rx164_init_irq(void) rx164_update_irq_hw(0); for (i = 16; i < 40; ++i) { - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].chip = &rx164_irq_type; + irq_to_desc(i)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq); } init_i8259a_irqs(); diff --git a/arch/alpha/kernel/sys_sable.c b/arch/alpha/kernel/sys_sable.c index b2abe27a23c..5c4423d1b06 100644 --- a/arch/alpha/kernel/sys_sable.c +++ b/arch/alpha/kernel/sys_sable.c @@ -474,20 +474,6 @@ sable_lynx_disable_irq(unsigned int irq) #endif } -static unsigned int -sable_lynx_startup_irq(unsigned int irq) -{ - sable_lynx_enable_irq(irq); - return 0; -} - -static void -sable_lynx_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - sable_lynx_enable_irq(irq); -} - static void sable_lynx_mask_and_ack_irq(unsigned int irq) { @@ -503,12 +489,9 @@ sable_lynx_mask_and_ack_irq(unsigned int irq) static struct irq_chip sable_lynx_irq_type = { .name = "SABLE/LYNX", - .startup = sable_lynx_startup_irq, - .shutdown = sable_lynx_disable_irq, - .enable = sable_lynx_enable_irq, - .disable = sable_lynx_disable_irq, - .ack = sable_lynx_mask_and_ack_irq, - .end = sable_lynx_end_irq, + .unmask = sable_lynx_enable_irq, + .mask = sable_lynx_disable_irq, + .mask_ack = sable_lynx_mask_and_ack_irq, }; static void @@ -535,8 +518,9 @@ sable_lynx_init_irq(int nr_of_irqs) long i; for (i = 0; i < nr_of_irqs; ++i) { - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].chip = &sable_lynx_irq_type; + irq_to_desc(i)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(i, &sable_lynx_irq_type, + handle_level_irq); } common_init_isa_dma(); diff --git a/arch/alpha/kernel/sys_takara.c b/arch/alpha/kernel/sys_takara.c index 4da596b6adb..f8a1e8a862f 100644 --- a/arch/alpha/kernel/sys_takara.c +++ b/arch/alpha/kernel/sys_takara.c @@ -60,28 +60,11 @@ takara_disable_irq(unsigned int irq) takara_update_irq_hw(irq, mask); } -static unsigned int -takara_startup_irq(unsigned int irq) -{ - takara_enable_irq(irq); - return 0; /* never anything pending */ -} - -static void -takara_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - takara_enable_irq(irq); -} - static struct irq_chip takara_irq_type = { .name = "TAKARA", - .startup = takara_startup_irq, - .shutdown = takara_disable_irq, - .enable = takara_enable_irq, - .disable = takara_disable_irq, - .ack = takara_disable_irq, - .end = takara_end_irq, + .unmask = takara_enable_irq, + .mask = takara_disable_irq, + .mask_ack = takara_disable_irq, }; static void @@ -153,8 +136,8 @@ takara_init_irq(void) takara_update_irq_hw(i, -1); for (i = 16; i < 128; ++i) { - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].chip = &takara_irq_type; + irq_to_desc(i)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq); } common_init_isa_dma(); diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c index 9008d0f20c5..e02494bf5ef 100644 --- a/arch/alpha/kernel/sys_titan.c +++ b/arch/alpha/kernel/sys_titan.c @@ -129,20 +129,6 @@ titan_disable_irq(unsigned int irq) spin_unlock(&titan_irq_lock); } -static unsigned int -titan_startup_irq(unsigned int irq) -{ - titan_enable_irq(irq); - return 0; /* never anything pending */ -} - -static void -titan_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - titan_enable_irq(irq); -} - static void titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) { @@ -189,20 +175,17 @@ init_titan_irqs(struct irq_chip * ops, int imin, int imax) { long i; for (i = imin; i <= imax; ++i) { - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i].chip = ops; + irq_to_desc(i)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(i, ops, handle_level_irq); } } static struct irq_chip titan_irq_type = { - .name = "TITAN", - .startup = titan_startup_irq, - .shutdown = titan_disable_irq, - .enable = titan_enable_irq, - .disable = titan_disable_irq, - .ack = titan_disable_irq, - .end = titan_end_irq, - .set_affinity = titan_set_irq_affinity, + .name = "TITAN", + .unmask = titan_enable_irq, + .mask = titan_disable_irq, + .mask_ack = titan_disable_irq, + .set_affinity = titan_set_irq_affinity, }; static irqreturn_t diff --git a/arch/alpha/kernel/sys_wildfire.c b/arch/alpha/kernel/sys_wildfire.c index 62fd972e18e..eec52594d41 100644 --- a/arch/alpha/kernel/sys_wildfire.c +++ b/arch/alpha/kernel/sys_wildfire.c @@ -139,32 +139,11 @@ wildfire_mask_and_ack_irq(unsigned int irq) spin_unlock(&wildfire_irq_lock); } -static unsigned int -wildfire_startup_irq(unsigned int irq) -{ - wildfire_enable_irq(irq); - return 0; /* never anything pending */ -} - -static void -wildfire_end_irq(unsigned int irq) -{ -#if 0 - if (!irq_desc[irq].action) - printk("got irq %d\n", irq); -#endif - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - wildfire_enable_irq(irq); -} - static struct irq_chip wildfire_irq_type = { .name = "WILDFIRE", - .startup = wildfire_startup_irq, - .shutdown = wildfire_disable_irq, - .enable = wildfire_enable_irq, - .disable = wildfire_disable_irq, - .ack = wildfire_mask_and_ack_irq, - .end = wildfire_end_irq, + .unmask = wildfire_enable_irq, + .mask = wildfire_disable_irq, + .mask_ack = wildfire_mask_and_ack_irq, }; static void __init @@ -198,15 +177,18 @@ wildfire_init_irq_per_pca(int qbbno, int pcano) for (i = 0; i < 16; ++i) { if (i == 2) continue; - irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i+irq_bias].chip = &wildfire_irq_type; + irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type, + handle_level_irq); } - irq_desc[36+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[36+irq_bias].chip = &wildfire_irq_type; + irq_to_desc(36+irq_bias)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type, + handle_level_irq); for (i = 40; i < 64; ++i) { - irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; - irq_desc[i+irq_bias].chip = &wildfire_irq_type; + irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL; + set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type, + handle_level_irq); } setup_irq(32+irq_bias, &isa_enable); diff --git a/arch/alpha/lib/Makefile b/arch/alpha/lib/Makefile index 9b72c59c95b..c0a83ab62b7 100644 --- a/arch/alpha/lib/Makefile +++ b/arch/alpha/lib/Makefile @@ -2,8 +2,8 @@ # Makefile for alpha-specific library files.. # -EXTRA_AFLAGS := $(KBUILD_CFLAGS) -EXTRA_CFLAGS := -Werror +asflags-y := $(KBUILD_CFLAGS) +ccflags-y := -Werror # Many of these routines have implementations tuned for ev6. # Choose them iff we're targeting ev6 specifically. diff --git a/arch/alpha/math-emu/Makefile b/arch/alpha/math-emu/Makefile index 359ef087e69..7f467199524 100644 --- a/arch/alpha/math-emu/Makefile +++ b/arch/alpha/math-emu/Makefile @@ -2,7 +2,7 @@ # Makefile for the FPU instruction emulation. # -EXTRA_CFLAGS := -w +ccflags-y := -w obj-$(CONFIG_MATHEMU) += math-emu.o diff --git a/arch/alpha/mm/Makefile b/arch/alpha/mm/Makefile index 09399c5386c..c993d3f93cf 100644 --- a/arch/alpha/mm/Makefile +++ b/arch/alpha/mm/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux alpha-specific parts of the memory manager. # -EXTRA_CFLAGS := -Werror +ccflags-y := -Werror obj-y := init.o fault.o extable.o diff --git a/arch/alpha/oprofile/Makefile b/arch/alpha/oprofile/Makefile index 4aa56247bdc..3473de751b0 100644 --- a/arch/alpha/oprofile/Makefile +++ b/arch/alpha/oprofile/Makefile @@ -1,4 +1,4 @@ -EXTRA_CFLAGS := -Werror -Wno-sign-compare +ccflags-y := -Werror -Wno-sign-compare obj-$(CONFIG_OPROFILE) += oprofile.o diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e2f80116759..5cff165b7eb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -26,6 +26,8 @@ config ARM select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7)) select HAVE_C_RECORDMCOUNT + select HAVE_GENERIC_HARDIRQS + select HAVE_SPARSE_IRQ help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and @@ -97,10 +99,6 @@ config MCA <file:Documentation/mca.txt> (and especially the web page given there) before attempting to build an MCA bus kernel. -config GENERIC_HARDIRQS - bool - default y - config STACKTRACE_SUPPORT bool default y @@ -180,9 +178,6 @@ config FIQ config ARCH_MTD_XIP bool -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config ARM_L1_CACHE_SHIFT_6 bool help @@ -368,7 +363,7 @@ config ARCH_MXS bool "Freescale MXS-based" select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB - select COMMON_CLKDEV + select CLKDEV_LOOKUP help Support for Freescale MXS-based family of processors @@ -771,6 +766,7 @@ config ARCH_S5PV310 select ARCH_SPARSEMEM_ENABLE select GENERIC_GPIO select HAVE_CLK + select ARCH_HAS_CPUFREQ select GENERIC_CLOCKEVENTS select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_I2C if I2C @@ -1281,7 +1277,7 @@ config SMP config SMP_ON_UP bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" depends on EXPERIMENTAL - depends on SMP && !XIP + depends on SMP && !XIP_KERNEL default y help SMP kernels contain instructions which fail on non-SMP processors. @@ -1452,15 +1448,6 @@ config HW_PERF_EVENTS Enable hardware performance counter support for perf events. If disabled, perf events will use software events only. -config SPARSE_IRQ - def_bool n - help - This enables support for sparse irqs. This is useful in general - as most CPUs have a fairly sparse array of IRQ vectors, which - the irq_desc then maps directly on to. Systems with a high - number of off-chip IRQs will want to treat this as - experimental until they have been independently verified. - source "mm/Kconfig" config FORCE_MAX_ZONEORDER diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 0b89ef00133..22437721115 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -50,57 +50,56 @@ struct gic_chip_data { static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; -static inline void __iomem *gic_dist_base(unsigned int irq) +static inline void __iomem *gic_dist_base(struct irq_data *d) { - struct gic_chip_data *gic_data = get_irq_chip_data(irq); + struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); return gic_data->dist_base; } -static inline void __iomem *gic_cpu_base(unsigned int irq) +static inline void __iomem *gic_cpu_base(struct irq_data *d) { - struct gic_chip_data *gic_data = get_irq_chip_data(irq); + struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); return gic_data->cpu_base; } -static inline unsigned int gic_irq(unsigned int irq) +static inline unsigned int gic_irq(struct irq_data *d) { - struct gic_chip_data *gic_data = get_irq_chip_data(irq); - return irq - gic_data->irq_offset; + struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); + return d->irq - gic_data->irq_offset; } /* * Routines to acknowledge, disable and enable interrupts */ -static void gic_ack_irq(unsigned int irq) +static void gic_ack_irq(struct irq_data *d) { - spin_lock(&irq_controller_lock); - writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI); + writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); spin_unlock(&irq_controller_lock); } -static void gic_mask_irq(unsigned int irq) +static void gic_mask_irq(struct irq_data *d) { - u32 mask = 1 << (irq % 32); + u32 mask = 1 << (d->irq % 32); spin_lock(&irq_controller_lock); - writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4); + writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); spin_unlock(&irq_controller_lock); } -static void gic_unmask_irq(unsigned int irq) +static void gic_unmask_irq(struct irq_data *d) { - u32 mask = 1 << (irq % 32); + u32 mask = 1 << (d->irq % 32); spin_lock(&irq_controller_lock); - writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4); + writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); spin_unlock(&irq_controller_lock); } -static int gic_set_type(unsigned int irq, unsigned int type) +static int gic_set_type(struct irq_data *d, unsigned int type) { - void __iomem *base = gic_dist_base(irq); - unsigned int gicirq = gic_irq(irq); + void __iomem *base = gic_dist_base(d); + unsigned int gicirq = gic_irq(d); u32 enablemask = 1 << (gicirq % 32); u32 enableoff = (gicirq / 32) * 4; u32 confmask = 0x2 << ((gicirq % 16) * 2); @@ -143,21 +142,22 @@ static int gic_set_type(unsigned int irq, unsigned int type) } #ifdef CONFIG_SMP -static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) +static int +gic_set_cpu(struct irq_data *d, const struct cpumask *mask_val, bool force) { - void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3); - unsigned int shift = (irq % 4) * 8; + void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); + unsigned int shift = (d->irq % 4) * 8; unsigned int cpu = cpumask_first(mask_val); u32 val; struct irq_desc *desc; spin_lock(&irq_controller_lock); - desc = irq_to_desc(irq); + desc = irq_to_desc(d->irq); if (desc == NULL) { spin_unlock(&irq_controller_lock); return -EINVAL; } - desc->node = cpu; + d->node = cpu; val = readl(reg) & ~(0xff << shift); val |= 1 << (cpu + shift); writel(val, reg); @@ -175,7 +175,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) unsigned long status; /* primary controller ack'ing */ - chip->ack(irq); + chip->irq_ack(&desc->irq_data); spin_lock(&irq_controller_lock); status = readl(chip_data->cpu_base + GIC_CPU_INTACK); @@ -193,17 +193,17 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) out: /* primary controller unmasking */ - chip->unmask(irq); + chip->irq_unmask(&desc->irq_data); } static struct irq_chip gic_chip = { - .name = "GIC", - .ack = gic_ack_irq, - .mask = gic_mask_irq, - .unmask = gic_unmask_irq, - .set_type = gic_set_type, + .name = "GIC", + .irq_ack = gic_ack_irq, + .irq_mask = gic_mask_irq, + .irq_unmask = gic_unmask_irq, + .irq_set_type = gic_set_type, #ifdef CONFIG_SMP - .set_affinity = gic_set_cpu, + .irq_set_affinity = gic_set_cpu, #endif }; @@ -337,7 +337,7 @@ void __cpuinit gic_enable_ppi(unsigned int irq) local_irq_save(flags); irq_to_desc(irq)->status |= IRQ_NOPROBE; - gic_unmask_irq(irq); + gic_unmask_irq(irq_get_irq_data(irq)); local_irq_restore(flags); } diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index 665ebf7e62a..fcddd48fe9d 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c @@ -31,8 +31,10 @@ #define MAX_SLOTS 21 -static void it8152_mask_irq(unsigned int irq) +static void it8152_mask_irq(struct irq_data *d) { + unsigned int irq = d->irq; + if (irq >= IT8152_LD_IRQ(0)) { __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) | (1 << (irq - IT8152_LD_IRQ(0)))), @@ -48,8 +50,10 @@ static void it8152_mask_irq(unsigned int irq) } } -static void it8152_unmask_irq(unsigned int irq) +static void it8152_unmask_irq(struct irq_data *d) { + unsigned int irq = d->irq; + if (irq >= IT8152_LD_IRQ(0)) { __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) & ~(1 << (irq - IT8152_LD_IRQ(0)))), @@ -67,9 +71,9 @@ static void it8152_unmask_irq(unsigned int irq) static struct irq_chip it8152_irq_chip = { .name = "it8152", - .ack = it8152_mask_irq, - .mask = it8152_mask_irq, - .unmask = it8152_unmask_irq, + .irq_ack = it8152_mask_irq, + .irq_mask = it8152_mask_irq, + .irq_unmask = it8152_unmask_irq, }; void it8152_init_irq(void) diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index 9dff07c80dd..a026a6bf489 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -144,7 +144,7 @@ static void locomo_handler(unsigned int irq, struct irq_desc *desc) int req, i; /* Acknowledge the parent IRQ */ - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); /* check why this interrupt was generated */ req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00; @@ -161,33 +161,33 @@ static void locomo_handler(unsigned int irq, struct irq_desc *desc) } } -static void locomo_ack_irq(unsigned int irq) +static void locomo_ack_irq(struct irq_data *d) { } -static void locomo_mask_irq(unsigned int irq) +static void locomo_mask_irq(struct irq_data *d) { - struct locomo *lchip = get_irq_chip_data(irq); + struct locomo *lchip = irq_data_get_irq_chip_data(d); unsigned int r; r = locomo_readl(lchip->base + LOCOMO_ICR); - r &= ~(0x0010 << (irq - lchip->irq_base)); + r &= ~(0x0010 << (d->irq - lchip->irq_base)); locomo_writel(r, lchip->base + LOCOMO_ICR); } -static void locomo_unmask_irq(unsigned int irq) +static void locomo_unmask_irq(struct irq_data *d) { - struct locomo *lchip = get_irq_chip_data(irq); + struct locomo *lchip = irq_data_get_irq_chip_data(d); unsigned int r; r = locomo_readl(lchip->base + LOCOMO_ICR); - r |= (0x0010 << (irq - lchip->irq_base)); + r |= (0x0010 << (d->irq - lchip->irq_base)); locomo_writel(r, lchip->base + LOCOMO_ICR); } static struct irq_chip locomo_chip = { - .name = "LOCOMO", - .ack = locomo_ack_irq, - .mask = locomo_mask_irq, - .unmask = locomo_unmask_irq, + .name = "LOCOMO", + .irq_ack = locomo_ack_irq, + .irq_mask = locomo_mask_irq, + .irq_unmask = locomo_unmask_irq, }; static void locomo_setup_irq(struct locomo *lchip) diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index c0258a8c103..eb9796b0dab 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -210,7 +210,7 @@ sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) sa1111_writel(stat0, mapbase + SA1111_INTSTATCLR0); - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); sa1111_writel(stat1, mapbase + SA1111_INTSTATCLR1); @@ -228,35 +228,35 @@ sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) generic_handle_irq(i + sachip->irq_base); /* For level-based interrupts */ - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); } #define SA1111_IRQMASK_LO(x) (1 << (x - sachip->irq_base)) #define SA1111_IRQMASK_HI(x) (1 << (x - sachip->irq_base - 32)) -static void sa1111_ack_irq(unsigned int irq) +static void sa1111_ack_irq(struct irq_data *d) { } -static void sa1111_mask_lowirq(unsigned int irq) +static void sa1111_mask_lowirq(struct irq_data *d) { - struct sa1111 *sachip = get_irq_chip_data(irq); + struct sa1111 *sachip = irq_data_get_irq_chip_data(d); void __iomem *mapbase = sachip->base + SA1111_INTC; unsigned long ie0; ie0 = sa1111_readl(mapbase + SA1111_INTEN0); - ie0 &= ~SA1111_IRQMASK_LO(irq); + ie0 &= ~SA1111_IRQMASK_LO(d->irq); writel(ie0, mapbase + SA1111_INTEN0); } -static void sa1111_unmask_lowirq(unsigned int irq) +static void sa1111_unmask_lowirq(struct irq_data *d) { - struct sa1111 *sachip = get_irq_chip_data(irq); + struct sa1111 *sachip = irq_data_get_irq_chip_data(d); void __iomem *mapbase = sachip->base + SA1111_INTC; unsigned long ie0; ie0 = sa1111_readl(mapbase + SA1111_INTEN0); - ie0 |= SA1111_IRQMASK_LO(irq); + ie0 |= SA1111_IRQMASK_LO(d->irq); sa1111_writel(ie0, mapbase + SA1111_INTEN0); } @@ -267,11 +267,11 @@ static void sa1111_unmask_lowirq(unsigned int irq) * be triggered. In fact, its very difficult, if not impossible to get * INTSET to re-trigger the interrupt. */ -static int sa1111_retrigger_lowirq(unsigned int irq) +static int sa1111_retrigger_lowirq(struct irq_data *d) { - struct sa1111 *sachip = get_irq_chip_data(irq); + struct sa1111 *sachip = irq_data_get_irq_chip_data(d); void __iomem *mapbase = sachip->base + SA1111_INTC; - unsigned int mask = SA1111_IRQMASK_LO(irq); + unsigned int mask = SA1111_IRQMASK_LO(d->irq); unsigned long ip0; int i; @@ -279,21 +279,21 @@ static int sa1111_retrigger_lowirq(unsigned int irq) for (i = 0; i < 8; i++) { sa1111_writel(ip0 ^ mask, mapbase + SA1111_INTPOL0); sa1111_writel(ip0, mapbase + SA1111_INTPOL0); - if (sa1111_readl(mapbase + SA1111_INTSTATCLR1) & mask) + if (sa1111_readl(mapbase + SA1111_INTSTATCLR0) & mask) break; } if (i == 8) printk(KERN_ERR "Danger Will Robinson: failed to " - "re-trigger IRQ%d\n", irq); + "re-trigger IRQ%d\n", d->irq); return i == 8 ? -1 : 0; } -static int sa1111_type_lowirq(unsigned int irq, unsigned int flags) +static int sa1111_type_lowirq(struct irq_data *d, unsigned int flags) { - struct sa1111 *sachip = get_irq_chip_data(irq); + struct sa1111 *sachip = irq_data_get_irq_chip_data(d); void __iomem *mapbase = sachip->base + SA1111_INTC; - unsigned int mask = SA1111_IRQMASK_LO(irq); + unsigned int mask = SA1111_IRQMASK_LO(d->irq); unsigned long ip0; if (flags == IRQ_TYPE_PROBE) @@ -313,11 +313,11 @@ static int sa1111_type_lowirq(unsigned int irq, unsigned int flags) return 0; } -static int sa1111_wake_lowirq(unsigned int irq, unsigned int on) +static int sa1111_wake_lowirq(struct irq_data *d, unsigned int on) { - struct sa1111 *sachip = get_irq_chip_data(irq); + struct sa1111 *sachip = irq_data_get_irq_chip_data(d); void __iomem *mapbase = sachip->base + SA1111_INTC; - unsigned int mask = SA1111_IRQMASK_LO(irq); + unsigned int mask = SA1111_IRQMASK_LO(d->irq); unsigned long we0; we0 = sa1111_readl(mapbase + SA1111_WAKEEN0); @@ -332,33 +332,33 @@ static int sa1111_wake_lowirq(unsigned int irq, unsigned int on) static struct irq_chip sa1111_low_chip = { .name = "SA1111-l", - .ack = sa1111_ack_irq, - .mask = sa1111_mask_lowirq, - .unmask = sa1111_unmask_lowirq, - .retrigger = sa1111_retrigger_lowirq, - .set_type = sa1111_type_lowirq, - .set_wake = sa1111_wake_lowirq, + .irq_ack = sa1111_ack_irq, + .irq_mask = sa1111_mask_lowirq, + .irq_unmask = sa1111_unmask_lowirq, + .irq_retrigger = sa1111_retrigger_lowirq, + .irq_set_type = sa1111_type_lowirq, + .irq_set_wake = sa1111_wake_lowirq, }; -static void sa1111_mask_highirq(unsigned int irq) +static void sa1111_mask_highirq(struct irq_data *d) { - struct sa1111 *sachip = get_irq_chip_data(irq); + struct sa1111 *sachip = irq_data_get_irq_chip_data(d); void __iomem *mapbase = sachip->base + SA1111_INTC; unsigned long ie1; ie1 = sa1111_readl(mapbase + SA1111_INTEN1); - ie1 &= ~SA1111_IRQMASK_HI(irq); + ie1 &= ~SA1111_IRQMASK_HI(d->irq); sa1111_writel(ie1, mapbase + SA1111_INTEN1); } -static void sa1111_unmask_highirq(unsigned int irq) +static void sa1111_unmask_highirq(struct irq_data *d) { - struct sa1111 *sachip = get_irq_chip_data(irq); + struct sa1111 *sachip = irq_data_get_irq_chip_data(d); void __iomem *mapbase = sachip->base + SA1111_INTC; unsigned long ie1; ie1 = sa1111_readl(mapbase + SA1111_INTEN1); - ie1 |= SA1111_IRQMASK_HI(irq); + ie1 |= SA1111_IRQMASK_HI(d->irq); sa1111_writel(ie1, mapbase + SA1111_INTEN1); } @@ -369,11 +369,11 @@ static void sa1111_unmask_highirq(unsigned int irq) * be triggered. In fact, its very difficult, if not impossible to get * INTSET to re-trigger the interrupt. */ -static int sa1111_retrigger_highirq(unsigned int irq) +static int sa1111_retrigger_highirq(struct irq_data *d) { - struct sa1111 *sachip = get_irq_chip_data(irq); + struct sa1111 *sachip = irq_data_get_irq_chip_data(d); void __iomem *mapbase = sachip->base + SA1111_INTC; - unsigned int mask = SA1111_IRQMASK_HI(irq); + unsigned int mask = SA1111_IRQMASK_HI(d->irq); unsigned long ip1; int i; @@ -387,15 +387,15 @@ static int sa1111_retrigger_highirq(unsigned int irq) if (i == 8) printk(KERN_ERR "Danger Will Robinson: failed to " - "re-trigger IRQ%d\n", irq); + "re-trigger IRQ%d\n", d->irq); return i == 8 ? -1 : 0; } -static int sa1111_type_highirq(unsigned int irq, unsigned int flags) +static int sa1111_type_highirq(struct irq_data *d, unsigned int flags) { - struct sa1111 *sachip = get_irq_chip_data(irq); + struct sa1111 *sachip = irq_data_get_irq_chip_data(d); void __iomem *mapbase = sachip->base + SA1111_INTC; - unsigned int mask = SA1111_IRQMASK_HI(irq); + unsigned int mask = SA1111_IRQMASK_HI(d->irq); unsigned long ip1; if (flags == IRQ_TYPE_PROBE) @@ -415,11 +415,11 @@ static int sa1111_type_highirq(unsigned int irq, unsigned int flags) return 0; } -static int sa1111_wake_highirq(unsigned int irq, unsigned int on) +static int sa1111_wake_highirq(struct irq_data *d, unsigned int on) { - struct sa1111 *sachip = get_irq_chip_data(irq); + struct sa1111 *sachip = irq_data_get_irq_chip_data(d); void __iomem *mapbase = sachip->base + SA1111_INTC; - unsigned int mask = SA1111_IRQMASK_HI(irq); + unsigned int mask = SA1111_IRQMASK_HI(d->irq); unsigned long we1; we1 = sa1111_readl(mapbase + SA1111_WAKEEN1); @@ -434,12 +434,12 @@ static int sa1111_wake_highirq(unsigned int irq, unsigned int on) static struct irq_chip sa1111_high_chip = { .name = "SA1111-h", - .ack = sa1111_ack_irq, - .mask = sa1111_mask_highirq, - .unmask = sa1111_unmask_highirq, - .retrigger = sa1111_retrigger_highirq, - .set_type = sa1111_type_highirq, - .set_wake = sa1111_wake_highirq, + .irq_ack = sa1111_ack_irq, + .irq_mask = sa1111_mask_highirq, + .irq_unmask = sa1111_unmask_highirq, + .irq_retrigger = sa1111_retrigger_highirq, + .irq_set_type = sa1111_type_highirq, + .irq_set_wake = sa1111_wake_highirq, }; static void sa1111_setup_irq(struct sa1111 *sachip) diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index cb660bc54d7..ae5fe7292e0 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -204,26 +204,26 @@ static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 res static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { } #endif /* CONFIG_PM */ -static void vic_ack_irq(unsigned int irq) +static void vic_ack_irq(struct irq_data *d) { - void __iomem *base = get_irq_chip_data(irq); - irq &= 31; + void __iomem *base = irq_data_get_irq_chip_data(d); + unsigned int irq = d->irq & 31; writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); /* moreover, clear the soft-triggered, in case it was the reason */ writel(1 << irq, base + VIC_INT_SOFT_CLEAR); } -static void vic_mask_irq(unsigned int irq) +static void vic_mask_irq(struct irq_data *d) { - void __iomem *base = get_irq_chip_data(irq); - irq &= 31; + void __iomem *base = irq_data_get_irq_chip_data(d); + unsigned int irq = d->irq & 31; writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); } -static void vic_unmask_irq(unsigned int irq) +static void vic_unmask_irq(struct irq_data *d) { - void __iomem *base = get_irq_chip_data(irq); - irq &= 31; + void __iomem *base = irq_data_get_irq_chip_data(d); + unsigned int irq = d->irq & 31; writel(1 << irq, base + VIC_INT_ENABLE); } @@ -242,10 +242,10 @@ static struct vic_device *vic_from_irq(unsigned int irq) return NULL; } -static int vic_set_wake(unsigned int irq, unsigned int on) +static int vic_set_wake(struct irq_data *d, unsigned int on) { - struct vic_device *v = vic_from_irq(irq); - unsigned int off = irq & 31; + struct vic_device *v = vic_from_irq(d->irq); + unsigned int off = d->irq & 31; u32 bit = 1 << off; if (!v) @@ -267,10 +267,10 @@ static int vic_set_wake(unsigned int irq, unsigned int on) static struct irq_chip vic_chip = { .name = "VIC", - .ack = vic_ack_irq, - .mask = vic_mask_irq, - .unmask = vic_unmask_irq, - .set_wake = vic_set_wake, + .irq_ack = vic_ack_irq, + .irq_mask = vic_mask_irq, + .irq_unmask = vic_unmask_irq, + .irq_set_wake = vic_set_wake, }; static void __init vic_disable(void __iomem *base) diff --git a/arch/arm/configs/ag5evm_defconfig b/arch/arm/configs/ag5evm_defconfig index 2b9cf56db36..212ead354a6 100644 --- a/arch/arm/configs/ag5evm_defconfig +++ b/arch/arm/configs/ag5evm_defconfig @@ -10,7 +10,7 @@ CONFIG_NAMESPACES=y # CONFIG_PID_NS is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig index 5536c488dd0..f0dea52e49c 100644 --- a/arch/arm/configs/am200epdkit_defconfig +++ b/arch/arm/configs/am200epdkit_defconfig @@ -3,7 +3,7 @@ CONFIG_LOCALVERSION="gum" # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_EPOLL is not set # CONFIG_SHMEM is not set diff --git a/arch/arm/configs/at572d940hfek_defconfig b/arch/arm/configs/at572d940hfek_defconfig index 695e32d4fb5..1b1158ae8f8 100644 --- a/arch/arm/configs/at572d940hfek_defconfig +++ b/arch/arm/configs/at572d940hfek_defconfig @@ -17,7 +17,7 @@ CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_OPROFILE=m diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig index 3a1ad15a779..5b54abbeb0b 100644 --- a/arch/arm/configs/badge4_defconfig +++ b/arch/arm/configs/badge4_defconfig @@ -1,6 +1,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODVERSIONS=y CONFIG_ARCH_SA1100=y diff --git a/arch/arm/configs/bcmring_defconfig b/arch/arm/configs/bcmring_defconfig index 75984cd1e23..795374d48f8 100644 --- a/arch/arm/configs/bcmring_defconfig +++ b/arch/arm/configs/bcmring_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_EXTRA_PASS=y # CONFIG_HOTPLUG is not set # CONFIG_ELF_CORE is not set diff --git a/arch/arm/configs/cm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig index dcfbcf3b6c3..a93ff8da5ba 100644 --- a/arch/arm/configs/cm_x2xx_defconfig +++ b/arch/arm/configs/cm_x2xx_defconfig @@ -6,7 +6,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_SLUB_DEBUG is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/arm/configs/colibri_pxa270_defconfig b/arch/arm/configs/colibri_pxa270_defconfig index f52c64e36d8..2ef2c5e8aae 100644 --- a/arch/arm/configs/colibri_pxa270_defconfig +++ b/arch/arm/configs/colibri_pxa270_defconfig @@ -8,7 +8,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig index 310f9a6270b..6c56ad086c7 100644 --- a/arch/arm/configs/collie_defconfig +++ b/arch/arm/configs/collie_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_BASE_FULL is not set # CONFIG_EPOLL is not set CONFIG_SLOB=y diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig index 4a1fa81ed37..e53c4756384 100644 --- a/arch/arm/configs/corgi_defconfig +++ b/arch/arm/configs/corgi_defconfig @@ -4,7 +4,7 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_PROFILING=y CONFIG_OPROFILE=m CONFIG_MODULES=y diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig index cdc40c4b8c4..88ccde058ba 100644 --- a/arch/arm/configs/da8xx_omapl_defconfig +++ b/arch/arm/configs/da8xx_omapl_defconfig @@ -6,7 +6,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 2519cc5a5f8..889922ad229 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -6,7 +6,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index 9359e1bf32c..54bf5eec801 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -1,7 +1,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/arm/configs/ebsa110_defconfig b/arch/arm/configs/ebsa110_defconfig index c3194186920..14559dbb4c2 100644 --- a/arch/arm/configs/ebsa110_defconfig +++ b/arch/arm/configs/ebsa110_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_ARCH_EBSA110=y CONFIG_PCCARD=m diff --git a/arch/arm/configs/edb7211_defconfig b/arch/arm/configs/edb7211_defconfig index 7b62be1561e..d52ded350a1 100644 --- a/arch/arm/configs/edb7211_defconfig +++ b/arch/arm/configs/edb7211_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_HOTPLUG is not set CONFIG_ARCH_CLPS711X=y CONFIG_ARCH_EDB7211=y diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig index d7db34f7970..60a21e01eb7 100644 --- a/arch/arm/configs/em_x270_defconfig +++ b/arch/arm/configs/em_x270_defconfig @@ -6,7 +6,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_SLUB_DEBUG is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig index 6d6689cdf39..8e97b2f7cee 100644 --- a/arch/arm/configs/ep93xx_defconfig +++ b/arch/arm/configs/ep93xx_defconfig @@ -4,7 +4,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig index 1691dea582f..d68ac67c201 100644 --- a/arch/arm/configs/eseries_pxa_defconfig +++ b/arch/arm/configs/eseries_pxa_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig index c4eeb6d1cbf..227a477346e 100644 --- a/arch/arm/configs/ezx_defconfig +++ b/arch/arm/configs/ezx_defconfig @@ -7,7 +7,7 @@ CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/arm/configs/footbridge_defconfig b/arch/arm/configs/footbridge_defconfig index 4f925ead261..038518ab39a 100644 --- a/arch/arm/configs/footbridge_defconfig +++ b/arch/arm/configs/footbridge_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_HOTPLUG is not set CONFIG_MODULES=y CONFIG_ARCH_FOOTBRIDGE=y diff --git a/arch/arm/configs/fortunet_defconfig b/arch/arm/configs/fortunet_defconfig index e11c7eab8ed..840fced7529 100644 --- a/arch/arm/configs/fortunet_defconfig +++ b/arch/arm/configs/fortunet_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_HOTPLUG is not set CONFIG_ARCH_CLPS711X=y CONFIG_ARCH_FORTUNET=y diff --git a/arch/arm/configs/h5000_defconfig b/arch/arm/configs/h5000_defconfig index ac336f10000..37903e3f0ef 100644 --- a/arch/arm/configs/h5000_defconfig +++ b/arch/arm/configs/h5000_defconfig @@ -4,7 +4,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_UID16 is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig index ade55c8c408..176ec22af03 100644 --- a/arch/arm/configs/imote2_defconfig +++ b/arch/arm/configs/imote2_defconfig @@ -6,7 +6,7 @@ CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/arm/configs/ixp2000_defconfig b/arch/arm/configs/ixp2000_defconfig index 90832468454..8405aded97a 100644 --- a/arch/arm/configs/ixp2000_defconfig +++ b/arch/arm/configs/ixp2000_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_HOTPLUG is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/arm/configs/ixp23xx_defconfig b/arch/arm/configs/ixp23xx_defconfig index 7fc056a8569..688717612e9 100644 --- a/arch/arm/configs/ixp23xx_defconfig +++ b/arch/arm/configs/ixp23xx_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig index 5c502393400..063e2ab2c8f 100644 --- a/arch/arm/configs/ixp4xx_defconfig +++ b/arch/arm/configs/ixp4xx_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODVERSIONS=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/arm/configs/loki_defconfig b/arch/arm/configs/loki_defconfig index e1eaff7f553..1ba752b2dc6 100644 --- a/arch/arm/configs/loki_defconfig +++ b/arch/arm/configs/loki_defconfig @@ -1,7 +1,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/arm/configs/lpd7a400_defconfig b/arch/arm/configs/lpd7a400_defconfig index 20caaaba4a0..5a48f171204 100644 --- a/arch/arm/configs/lpd7a400_defconfig +++ b/arch/arm/configs/lpd7a400_defconfig @@ -3,7 +3,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_HOTPLUG is not set # CONFIG_EPOLL is not set # CONFIG_IOSCHED_DEADLINE is not set diff --git a/arch/arm/configs/lpd7a404_defconfig b/arch/arm/configs/lpd7a404_defconfig index 1efcce97b4a..22d0631de00 100644 --- a/arch/arm/configs/lpd7a404_defconfig +++ b/arch/arm/configs/lpd7a404_defconfig @@ -3,7 +3,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y CONFIG_LOG_BUF_SHIFT=16 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_HOTPLUG is not set # CONFIG_EPOLL is not set CONFIG_SLAB=y diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig index af805e8fd03..a88e64d4e9a 100644 --- a/arch/arm/configs/magician_defconfig +++ b/arch/arm/configs/magician_defconfig @@ -4,7 +4,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_UID16 is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig index b0d082422d4..7305ebddb51 100644 --- a/arch/arm/configs/mv78xx0_defconfig +++ b/arch/arm/configs/mv78xx0_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y # CONFIG_SLUB_DEBUG is not set CONFIG_PROFILING=y diff --git a/arch/arm/configs/mx1_defconfig b/arch/arm/configs/mx1_defconfig index 2f38d971543..b39b5ced8a1 100644 --- a/arch/arm/configs/mx1_defconfig +++ b/arch/arm/configs/mx1_defconfig @@ -4,7 +4,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/arm/configs/mx21_defconfig b/arch/arm/configs/mx21_defconfig index 6454e18e2ab..411f88dd440 100644 --- a/arch/arm/configs/mx21_defconfig +++ b/arch/arm/configs/mx21_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/arm/configs/mx27_defconfig b/arch/arm/configs/mx27_defconfig index 813cfb366c1..9ad4c656c9b 100644 --- a/arch/arm/configs/mx27_defconfig +++ b/arch/arm/configs/mx27_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_EXTRA_PASS=y # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig index e648ea3429b..7c4b30b3495 100644 --- a/arch/arm/configs/mx3_defconfig +++ b/arch/arm/configs/mx3_defconfig @@ -4,7 +4,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig index 5c7a87260fa..9cba68cfa51 100644 --- a/arch/arm/configs/mx51_defconfig +++ b/arch/arm/configs/mx51_defconfig @@ -3,7 +3,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=18 CONFIG_RELAY=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SLUB_DEBUG is not set # CONFIG_COMPAT_BRK is not set CONFIG_MODULES=y diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig index 0e2dc26ebe6..37207d1bf44 100644 --- a/arch/arm/configs/nhk8815_defconfig +++ b/arch/arm/configs/nhk8815_defconfig @@ -7,7 +7,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig index a350cc6bfe6..7b63462b349 100644 --- a/arch/arm/configs/omap1_defconfig +++ b/arch/arm/configs/omap1_defconfig @@ -6,7 +6,7 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_ELF_CORE is not set # CONFIG_BASE_FULL is not set diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index ccedde1371c..ae890caa17a 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -6,7 +6,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_SLAB=y diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig index 439323b3b0e..a288d703395 100644 --- a/arch/arm/configs/orion5x_defconfig +++ b/arch/arm/configs/orion5x_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SLUB_DEBUG is not set CONFIG_PROFILING=y CONFIG_OPROFILE=y diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig index 583a0610bd0..2f136c30a98 100644 --- a/arch/arm/configs/pcm027_defconfig +++ b/arch/arm/configs/pcm027_defconfig @@ -7,7 +7,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/arm/configs/pcontrol_g20_defconfig b/arch/arm/configs/pcontrol_g20_defconfig index b42ee62c4d7..c75c9fcede5 100644 --- a/arch/arm/configs/pcontrol_g20_defconfig +++ b/arch/arm/configs/pcontrol_g20_defconfig @@ -10,7 +10,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_NAMESPACES=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_KALLSYMS is not set # CONFIG_VM_EVENT_COUNTERS is not set diff --git a/arch/arm/configs/pleb_defconfig b/arch/arm/configs/pleb_defconfig index d1efbdc1e6d..cb08cc561da 100644 --- a/arch/arm/configs/pleb_defconfig +++ b/arch/arm/configs/pleb_defconfig @@ -3,7 +3,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_HOTPLUG is not set # CONFIG_SHMEM is not set CONFIG_MODULES=y diff --git a/arch/arm/configs/pnx4008_defconfig b/arch/arm/configs/pnx4008_defconfig index bd481f04276..35a31ccacc3 100644 --- a/arch/arm/configs/pnx4008_defconfig +++ b/arch/arm/configs/pnx4008_defconfig @@ -5,7 +5,7 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_AUDIT=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/arm/configs/simpad_defconfig b/arch/arm/configs/simpad_defconfig index af3b12e3b46..d3358155bf8 100644 --- a/arch/arm/configs/simpad_defconfig +++ b/arch/arm/configs/simpad_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_LOCALVERSION="oe1" CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig index aebd4bb0ad0..70158273c6d 100644 --- a/arch/arm/configs/spitz_defconfig +++ b/arch/arm/configs/spitz_defconfig @@ -4,7 +4,7 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_PROFILING=y CONFIG_OPROFILE=m CONFIG_MODULES=y diff --git a/arch/arm/configs/stmp378x_defconfig b/arch/arm/configs/stmp378x_defconfig index 94a2d904bf9..1079c2b6eb3 100644 --- a/arch/arm/configs/stmp378x_defconfig +++ b/arch/arm/configs/stmp378x_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/arm/configs/stmp37xx_defconfig b/arch/arm/configs/stmp37xx_defconfig index d8ee58cfa87..564a5cc4408 100644 --- a/arch/arm/configs/stmp37xx_defconfig +++ b/arch/arm/configs/stmp37xx_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig index e89ca19489c..95c0f0d63db 100644 --- a/arch/arm/configs/tct_hammer_defconfig +++ b/arch/arm/configs/tct_hammer_defconfig @@ -5,7 +5,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_BUG is not set # CONFIG_ELF_CORE is not set diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig index 37f48342827..3162173fa75 100644 --- a/arch/arm/configs/trizeps4_defconfig +++ b/arch/arm/configs/trizeps4_defconfig @@ -7,7 +7,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig index c1c252cdca6..4a5a12681be 100644 --- a/arch/arm/configs/u300_defconfig +++ b/arch/arm/configs/u300_defconfig @@ -3,7 +3,7 @@ CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_AIO is not set # CONFIG_VM_EVENT_COUNTERS is not set CONFIG_MODULES=y diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig index 9d7bf5e0d0f..8b0c717378f 100644 --- a/arch/arm/configs/viper_defconfig +++ b/arch/arm/configs/viper_defconfig @@ -3,7 +3,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=13 CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_ELF_CORE is not set # CONFIG_SHMEM is not set CONFIG_SLAB=y diff --git a/arch/arm/configs/xcep_defconfig b/arch/arm/configs/xcep_defconfig index 70d47dbae6d..5b550414364 100644 --- a/arch/arm/configs/xcep_defconfig +++ b/arch/arm/configs/xcep_defconfig @@ -8,7 +8,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_UID16 is not set # CONFIG_SHMEM is not set # CONFIG_VM_EVENT_COUNTERS is not set diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 338ff19ae44..7b1bb2bbaf8 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -285,7 +285,7 @@ static inline int fls(int x) if (__builtin_constant_p(x)) return constant_fls(x); - asm("clz\t%0, %1" : "=r" (ret) : "r" (x) : "cc"); + asm("clz\t%0, %1" : "=r" (ret) : "r" (x)); ret = 32 - ret; return ret; } diff --git a/arch/arm/include/asm/sched_clock.h b/arch/arm/include/asm/sched_clock.h index a84628be1a7..c8e6ddf3e86 100644 --- a/arch/arm/include/asm/sched_clock.h +++ b/arch/arm/include/asm/sched_clock.h @@ -115,4 +115,6 @@ static inline void init_fixed_sched_clock(struct clock_data *cd, } } +extern void sched_clock_postinit(void); + #endif diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c index eed2f795e1b..2ad62df3773 100644 --- a/arch/arm/kernel/ecard.c +++ b/arch/arm/kernel/ecard.c @@ -443,40 +443,40 @@ static expansioncard_ops_t ecard_default_ops = { * * They are not meant to be called directly, but via enable/disable_irq. */ -static void ecard_irq_unmask(unsigned int irqnr) +static void ecard_irq_unmask(struct irq_data *d) { - ecard_t *ec = slot_to_ecard(irqnr - 32); + ecard_t *ec = slot_to_ecard(d->irq - 32); if (ec) { if (!ec->ops) ec->ops = &ecard_default_ops; if (ec->claimed && ec->ops->irqenable) - ec->ops->irqenable(ec, irqnr); + ec->ops->irqenable(ec, d->irq); else printk(KERN_ERR "ecard: rejecting request to " - "enable IRQs for %d\n", irqnr); + "enable IRQs for %d\n", d->irq); } } -static void ecard_irq_mask(unsigned int irqnr) +static void ecard_irq_mask(struct irq_data *d) { - ecard_t *ec = slot_to_ecard(irqnr - 32); + ecard_t *ec = slot_to_ecard(d->irq - 32); if (ec) { if (!ec->ops) ec->ops = &ecard_default_ops; if (ec->ops && ec->ops->irqdisable) - ec->ops->irqdisable(ec, irqnr); + ec->ops->irqdisable(ec, d->irq); } } static struct irq_chip ecard_chip = { - .name = "ECARD", - .ack = ecard_irq_mask, - .mask = ecard_irq_mask, - .unmask = ecard_irq_unmask, + .name = "ECARD", + .irq_ack = ecard_irq_mask, + .irq_mask = ecard_irq_mask, + .irq_unmask = ecard_irq_unmask, }; void ecard_enablefiq(unsigned int fiqnr) @@ -551,7 +551,7 @@ static void ecard_check_lockup(struct irq_desc *desc) printk(KERN_ERR "\nInterrupt lockup detected - " "disabling all expansion card interrupts\n"); - desc->chip->mask(IRQ_EXPANSIONCARD); + desc->irq_data.chip->irq_mask(&desc->irq_data); ecard_dump_irq_state(); } } else @@ -574,7 +574,7 @@ ecard_irq_handler(unsigned int irq, struct irq_desc *desc) ecard_t *ec; int called = 0; - desc->chip->mask(irq); + desc->irq_data.chip->irq_mask(&desc->irq_data); for (ec = cards; ec; ec = ec->next) { int pending; @@ -591,7 +591,7 @@ ecard_irq_handler(unsigned int irq, struct irq_desc *desc) called ++; } } - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); if (called == 0) ecard_check_lockup(desc); diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index bbecaac1e01..8f57515bbdb 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S @@ -60,6 +60,8 @@ str_a1: .asciz "\nError: unrecognized/unsupported machine ID (r1 = 0x" str_a2: .asciz ").\n\nAvailable machine support:\n\nID (hex)\tNAME\n" str_a3: .asciz "\nPlease check your kernel config and/or bootloader.\n" .align +#else + b __error #endif /* diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 8135438b881..28536e352de 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -88,7 +88,7 @@ int show_interrupts(struct seq_file *p, void *v) seq_printf(p, "%*d: ", prec, i); for_each_present_cpu(cpu) seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); - seq_printf(p, " %10s", desc->chip->name ? : "-"); + seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-"); seq_printf(p, " %s", action->name); for (action = action->next; action; action = action->next) seq_printf(p, ", %s", action->name); @@ -181,10 +181,11 @@ int __init arch_probe_nr_irqs(void) static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) { - pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->node, cpu); + pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->irq_data.node, cpu); raw_spin_lock_irq(&desc->lock); - desc->chip->set_affinity(irq, cpumask_of(cpu)); + desc->irq_data.chip->irq_set_affinity(&desc->irq_data, + cpumask_of(cpu), false); raw_spin_unlock_irq(&desc->lock); } @@ -199,16 +200,18 @@ void migrate_irqs(void) struct irq_desc *desc; for_each_irq_desc(i, desc) { - if (desc->node == cpu) { - unsigned int newcpu = cpumask_any_and(desc->affinity, + struct irq_data *d = &desc->irq_data; + + if (d->node == cpu) { + unsigned int newcpu = cpumask_any_and(d->affinity, cpu_online_mask); if (newcpu >= nr_cpu_ids) { if (printk_ratelimit()) printk(KERN_INFO "IRQ%u no longer affine to CPU%u\n", i, cpu); - cpumask_setall(desc->affinity); - newcpu = cpumask_any_and(desc->affinity, + cpumask_setall(d->affinity); + newcpu = cpumask_any_and(d->affinity, cpu_online_mask); } diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index e76fcaadce0..94bbedbed63 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -483,6 +483,7 @@ unsigned long arch_randomize_brk(struct mm_struct *mm) return randomize_range(mm->brk, range_end, 0) ? : mm->brk; } +#ifdef CONFIG_MMU /* * The vectors page is always readable from user space for the * atomic helpers and the signal restart code. Let's declare a mapping @@ -503,3 +504,4 @@ const char *arch_vma_name(struct vm_area_struct *vma) { return (vma->vm_start == 0xffff0000) ? "[vectors]" : NULL; } +#endif diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c index 2cdcc9287c7..9a46370fe9d 100644 --- a/arch/arm/kernel/sched_clock.c +++ b/arch/arm/kernel/sched_clock.c @@ -34,7 +34,7 @@ void __init init_sched_clock(struct clock_data *cd, void (*update)(void), sched_clock_update_fn = update; /* calculate the mult/shift to convert counter ticks to ns. */ - clocks_calc_mult_shift(&cd->mult, &cd->shift, rate, NSEC_PER_SEC, 60); + clocks_calc_mult_shift(&cd->mult, &cd->shift, rate, NSEC_PER_SEC, 0); r = rate; if (r >= 4000000) { @@ -60,10 +60,15 @@ void __init init_sched_clock(struct clock_data *cd, void (*update)(void), * sets the initial epoch. */ sched_clock_timer.data = msecs_to_jiffies(w - (w / 10)); - sched_clock_poll(sched_clock_timer.data); + update(); /* * Ensure that sched_clock() starts off at 0ns */ cd->epoch_ns = 0; } + +void __init sched_clock_postinit(void) +{ + sched_clock_poll(sched_clock_timer.data); +} diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 3455ad33de4..420b8d6485d 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -518,25 +518,21 @@ setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz) #endif } -static void __init -request_standard_resources(struct meminfo *mi, struct machine_desc *mdesc) +static void __init request_standard_resources(struct machine_desc *mdesc) { + struct memblock_region *region; struct resource *res; - int i; kernel_code.start = virt_to_phys(_text); kernel_code.end = virt_to_phys(_etext - 1); kernel_data.start = virt_to_phys(_sdata); kernel_data.end = virt_to_phys(_end - 1); - for (i = 0; i < mi->nr_banks; i++) { - if (mi->bank[i].size == 0) - continue; - + for_each_memblock(memory, region) { res = alloc_bootmem_low(sizeof(*res)); res->name = "System RAM"; - res->start = mi->bank[i].start; - res->end = mi->bank[i].start + mi->bank[i].size - 1; + res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); + res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; request_resource(&iomem_resource, res); @@ -650,15 +646,17 @@ static int __init parse_tag_revision(const struct tag *tag) __tagtable(ATAG_REVISION, parse_tag_revision); -#ifndef CONFIG_CMDLINE_FORCE static int __init parse_tag_cmdline(const struct tag *tag) { +#ifndef CONFIG_CMDLINE_FORCE strlcpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE); +#else + pr_warning("Ignoring tag cmdline (using the default kernel command line)\n"); +#endif /* CONFIG_CMDLINE_FORCE */ return 0; } __tagtable(ATAG_CMDLINE, parse_tag_cmdline); -#endif /* CONFIG_CMDLINE_FORCE */ /* * Scan the tag table for this tag, and call its parse function. @@ -857,7 +855,7 @@ void __init setup_arch(char **cmdline_p) arm_memblock_init(&meminfo, mdesc); paging_init(mdesc); - request_standard_resources(&meminfo, mdesc); + request_standard_resources(mdesc); #ifdef CONFIG_SMP if (is_smp()) diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index dd790745b3e..fd9156698ab 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -114,7 +114,7 @@ static void __cpuinit twd_calibrate_rate(void) twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5); printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000, - (twd_timer_rate / 100000) % 100); + (twd_timer_rate / 1000000) % 100); } load = twd_timer_rate / HZ; diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c index c2e112e1a05..381d23a497c 100644 --- a/arch/arm/kernel/stacktrace.c +++ b/arch/arm/kernel/stacktrace.c @@ -94,10 +94,13 @@ void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) if (tsk != current) { #ifdef CONFIG_SMP /* - * What guarantees do we have here that 'tsk' - * is not running on another CPU? + * What guarantees do we have here that 'tsk' is not + * running on another CPU? For now, ignore it as we + * can't guarantee we won't explode. */ - BUG(); + if (trace->nr_entries < trace->max_entries) + trace->entries[trace->nr_entries++] = ULONG_MAX; + return; #else data.no_sched_functions = 1; frame.fp = thread_saved_fp(tsk); diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index f1e2eb19a67..3d76bf23373 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -29,6 +29,7 @@ #include <asm/leds.h> #include <asm/thread_info.h> +#include <asm/sched_clock.h> #include <asm/stacktrace.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> @@ -163,5 +164,8 @@ void __init time_init(void) { system_timer = machine_desc->timer; system_timer->init(); +#ifdef CONFIG_HAVE_SCHED_CLOCK + sched_clock_postinit(); +#endif } diff --git a/arch/arm/lib/delay.S b/arch/arm/lib/delay.S index 8d6a8762ab8..3c9a05c8d20 100644 --- a/arch/arm/lib/delay.S +++ b/arch/arm/lib/delay.S @@ -25,11 +25,15 @@ ENTRY(__udelay) ldr r2, .LC1 mul r0, r2, r0 ENTRY(__const_udelay) @ 0 <= r0 <= 0x7fffff06 + mov r1, #-1 ldr r2, .LC0 ldr r2, [r2] @ max = 0x01ffffff + add r0, r0, r1, lsr #32-14 mov r0, r0, lsr #14 @ max = 0x0001ffff + add r2, r2, r1, lsr #32-10 mov r2, r2, lsr #10 @ max = 0x00007fff mul r0, r2, r0 @ max = 2^32-1 + add r0, r0, r1, lsr #32-6 movs r0, r0, lsr #6 moveq pc, lr diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c index 3ef68330452..f8465bd17e6 100644 --- a/arch/arm/mach-aaec2000/core.c +++ b/arch/arm/mach-aaec2000/core.c @@ -68,25 +68,25 @@ void __init aaec2000_map_io(void) /* * Interrupt handling routines */ -static void aaec2000_int_ack(unsigned int irq) +static void aaec2000_int_ack(struct irq_data *d) { - IRQ_INTSR = 1 << irq; + IRQ_INTSR = 1 << d->irq; } -static void aaec2000_int_mask(unsigned int irq) +static void aaec2000_int_mask(struct irq_data *d) { - IRQ_INTENC |= (1 << irq); + IRQ_INTENC |= (1 << d->irq); } -static void aaec2000_int_unmask(unsigned int irq) +static void aaec2000_int_unmask(struct irq_data *d) { - IRQ_INTENS |= (1 << irq); + IRQ_INTENS |= (1 << d->irq); } static struct irq_chip aaec2000_irq_chip = { - .ack = aaec2000_int_ack, - .mask = aaec2000_int_mask, - .unmask = aaec2000_int_unmask, + .irq_ack = aaec2000_int_ack, + .irq_mask = aaec2000_int_mask, + .irq_unmask = aaec2000_int_unmask, }; void __init aaec2000_init_irq(void) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c015b684b4f..19390231a0e 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -362,6 +362,12 @@ config MACH_CPU9G20 Select this if you are using a Eukrea Electromatique's CPU9G20 Board <http://www.eukrea.com/> +config MACH_ACMENETUSFOXG20 + bool "Acme Systems srl FOX Board G20" + help + Select this if you are using Acme Systems + FOX Board G20 <http://www.acmesystems.it> + config MACH_PORTUXG20 bool "taskit PortuxG20" help @@ -381,6 +387,13 @@ config MACH_PCONTROL_G20 Select this if you are using taskit's Stamp9G20 CPU module on this carrier board, beeing the decentralized unit of a building automation system; featuring nvram, eth-switch, iso-rs485, display, io + +config MACH_GSIA18S + bool "GS_IA18_S board" + help + This enables support for the GS_IA18_S board + produced by GeoSIG Ltd company. This is an internet accelerograph. + <http://www.geosig.com> endif if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index d13add71f72..a83835e0c18 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -63,9 +63,11 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o # AT91SAM9G20 board-specific support obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o +obj-$(CONFIG_MACH_ACMENETUSFOXG20) += board-foxg20.o obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o +obj-$(CONFIG_MACH_GSIA18S) += board-gsia18s.o board-stamp9g20.o # AT91SAM9260/AT91SAM9G20 board-specific support obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c new file mode 100644 index 00000000000..dfc7dfe738e --- /dev/null +++ b/arch/arm/mach-at91/board-foxg20.c @@ -0,0 +1,274 @@ +/* + * Copyright (C) 2005 SAN People + * Copyright (C) 2008 Atmel + * Copyright (C) 2010 Lee McLoughlin - lee@lmmrtech.com + * Copyright (C) 2010 Sergio Tanzilli - tanzilli@acmesystems.it + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/types.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/spi/spi.h> +#include <linux/spi/at73c213.h> +#include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/clk.h> +#include <linux/w1-gpio.h> + +#include <mach/hardware.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/irq.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <mach/board.h> +#include <mach/at91sam9_smc.h> + +#include "sam9_smc.h" +#include "generic.h" + +/* + * The FOX Board G20 hardware comes as the "Netus G20" board with + * just the cpu, ram, dataflash and two header connectors. + * This is plugged into the FOX Board which provides the ethernet, + * usb, rtc, leds, switch, ... + * + * For more info visit: http://www.acmesystems.it/foxg20 + */ + + +static void __init foxg20_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91sam9260_initialize(18432000); + + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, + ATMEL_UART_CTS + | ATMEL_UART_RTS + | ATMEL_UART_DTR + | ATMEL_UART_DSR + | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, + ATMEL_UART_CTS + | ATMEL_UART_RTS); + + /* USART2 on ttyS3. (Rx & Tx only) */ + at91_register_uart(AT91SAM9260_ID_US2, 3, 0); + + /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US3, 4, + ATMEL_UART_CTS + | ATMEL_UART_RTS); + + /* USART4 on ttyS5. (Rx & Tx only) */ + at91_register_uart(AT91SAM9260_ID_US4, 5, 0); + + /* USART5 on ttyS6. (Rx & Tx only) */ + at91_register_uart(AT91SAM9260_ID_US5, 6, 0); + + /* set serial console to ttyS0 (ie, DBGU) */ + at91_set_serial_console(0); + + /* Set the internal pull-up resistor on DRXD */ + at91_set_A_periph(AT91_PIN_PB14, 1); + +} + +static void __init foxg20_init_irq(void) +{ + at91sam9260_init_interrupts(NULL); +} + + +/* + * USB Host port + */ +static struct at91_usbh_data __initdata foxg20_usbh_data = { + .ports = 2, +}; + +/* + * USB Device port + */ +static struct at91_udc_data __initdata foxg20_udc_data = { + .vbus_pin = AT91_PIN_PC6, + .pullup_pin = 0, /* pull-up driven by UDC */ +}; + + +/* + * SPI devices. + */ +static struct spi_board_info foxg20_spi_devices[] = { +#if !defined(CONFIG_MMC_AT91) + { + .modalias = "mtd_dataflash", + .chip_select = 1, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +#endif +}; + + +/* + * MACB Ethernet device + */ +static struct at91_eth_data __initdata foxg20_macb_data = { + .phy_irq_pin = AT91_PIN_PA7, + .is_rmii = 1, +}; + +/* + * MCI (SD/MMC) + * det_pin, wp_pin and vcc_pin are not connected + */ +static struct at91_mmc_data __initdata foxg20_mmc_data = { + .slot_b = 1, + .wire4 = 1, +}; + + +/* + * LEDs + */ +static struct gpio_led foxg20_leds[] = { + { /* user led, red */ + .name = "user_led", + .gpio = AT91_PIN_PC7, + .active_low = 0, + .default_trigger = "heartbeat", + }, +}; + + +/* + * GPIO Buttons + */ +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +static struct gpio_keys_button foxg20_buttons[] = { + { + .gpio = AT91_PIN_PC4, + .code = BTN_1, + .desc = "Button 1", + .active_low = 1, + .wakeup = 1, + }, +}; + +static struct gpio_keys_platform_data foxg20_button_data = { + .buttons = foxg20_buttons, + .nbuttons = ARRAY_SIZE(foxg20_buttons), +}; + +static struct platform_device foxg20_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &foxg20_button_data, + } +}; + +static void __init foxg20_add_device_buttons(void) +{ + at91_set_gpio_input(AT91_PIN_PC4, 1); /* btn1 */ + at91_set_deglitch(AT91_PIN_PC4, 1); + + platform_device_register(&foxg20_button_device); +} +#else +static void __init foxg20_add_device_buttons(void) {} +#endif + + +#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) +static struct w1_gpio_platform_data w1_gpio_pdata = { + /* If you choose to use a pin other than PB16 it needs to be 3.3V */ + .pin = AT91_PIN_PB16, + .is_open_drain = 1, +}; + +static struct platform_device w1_device = { + .name = "w1-gpio", + .id = -1, + .dev.platform_data = &w1_gpio_pdata, +}; + +static void __init at91_add_device_w1(void) +{ + at91_set_GPIO_periph(w1_gpio_pdata.pin, 1); + at91_set_multi_drive(w1_gpio_pdata.pin, 1); + platform_device_register(&w1_device); +} + +#endif + + +static struct i2c_board_info __initdata foxg20_i2c_devices[] = { + { + I2C_BOARD_INFO("24c512", 0x50), + }, +}; + + +static void __init foxg20_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&foxg20_usbh_data); + /* USB Device */ + at91_add_device_udc(&foxg20_udc_data); + /* SPI */ + at91_add_device_spi(foxg20_spi_devices, ARRAY_SIZE(foxg20_spi_devices)); + /* Ethernet */ + at91_add_device_eth(&foxg20_macb_data); + /* MMC */ + at91_add_device_mmc(0, &foxg20_mmc_data); + /* I2C */ + at91_add_device_i2c(foxg20_i2c_devices, ARRAY_SIZE(foxg20_i2c_devices)); + /* LEDs */ + at91_gpio_leds(foxg20_leds, ARRAY_SIZE(foxg20_leds)); + /* Push Buttons */ + foxg20_add_device_buttons(); +#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) + at91_add_device_w1(); +#endif +} + +MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20") + /* Maintainer: Sergio Tanzilli */ + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = foxg20_map_io, + .init_irq = foxg20_init_irq, + .init_machine = foxg20_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c new file mode 100644 index 00000000000..bc28136ee24 --- /dev/null +++ b/arch/arm/mach-at91/board-gsia18s.c @@ -0,0 +1,584 @@ +/* + * Copyright (C) 2010 Christian Glindkamp <christian.glindkamp@taskit.de> + * taskit GmbH + * 2010 Igor Plyatov <plyatov@gmail.com> + * GeoSIG Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/w1-gpio.h> +#include <linux/i2c.h> +#include <linux/i2c/pcf857x.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/board.h> +#include <mach/at91sam9_smc.h> +#include <mach/gsia18s.h> +#include <mach/stamp9g20.h> + +#include "sam9_smc.h" +#include "generic.h" + +static void __init gsia18s_map_io(void) +{ + stamp9g20_map_io(); + + /* + * USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI). + * Used for Internal Analog Modem. + */ + at91_register_uart(AT91SAM9260_ID_US0, 1, + ATMEL_UART_CTS | ATMEL_UART_RTS | + ATMEL_UART_DTR | ATMEL_UART_DSR | + ATMEL_UART_DCD | ATMEL_UART_RI); + /* + * USART1 on ttyS2 (Rx, Tx, CTS, RTS). + * Used for GPS or WiFi or Data stream. + */ + at91_register_uart(AT91SAM9260_ID_US1, 2, + ATMEL_UART_CTS | ATMEL_UART_RTS); + /* + * USART2 on ttyS3 (Rx, Tx, CTS, RTS). + * Used for External Modem. + */ + at91_register_uart(AT91SAM9260_ID_US2, 3, + ATMEL_UART_CTS | ATMEL_UART_RTS); + /* + * USART3 on ttyS4 (Rx, Tx, RTS). + * Used for RS-485. + */ + at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS); + + /* + * USART4 on ttyS5 (Rx, Tx). + * Used for TRX433 Radio Module. + */ + at91_register_uart(AT91SAM9260_ID_US4, 5, 0); +} + +static void __init init_irq(void) +{ + at91sam9260_init_interrupts(NULL); +} + +/* + * Two USB Host ports + */ +static struct at91_usbh_data __initdata usbh_data = { + .ports = 2, +}; + +/* + * USB Device port + */ +static struct at91_udc_data __initdata udc_data = { + .vbus_pin = AT91_PIN_PA22, + .pullup_pin = 0, /* pull-up driven by UDC */ +}; + +/* + * MACB Ethernet device + */ +static struct at91_eth_data __initdata macb_data = { + .phy_irq_pin = AT91_PIN_PA28, + .is_rmii = 1, +}; + +/* + * LEDs and GPOs + */ +static struct gpio_led gpio_leds[] = { + { + .name = "gpo:spi1reset", + .gpio = AT91_PIN_PC1, + .active_low = 0, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + { + .name = "gpo:trig_net_out", + .gpio = AT91_PIN_PB20, + .active_low = 0, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + { + .name = "gpo:trig_net_dir", + .gpio = AT91_PIN_PB19, + .active_low = 0, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + { + .name = "gpo:charge_dis", + .gpio = AT91_PIN_PC2, + .active_low = 0, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + { + .name = "led:event", + .gpio = AT91_PIN_PB17, + .active_low = 1, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + { + .name = "led:lan", + .gpio = AT91_PIN_PB18, + .active_low = 1, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + { + .name = "led:error", + .gpio = AT91_PIN_PB16, + .active_low = 1, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_ON, + } +}; + +static struct gpio_led_platform_data gpio_led_info = { + .leds = gpio_leds, + .num_leds = ARRAY_SIZE(gpio_leds), +}; + +static struct platform_device leds = { + .name = "leds-gpio", + .id = 0, + .dev = { + .platform_data = &gpio_led_info, + } +}; + +static void __init gsia18s_leds_init(void) +{ + platform_device_register(&leds); +} + +/* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */ +static struct gpio_led pcf_gpio_leds1[] = { + { /* bit 0 */ + .name = "gpo:hdc_power", + .gpio = PCF_GPIO_HDC_POWER, + .active_low = 0, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + { /* bit 1 */ + .name = "gpo:wifi_setup", + .gpio = PCF_GPIO_WIFI_SETUP, + .active_low = 1, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + { /* bit 2 */ + .name = "gpo:wifi_enable", + .gpio = PCF_GPIO_WIFI_ENABLE, + .active_low = 1, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + { /* bit 3 */ + .name = "gpo:wifi_reset", + .gpio = PCF_GPIO_WIFI_RESET, + .active_low = 1, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, + /* bit 4 used as GPI */ + { /* bit 5 */ + .name = "gpo:gps_setup", + .gpio = PCF_GPIO_GPS_SETUP, + .active_low = 1, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + { /* bit 6 */ + .name = "gpo:gps_standby", + .gpio = PCF_GPIO_GPS_STANDBY, + .active_low = 0, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, + { /* bit 7 */ + .name = "gpo:gps_power", + .gpio = PCF_GPIO_GPS_POWER, + .active_low = 0, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + } +}; + +static struct gpio_led_platform_data pcf_gpio_led_info1 = { + .leds = pcf_gpio_leds1, + .num_leds = ARRAY_SIZE(pcf_gpio_leds1), +}; + +static struct platform_device pcf_leds1 = { + .name = "leds-gpio", /* GS_IA18-CB_board */ + .id = 1, + .dev = { + .platform_data = &pcf_gpio_led_info1, + } +}; + +/* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */ +static struct gpio_led pcf_gpio_leds2[] = { + { /* bit 0 */ + .name = "gpo:alarm_1", + .gpio = PCF_GPIO_ALARM1, + .active_low = 1, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + { /* bit 1 */ + .name = "gpo:alarm_2", + .gpio = PCF_GPIO_ALARM2, + .active_low = 1, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + { /* bit 2 */ + .name = "gpo:alarm_3", + .gpio = PCF_GPIO_ALARM3, + .active_low = 1, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + { /* bit 3 */ + .name = "gpo:alarm_4", + .gpio = PCF_GPIO_ALARM4, + .active_low = 1, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + /* bits 4, 5, 6 not used */ + { /* bit 7 */ + .name = "gpo:alarm_v_relay_on", + .gpio = PCF_GPIO_ALARM_V_RELAY_ON, + .active_low = 0, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, +}; + +static struct gpio_led_platform_data pcf_gpio_led_info2 = { + .leds = pcf_gpio_leds2, + .num_leds = ARRAY_SIZE(pcf_gpio_leds2), +}; + +static struct platform_device pcf_leds2 = { + .name = "leds-gpio", + .id = 2, + .dev = { + .platform_data = &pcf_gpio_led_info2, + } +}; + +/* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */ +static struct gpio_led pcf_gpio_leds3[] = { + { /* bit 0 */ + .name = "gpo:modem_power", + .gpio = PCF_GPIO_MODEM_POWER, + .active_low = 1, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + /* bits 1 and 2 not used */ + { /* bit 3 */ + .name = "gpo:modem_reset", + .gpio = PCF_GPIO_MODEM_RESET, + .active_low = 1, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, + /* bits 4, 5 and 6 not used */ + { /* bit 7 */ + .name = "gpo:trx_reset", + .gpio = PCF_GPIO_TRX_RESET, + .active_low = 1, + .default_trigger = "none", + .default_state = LEDS_GPIO_DEFSTATE_ON, + } +}; + +static struct gpio_led_platform_data pcf_gpio_led_info3 = { + .leds = pcf_gpio_leds3, + .num_leds = ARRAY_SIZE(pcf_gpio_leds3), +}; + +static struct platform_device pcf_leds3 = { + .name = "leds-gpio", + .id = 3, + .dev = { + .platform_data = &pcf_gpio_led_info3, + } +}; + +static void __init gsia18s_pcf_leds_init(void) +{ + platform_device_register(&pcf_leds1); + platform_device_register(&pcf_leds2); + platform_device_register(&pcf_leds3); +} + +/* + * SPI busses. + */ +static struct spi_board_info gsia18s_spi_devices[] = { + { /* User accessible spi0, cs0 used for communication with MSP RTC */ + .modalias = "spidev", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 580000, + .mode = SPI_MODE_1, + }, + { /* User accessible spi1, cs0 used for communication with int. DSP */ + .modalias = "spidev", + .bus_num = 1, + .chip_select = 0, + .max_speed_hz = 5600000, + .mode = SPI_MODE_0, + }, + { /* User accessible spi1, cs1 used for communication with ext. DSP */ + .modalias = "spidev", + .bus_num = 1, + .chip_select = 1, + .max_speed_hz = 5600000, + .mode = SPI_MODE_0, + }, + { /* User accessible spi1, cs2 used for communication with ext. DSP */ + .modalias = "spidev", + .bus_num = 1, + .chip_select = 2, + .max_speed_hz = 5600000, + .mode = SPI_MODE_0, + }, + { /* User accessible spi1, cs3 used for communication with ext. DSP */ + .modalias = "spidev", + .bus_num = 1, + .chip_select = 3, + .max_speed_hz = 5600000, + .mode = SPI_MODE_0, + } +}; + +/* + * GPI Buttons + */ +static struct gpio_keys_button buttons[] = { + { + .gpio = GPIO_TRIG_NET_IN, + .code = BTN_1, + .desc = "TRIG_NET_IN", + .type = EV_KEY, + .active_low = 0, + .wakeup = 1, + }, + { /* SW80 on the GS_IA18_S-MN board*/ + .gpio = GPIO_CARD_UNMOUNT_0, + .code = BTN_2, + .desc = "Card umount 0", + .type = EV_KEY, + .active_low = 1, + .wakeup = 1, + }, + { /* SW79 on the GS_IA18_S-MN board*/ + .gpio = GPIO_CARD_UNMOUNT_1, + .code = BTN_3, + .desc = "Card umount 1", + .type = EV_KEY, + .active_low = 1, + .wakeup = 1, + }, + { /* SW280 on the GS_IA18-CB board*/ + .gpio = GPIO_KEY_POWER, + .code = KEY_POWER, + .desc = "Power Off Button", + .type = EV_KEY, + .active_low = 0, + .wakeup = 1, + } +}; + +static struct gpio_keys_platform_data button_data = { + .buttons = buttons, + .nbuttons = ARRAY_SIZE(buttons), +}; + +static struct platform_device button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &button_data, + } +}; + +static void __init gsia18s_add_device_buttons(void) +{ + at91_set_gpio_input(GPIO_TRIG_NET_IN, 1); + at91_set_deglitch(GPIO_TRIG_NET_IN, 1); + at91_set_gpio_input(GPIO_CARD_UNMOUNT_0, 1); + at91_set_deglitch(GPIO_CARD_UNMOUNT_0, 1); + at91_set_gpio_input(GPIO_CARD_UNMOUNT_1, 1); + at91_set_deglitch(GPIO_CARD_UNMOUNT_1, 1); + at91_set_gpio_input(GPIO_KEY_POWER, 0); + at91_set_deglitch(GPIO_KEY_POWER, 1); + + platform_device_register(&button_device); +} + +/* + * I2C + */ +static int pcf8574x_0x20_setup(struct i2c_client *client, int gpio, + unsigned int ngpio, void *context) +{ + int status; + + status = gpio_request(gpio + PCF_GPIO_ETH_DETECT, "eth_det"); + if (status < 0) { + pr_err("error: can't request GPIO%d\n", + gpio + PCF_GPIO_ETH_DETECT); + return status; + } + status = gpio_direction_input(gpio + PCF_GPIO_ETH_DETECT); + if (status < 0) { + pr_err("error: can't setup GPIO%d as input\n", + gpio + PCF_GPIO_ETH_DETECT); + return status; + } + status = gpio_export(gpio + PCF_GPIO_ETH_DETECT, false); + if (status < 0) { + pr_err("error: can't export GPIO%d\n", + gpio + PCF_GPIO_ETH_DETECT); + return status; + } + status = gpio_sysfs_set_active_low(gpio + PCF_GPIO_ETH_DETECT, 1); + if (status < 0) { + pr_err("error: gpio_sysfs_set active_low(GPIO%d, 1)\n", + gpio + PCF_GPIO_ETH_DETECT); + return status; + } + + return 0; +} + +static int pcf8574x_0x20_teardown(struct i2c_client *client, int gpio, + unsigned ngpio, void *context) +{ + gpio_free(gpio + PCF_GPIO_ETH_DETECT); + return 0; +} + +static struct pcf857x_platform_data pcf20_pdata = { + .gpio_base = GS_IA18_S_PCF_GPIO_BASE0, + .n_latch = (1 << 4), + .setup = pcf8574x_0x20_setup, + .teardown = pcf8574x_0x20_teardown, +}; + +static struct pcf857x_platform_data pcf22_pdata = { + .gpio_base = GS_IA18_S_PCF_GPIO_BASE1, +}; + +static struct pcf857x_platform_data pcf24_pdata = { + .gpio_base = GS_IA18_S_PCF_GPIO_BASE2, +}; + +static struct i2c_board_info __initdata gsia18s_i2c_devices[] = { + { /* U1 on the GS_IA18-CB_V3 board */ + I2C_BOARD_INFO("pcf8574", 0x20), + .platform_data = &pcf20_pdata, + }, + { /* U1 on the GS_2G_OPT1-A_V0 board (Alarm) */ + I2C_BOARD_INFO("pcf8574", 0x22), + .platform_data = &pcf22_pdata, + }, + { /* U1 on the GS_2G-OPT23-A_V0 board (Modem) */ + I2C_BOARD_INFO("pcf8574", 0x24), + .platform_data = &pcf24_pdata, + }, + { /* U161 on the GS_IA18_S-MN board */ + I2C_BOARD_INFO("24c1024", 0x50), + }, + { /* U162 on the GS_IA18_S-MN board */ + I2C_BOARD_INFO("24c01", 0x53), + }, +}; + +/* + * Compact Flash + */ +static struct at91_cf_data __initdata gsia18s_cf1_data = { + .irq_pin = AT91_PIN_PA27, + .det_pin = AT91_PIN_PB30, + .rst_pin = AT91_PIN_PB31, + .chipselect = 5, + .flags = AT91_CF_TRUE_IDE, +}; + +/* Power Off by RTC */ +static void gsia18s_power_off(void) +{ + pr_notice("Power supply will be switched off automatically now or after 60 seconds without ArmDAS.\n"); + at91_set_gpio_output(AT91_PIN_PA25, 1); + /* Spin to death... */ + while (1) + ; +} + +static int __init gsia18s_power_off_init(void) +{ + pm_power_off = gsia18s_power_off; + return 0; +} + +/* ---------------------------------------------------------------------------*/ + +static void __init gsia18s_board_init(void) +{ + stamp9g20_board_init(); + at91_add_device_usbh(&usbh_data); + at91_add_device_udc(&udc_data); + at91_add_device_eth(&macb_data); + gsia18s_leds_init(); + gsia18s_pcf_leds_init(); + gsia18s_add_device_buttons(); + at91_add_device_i2c(gsia18s_i2c_devices, + ARRAY_SIZE(gsia18s_i2c_devices)); + at91_add_device_cf(&gsia18s_cf1_data); + at91_add_device_spi(gsia18s_spi_devices, + ARRAY_SIZE(gsia18s_spi_devices)); + gsia18s_power_off_init(); +} + +MACHINE_START(GSIA18S, "GS_IA18_S") + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = gsia18s_map_io, + .init_irq = init_irq, + .init_machine = gsia18s_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index 86ff4b52db3..6c999dbd2bc 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c @@ -37,7 +37,6 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> #include <mach/board.h> #include <mach/gpio.h> #include <mach/at91sam9_smc.h> diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index ae4772e744a..af818a21587 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c @@ -274,10 +274,10 @@ EXPORT_SYMBOL(at91_get_gpio_value); static u32 wakeups[MAX_GPIO_BANKS]; static u32 backups[MAX_GPIO_BANKS]; -static int gpio_irq_set_wake(unsigned pin, unsigned state) +static int gpio_irq_set_wake(struct irq_data *d, unsigned state) { - unsigned mask = pin_to_mask(pin); - unsigned bank = (pin - PIN_BASE) / 32; + unsigned mask = pin_to_mask(d->irq); + unsigned bank = (d->irq - PIN_BASE) / 32; if (unlikely(bank >= MAX_GPIO_BANKS)) return -EINVAL; @@ -344,25 +344,25 @@ void at91_gpio_resume(void) * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. */ -static void gpio_irq_mask(unsigned pin) +static void gpio_irq_mask(struct irq_data *d) { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); + void __iomem *pio = pin_to_controller(d->irq); + unsigned mask = pin_to_mask(d->irq); if (pio) __raw_writel(mask, pio + PIO_IDR); } -static void gpio_irq_unmask(unsigned pin) +static void gpio_irq_unmask(struct irq_data *d) { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); + void __iomem *pio = pin_to_controller(d->irq); + unsigned mask = pin_to_mask(d->irq); if (pio) __raw_writel(mask, pio + PIO_IER); } -static int gpio_irq_type(unsigned pin, unsigned type) +static int gpio_irq_type(struct irq_data *d, unsigned type) { switch (type) { case IRQ_TYPE_NONE: @@ -375,10 +375,10 @@ static int gpio_irq_type(unsigned pin, unsigned type) static struct irq_chip gpio_irqchip = { .name = "GPIO", - .mask = gpio_irq_mask, - .unmask = gpio_irq_unmask, - .set_type = gpio_irq_type, - .set_wake = gpio_irq_set_wake, + .irq_mask = gpio_irq_mask, + .irq_unmask = gpio_irq_unmask, + .irq_set_type = gpio_irq_type, + .irq_set_wake = gpio_irq_set_wake, }; static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) @@ -393,7 +393,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) pio = at91_gpio->regbase; /* temporarily mask (level sensitive) parent IRQ */ - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); for (;;) { /* Reading ISR acks pending (edge triggered) GPIO interrupts. * When there none are pending, we're finished unless we need @@ -419,7 +419,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) * another IRQ must be generated before it actually gets * here to be disabled on the GPIO controller. */ - gpio_irq_mask(pin); + gpio_irq_mask(irq_get_irq_data(pin)); } else generic_handle_irq(pin); @@ -429,7 +429,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) isr >>= 1; } } - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); /* now it may re-trigger */ } diff --git a/arch/arm/mach-at91/include/mach/gsia18s.h b/arch/arm/mach-at91/include/mach/gsia18s.h new file mode 100644 index 00000000000..307c194926f --- /dev/null +++ b/arch/arm/mach-at91/include/mach/gsia18s.h @@ -0,0 +1,33 @@ +/* Buttons */ +#define GPIO_TRIG_NET_IN AT91_PIN_PB21 +#define GPIO_CARD_UNMOUNT_0 AT91_PIN_PB13 +#define GPIO_CARD_UNMOUNT_1 AT91_PIN_PB12 +#define GPIO_KEY_POWER AT91_PIN_PA25 + +/* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */ +#define GS_IA18_S_PCF_GPIO_BASE0 NR_BUILTIN_GPIO +#define PCF_GPIO_HDC_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 0) +#define PCF_GPIO_WIFI_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 1) +#define PCF_GPIO_WIFI_ENABLE (GS_IA18_S_PCF_GPIO_BASE0 + 2) +#define PCF_GPIO_WIFI_RESET (GS_IA18_S_PCF_GPIO_BASE0 + 3) +#define PCF_GPIO_ETH_DETECT 4 /* this is a GPI */ +#define PCF_GPIO_GPS_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 5) +#define PCF_GPIO_GPS_STANDBY (GS_IA18_S_PCF_GPIO_BASE0 + 6) +#define PCF_GPIO_GPS_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 7) + +/* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */ +#define GS_IA18_S_PCF_GPIO_BASE1 (GS_IA18_S_PCF_GPIO_BASE0 + 8) +#define PCF_GPIO_ALARM1 (GS_IA18_S_PCF_GPIO_BASE1 + 0) +#define PCF_GPIO_ALARM2 (GS_IA18_S_PCF_GPIO_BASE1 + 1) +#define PCF_GPIO_ALARM3 (GS_IA18_S_PCF_GPIO_BASE1 + 2) +#define PCF_GPIO_ALARM4 (GS_IA18_S_PCF_GPIO_BASE1 + 3) +/* bits 4, 5, 6 not used */ +#define PCF_GPIO_ALARM_V_RELAY_ON (GS_IA18_S_PCF_GPIO_BASE1 + 7) + +/* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */ +#define GS_IA18_S_PCF_GPIO_BASE2 (GS_IA18_S_PCF_GPIO_BASE1 + 8) +#define PCF_GPIO_MODEM_POWER (GS_IA18_S_PCF_GPIO_BASE2 + 0) +#define PCF_GPIO_MODEM_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 3) +/* bits 1, 2, 4, 5 not used */ +#define PCF_GPIO_TRX_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 6) +/* bit 7 not used */ diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c index da3494a5342..b56d6b3a408 100644 --- a/arch/arm/mach-at91/irq.c +++ b/arch/arm/mach-at91/irq.c @@ -34,23 +34,23 @@ #include <asm/mach/map.h> -static void at91_aic_mask_irq(unsigned int irq) +static void at91_aic_mask_irq(struct irq_data *d) { /* Disable interrupt on AIC */ - at91_sys_write(AT91_AIC_IDCR, 1 << irq); + at91_sys_write(AT91_AIC_IDCR, 1 << d->irq); } -static void at91_aic_unmask_irq(unsigned int irq) +static void at91_aic_unmask_irq(struct irq_data *d) { /* Enable interrupt on AIC */ - at91_sys_write(AT91_AIC_IECR, 1 << irq); + at91_sys_write(AT91_AIC_IECR, 1 << d->irq); } unsigned int at91_extern_irq; #define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq) -static int at91_aic_set_type(unsigned irq, unsigned type) +static int at91_aic_set_type(struct irq_data *d, unsigned type) { unsigned int smr, srctype; @@ -62,13 +62,13 @@ static int at91_aic_set_type(unsigned irq, unsigned type) srctype = AT91_AIC_SRCTYPE_RISING; break; case IRQ_TYPE_LEVEL_LOW: - if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */ + if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq)) /* only supported on external interrupts */ srctype = AT91_AIC_SRCTYPE_LOW; else return -EINVAL; break; case IRQ_TYPE_EDGE_FALLING: - if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */ + if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq)) /* only supported on external interrupts */ srctype = AT91_AIC_SRCTYPE_FALLING; else return -EINVAL; @@ -77,8 +77,8 @@ static int at91_aic_set_type(unsigned irq, unsigned type) return -EINVAL; } - smr = at91_sys_read(AT91_AIC_SMR(irq)) & ~AT91_AIC_SRCTYPE; - at91_sys_write(AT91_AIC_SMR(irq), smr | srctype); + smr = at91_sys_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE; + at91_sys_write(AT91_AIC_SMR(d->irq), smr | srctype); return 0; } @@ -87,15 +87,15 @@ static int at91_aic_set_type(unsigned irq, unsigned type) static u32 wakeups; static u32 backups; -static int at91_aic_set_wake(unsigned irq, unsigned value) +static int at91_aic_set_wake(struct irq_data *d, unsigned value) { - if (unlikely(irq >= 32)) + if (unlikely(d->irq >= 32)) return -EINVAL; if (value) - wakeups |= (1 << irq); + wakeups |= (1 << d->irq); else - wakeups &= ~(1 << irq); + wakeups &= ~(1 << d->irq); return 0; } @@ -119,11 +119,11 @@ void at91_irq_resume(void) static struct irq_chip at91_aic_chip = { .name = "AIC", - .ack = at91_aic_mask_irq, - .mask = at91_aic_mask_irq, - .unmask = at91_aic_unmask_irq, - .set_type = at91_aic_set_type, - .set_wake = at91_aic_set_wake, + .irq_ack = at91_aic_mask_irq, + .irq_mask = at91_aic_mask_irq, + .irq_unmask = at91_aic_unmask_irq, + .irq_set_type = at91_aic_set_type, + .irq_set_wake = at91_aic_set_wake, }; /* diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c index e3152631eb3..84dcda0d1d9 100644 --- a/arch/arm/mach-bcmring/irq.c +++ b/arch/arm/mach-bcmring/irq.c @@ -30,61 +30,61 @@ #include <mach/csp/intcHw_reg.h> #include <mach/csp/mm_io.h> -static void bcmring_mask_irq0(unsigned int irq) +static void bcmring_mask_irq0(struct irq_data *d) { - writel(1 << (irq - IRQ_INTC0_START), + writel(1 << (d->irq - IRQ_INTC0_START), MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR); } -static void bcmring_unmask_irq0(unsigned int irq) +static void bcmring_unmask_irq0(struct irq_data *d) { - writel(1 << (irq - IRQ_INTC0_START), + writel(1 << (d->irq - IRQ_INTC0_START), MM_IO_BASE_INTC0 + INTCHW_INTENABLE); } -static void bcmring_mask_irq1(unsigned int irq) +static void bcmring_mask_irq1(struct irq_data *d) { - writel(1 << (irq - IRQ_INTC1_START), + writel(1 << (d->irq - IRQ_INTC1_START), MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR); } -static void bcmring_unmask_irq1(unsigned int irq) +static void bcmring_unmask_irq1(struct irq_data *d) { - writel(1 << (irq - IRQ_INTC1_START), + writel(1 << (d->irq - IRQ_INTC1_START), MM_IO_BASE_INTC1 + INTCHW_INTENABLE); } -static void bcmring_mask_irq2(unsigned int irq) +static void bcmring_mask_irq2(struct irq_data *d) { - writel(1 << (irq - IRQ_SINTC_START), + writel(1 << (d->irq - IRQ_SINTC_START), MM_IO_BASE_SINTC + INTCHW_INTENCLEAR); } -static void bcmring_unmask_irq2(unsigned int irq) +static void bcmring_unmask_irq2(struct irq_data *d) { - writel(1 << (irq - IRQ_SINTC_START), + writel(1 << (d->irq - IRQ_SINTC_START), MM_IO_BASE_SINTC + INTCHW_INTENABLE); } static struct irq_chip bcmring_irq0_chip = { .name = "ARM-INTC0", - .ack = bcmring_mask_irq0, - .mask = bcmring_mask_irq0, /* mask a specific interrupt, blocking its delivery. */ - .unmask = bcmring_unmask_irq0, /* unmaks an interrupt */ + .irq_ack = bcmring_mask_irq0, + .irq_mask = bcmring_mask_irq0, /* mask a specific interrupt, blocking its delivery. */ + .irq_unmask = bcmring_unmask_irq0, /* unmaks an interrupt */ }; static struct irq_chip bcmring_irq1_chip = { .name = "ARM-INTC1", - .ack = bcmring_mask_irq1, - .mask = bcmring_mask_irq1, - .unmask = bcmring_unmask_irq1, + .irq_ack = bcmring_mask_irq1, + .irq_mask = bcmring_mask_irq1, + .irq_unmask = bcmring_unmask_irq1, }; static struct irq_chip bcmring_irq2_chip = { .name = "ARM-SINTC", - .ack = bcmring_mask_irq2, - .mask = bcmring_mask_irq2, - .unmask = bcmring_unmask_irq2, + .irq_ack = bcmring_mask_irq2, + .irq_mask = bcmring_mask_irq2, + .irq_unmask = bcmring_unmask_irq2, }; static void vic_init(void __iomem *base, struct irq_chip *chip, diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c index 9a12d856228..86da7a1b2bb 100644 --- a/arch/arm/mach-clps711x/irq.c +++ b/arch/arm/mach-clps711x/irq.c @@ -27,24 +27,24 @@ #include <asm/hardware/clps7111.h> -static void int1_mask(unsigned int irq) +static void int1_mask(struct irq_data *d) { u32 intmr1; intmr1 = clps_readl(INTMR1); - intmr1 &= ~(1 << irq); + intmr1 &= ~(1 << d->irq); clps_writel(intmr1, INTMR1); } -static void int1_ack(unsigned int irq) +static void int1_ack(struct irq_data *d) { u32 intmr1; intmr1 = clps_readl(INTMR1); - intmr1 &= ~(1 << irq); + intmr1 &= ~(1 << d->irq); clps_writel(intmr1, INTMR1); - switch (irq) { + switch (d->irq) { case IRQ_CSINT: clps_writel(0, COEOI); break; case IRQ_TC1OI: clps_writel(0, TC1EOI); break; case IRQ_TC2OI: clps_writel(0, TC2EOI); break; @@ -54,56 +54,56 @@ static void int1_ack(unsigned int irq) } } -static void int1_unmask(unsigned int irq) +static void int1_unmask(struct irq_data *d) { u32 intmr1; intmr1 = clps_readl(INTMR1); - intmr1 |= 1 << irq; + intmr1 |= 1 << d->irq; clps_writel(intmr1, INTMR1); } static struct irq_chip int1_chip = { - .ack = int1_ack, - .mask = int1_mask, - .unmask = int1_unmask, + .irq_ack = int1_ack, + .irq_mask = int1_mask, + .irq_unmask = int1_unmask, }; -static void int2_mask(unsigned int irq) +static void int2_mask(struct irq_data *d) { u32 intmr2; intmr2 = clps_readl(INTMR2); - intmr2 &= ~(1 << (irq - 16)); + intmr2 &= ~(1 << (d->irq - 16)); clps_writel(intmr2, INTMR2); } -static void int2_ack(unsigned int irq) +static void int2_ack(struct irq_data *d) { u32 intmr2; intmr2 = clps_readl(INTMR2); - intmr2 &= ~(1 << (irq - 16)); + intmr2 &= ~(1 << (d->irq - 16)); clps_writel(intmr2, INTMR2); - switch (irq) { + switch (d->irq) { case IRQ_KBDINT: clps_writel(0, KBDEOI); break; } } -static void int2_unmask(unsigned int irq) +static void int2_unmask(struct irq_data *d) { u32 intmr2; intmr2 = clps_readl(INTMR2); - intmr2 |= 1 << (irq - 16); + intmr2 |= 1 << (d->irq - 16); clps_writel(intmr2, INTMR2); } static struct irq_chip int2_chip = { - .ack = int2_ack, - .mask = int2_mask, - .unmask = int2_unmask, + .irq_ack = int2_ack, + .irq_mask = int2_mask, + .irq_unmask = int2_unmask, }; void __init clps711x_init_irq(void) diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index bb4c40ecb80..9abc80a86a2 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c @@ -26,30 +26,30 @@ static inline void cp_intc_write(unsigned long value, unsigned offset) __raw_writel(value, davinci_intc_base + offset); } -static void cp_intc_ack_irq(unsigned int irq) +static void cp_intc_ack_irq(struct irq_data *d) { - cp_intc_write(irq, CP_INTC_SYS_STAT_IDX_CLR); + cp_intc_write(d->irq, CP_INTC_SYS_STAT_IDX_CLR); } /* Disable interrupt */ -static void cp_intc_mask_irq(unsigned int irq) +static void cp_intc_mask_irq(struct irq_data *d) { /* XXX don't know why we need to disable nIRQ here... */ cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR); - cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_CLR); + cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_CLR); cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); } /* Enable interrupt */ -static void cp_intc_unmask_irq(unsigned int irq) +static void cp_intc_unmask_irq(struct irq_data *d) { - cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_SET); + cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_SET); } -static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type) +static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type) { - unsigned reg = BIT_WORD(irq); - unsigned mask = BIT_MASK(irq); + unsigned reg = BIT_WORD(d->irq); + unsigned mask = BIT_MASK(d->irq); unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg)); unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg)); @@ -85,18 +85,18 @@ static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type) * generic drivers which call {enable|disable}_irq_wake for * wake up interrupt sources (eg RTC on DA850). */ -static int cp_intc_set_wake(unsigned int irq, unsigned int on) +static int cp_intc_set_wake(struct irq_data *d, unsigned int on) { return 0; } static struct irq_chip cp_intc_irq_chip = { .name = "cp_intc", - .ack = cp_intc_ack_irq, - .mask = cp_intc_mask_irq, - .unmask = cp_intc_unmask_irq, - .set_type = cp_intc_set_irq_type, - .set_wake = cp_intc_set_wake, + .irq_ack = cp_intc_ack_irq, + .irq_mask = cp_intc_mask_irq, + .irq_unmask = cp_intc_unmask_irq, + .irq_set_type = cp_intc_set_irq_type, + .irq_set_wake = cp_intc_set_wake, }; void __init cp_intc_init(void) diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index bf0ff587e46..20d66e5e466 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -205,20 +205,20 @@ pure_initcall(davinci_gpio_setup); * serve as EDMA event triggers. */ -static void gpio_irq_disable(unsigned irq) +static void gpio_irq_disable(struct irq_data *d) { - struct davinci_gpio_regs __iomem *g = irq2regs(irq); - u32 mask = (u32) get_irq_data(irq); + struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); + u32 mask = (u32) irq_data_get_irq_data(d); __raw_writel(mask, &g->clr_falling); __raw_writel(mask, &g->clr_rising); } -static void gpio_irq_enable(unsigned irq) +static void gpio_irq_enable(struct irq_data *d) { - struct davinci_gpio_regs __iomem *g = irq2regs(irq); - u32 mask = (u32) get_irq_data(irq); - unsigned status = irq_desc[irq].status; + struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); + u32 mask = (u32) irq_data_get_irq_data(d); + unsigned status = irq_desc[d->irq].status; status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; if (!status) @@ -230,19 +230,19 @@ static void gpio_irq_enable(unsigned irq) __raw_writel(mask, &g->set_rising); } -static int gpio_irq_type(unsigned irq, unsigned trigger) +static int gpio_irq_type(struct irq_data *d, unsigned trigger) { - struct davinci_gpio_regs __iomem *g = irq2regs(irq); - u32 mask = (u32) get_irq_data(irq); + struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); + u32 mask = (u32) irq_data_get_irq_data(d); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) return -EINVAL; - irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; - irq_desc[irq].status |= trigger; + irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK; + irq_desc[d->irq].status |= trigger; /* don't enable the IRQ if it's currently disabled */ - if (irq_desc[irq].depth == 0) { + if (irq_desc[d->irq].depth == 0) { __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) ? &g->set_falling : &g->clr_falling); __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) @@ -253,9 +253,9 @@ static int gpio_irq_type(unsigned irq, unsigned trigger) static struct irq_chip gpio_irqchip = { .name = "GPIO", - .enable = gpio_irq_enable, - .disable = gpio_irq_disable, - .set_type = gpio_irq_type, + .irq_enable = gpio_irq_enable, + .irq_disable = gpio_irq_disable, + .irq_set_type = gpio_irq_type, }; static void @@ -269,8 +269,8 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) mask <<= 16; /* temporarily mask (level sensitive) parent IRQ */ - desc->chip->mask(irq); - desc->chip->ack(irq); + desc->irq_data.chip->irq_mask(&desc->irq_data); + desc->irq_data.chip->irq_ack(&desc->irq_data); while (1) { u32 status; int n; @@ -293,7 +293,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) status >>= res; } } - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); /* now it may re-trigger */ } @@ -320,10 +320,10 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) return -ENODEV; } -static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) +static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger) { - struct davinci_gpio_regs __iomem *g = irq2regs(irq); - u32 mask = (u32) get_irq_data(irq); + struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); + u32 mask = (u32) irq_data_get_irq_data(d); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) return -EINVAL; @@ -397,7 +397,7 @@ static int __init davinci_gpio_irq_setup(void) irq = bank_irq; gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq)); gpio_irqchip_unbanked.name = "GPIO-AINTC"; - gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked; + gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked; /* default trigger: both edges */ g = gpio2regs(0); diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index 784ddf3c5ad..5e05c9b64e1 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -53,14 +53,14 @@ static inline void davinci_irq_writel(unsigned long value, int offset) } /* Disable interrupt */ -static void davinci_mask_irq(unsigned int irq) +static void davinci_mask_irq(struct irq_data *d) { unsigned int mask; u32 l; - mask = 1 << IRQ_BIT(irq); + mask = 1 << IRQ_BIT(d->irq); - if (irq > 31) { + if (d->irq > 31) { l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); l &= ~mask; davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); @@ -72,14 +72,14 @@ static void davinci_mask_irq(unsigned int irq) } /* Enable interrupt */ -static void davinci_unmask_irq(unsigned int irq) +static void davinci_unmask_irq(struct irq_data *d) { unsigned int mask; u32 l; - mask = 1 << IRQ_BIT(irq); + mask = 1 << IRQ_BIT(d->irq); - if (irq > 31) { + if (d->irq > 31) { l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); l |= mask; davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); @@ -91,23 +91,23 @@ static void davinci_unmask_irq(unsigned int irq) } /* EOI interrupt */ -static void davinci_ack_irq(unsigned int irq) +static void davinci_ack_irq(struct irq_data *d) { unsigned int mask; - mask = 1 << IRQ_BIT(irq); + mask = 1 << IRQ_BIT(d->irq); - if (irq > 31) + if (d->irq > 31) davinci_irq_writel(mask, IRQ_REG1_OFFSET); else davinci_irq_writel(mask, IRQ_REG0_OFFSET); } static struct irq_chip davinci_irq_chip_0 = { - .name = "AINTC", - .ack = davinci_ack_irq, - .mask = davinci_mask_irq, - .unmask = davinci_unmask_irq, + .name = "AINTC", + .irq_ack = davinci_ack_irq, + .irq_mask = davinci_mask_irq, + .irq_unmask = davinci_unmask_irq, }; /* ARM Interrupt Controller Initialization */ diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index 61bfcb3b08c..9317f0558b5 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c @@ -36,9 +36,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) } } -static void pmu_irq_mask(unsigned int irq) +static void pmu_irq_mask(struct irq_data *d) { - int pin = irq_to_pmu(irq); + int pin = irq_to_pmu(d->irq); u32 u; u = readl(PMU_INTERRUPT_MASK); @@ -46,9 +46,9 @@ static void pmu_irq_mask(unsigned int irq) writel(u, PMU_INTERRUPT_MASK); } -static void pmu_irq_unmask(unsigned int irq) +static void pmu_irq_unmask(struct irq_data *d) { - int pin = irq_to_pmu(irq); + int pin = irq_to_pmu(d->irq); u32 u; u = readl(PMU_INTERRUPT_MASK); @@ -56,9 +56,9 @@ static void pmu_irq_unmask(unsigned int irq) writel(u, PMU_INTERRUPT_MASK); } -static void pmu_irq_ack(unsigned int irq) +static void pmu_irq_ack(struct irq_data *d) { - int pin = irq_to_pmu(irq); + int pin = irq_to_pmu(d->irq); u32 u; u = ~(1 << (pin & 31)); @@ -67,9 +67,9 @@ static void pmu_irq_ack(unsigned int irq) static struct irq_chip pmu_irq_chip = { .name = "pmu_irq", - .mask = pmu_irq_mask, - .unmask = pmu_irq_unmask, - .ack = pmu_irq_ack, + .irq_mask = pmu_irq_mask, + .irq_unmask = pmu_irq_unmask, + .irq_ack = pmu_irq_ack, }; static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc) diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c index 5df4099fc14..7df083f37fa 100644 --- a/arch/arm/mach-ebsa110/core.c +++ b/arch/arm/mach-ebsa110/core.c @@ -35,20 +35,20 @@ #define IRQ_STAT 0xff000000 /* read */ #define IRQ_MCLR 0xff000000 /* write */ -static void ebsa110_mask_irq(unsigned int irq) +static void ebsa110_mask_irq(struct irq_data *d) { - __raw_writeb(1 << irq, IRQ_MCLR); + __raw_writeb(1 << d->irq, IRQ_MCLR); } -static void ebsa110_unmask_irq(unsigned int irq) +static void ebsa110_unmask_irq(struct irq_data *d) { - __raw_writeb(1 << irq, IRQ_MSET); + __raw_writeb(1 << d->irq, IRQ_MSET); } static struct irq_chip ebsa110_irq_chip = { - .ack = ebsa110_mask_irq, - .mask = ebsa110_mask_irq, - .unmask = ebsa110_unmask_irq, + .irq_ack = ebsa110_mask_irq, + .irq_mask = ebsa110_mask_irq, + .irq_unmask = ebsa110_unmask_irq, }; static void __init ebsa110_init_irq(void) diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c index cf547ad7ebd..f3dc76fdcea 100644 --- a/arch/arm/mach-ep93xx/gpio.c +++ b/arch/arm/mach-ep93xx/gpio.c @@ -112,13 +112,13 @@ static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc) generic_handle_irq(gpio_irq); } -static void ep93xx_gpio_irq_ack(unsigned int irq) +static void ep93xx_gpio_irq_ack(struct irq_data *d) { - int line = irq_to_gpio(irq); + int line = irq_to_gpio(d->irq); int port = line >> 3; int port_mask = 1 << (line & 7); - if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { + if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { gpio_int_type2[port] ^= port_mask; /* switch edge direction */ ep93xx_gpio_update_int_params(port); } @@ -126,13 +126,13 @@ static void ep93xx_gpio_irq_ack(unsigned int irq) __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); } -static void ep93xx_gpio_irq_mask_ack(unsigned int irq) +static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { - int line = irq_to_gpio(irq); + int line = irq_to_gpio(d->irq); int port = line >> 3; int port_mask = 1 << (line & 7); - if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) + if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) gpio_int_type2[port] ^= port_mask; /* switch edge direction */ gpio_int_unmasked[port] &= ~port_mask; @@ -141,18 +141,18 @@ static void ep93xx_gpio_irq_mask_ack(unsigned int irq) __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); } -static void ep93xx_gpio_irq_mask(unsigned int irq) +static void ep93xx_gpio_irq_mask(struct irq_data *d) { - int line = irq_to_gpio(irq); + int line = irq_to_gpio(d->irq); int port = line >> 3; gpio_int_unmasked[port] &= ~(1 << (line & 7)); ep93xx_gpio_update_int_params(port); } -static void ep93xx_gpio_irq_unmask(unsigned int irq) +static void ep93xx_gpio_irq_unmask(struct irq_data *d) { - int line = irq_to_gpio(irq); + int line = irq_to_gpio(d->irq); int port = line >> 3; gpio_int_unmasked[port] |= 1 << (line & 7); @@ -164,10 +164,10 @@ static void ep93xx_gpio_irq_unmask(unsigned int irq) * edge (1) triggered, while gpio_int_type2 controls whether it * triggers on low/falling (0) or high/rising (1). */ -static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type) +static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) { - struct irq_desc *desc = irq_desc + irq; - const int gpio = irq_to_gpio(irq); + struct irq_desc *desc = irq_desc + d->irq; + const int gpio = irq_to_gpio(d->irq); const int port = gpio >> 3; const int port_mask = 1 << (gpio & 7); @@ -220,11 +220,11 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type) static struct irq_chip ep93xx_gpio_irq_chip = { .name = "GPIO", - .ack = ep93xx_gpio_irq_ack, - .mask_ack = ep93xx_gpio_irq_mask_ack, - .mask = ep93xx_gpio_irq_mask, - .unmask = ep93xx_gpio_irq_unmask, - .set_type = ep93xx_gpio_irq_type, + .irq_ack = ep93xx_gpio_irq_ack, + .irq_mask_ack = ep93xx_gpio_irq_mask_ack, + .irq_mask = ep93xx_gpio_irq_mask, + .irq_unmask = ep93xx_gpio_irq_unmask, + .irq_set_type = ep93xx_gpio_irq_type, }; void __init ep93xx_gpio_init_irq(void) diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index 88b3dd89be8..84c5f258f2d 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c @@ -75,20 +75,20 @@ static const int fb_irq_mask[] = { IRQ_MASK_PCI_PERR, /* 19 */ }; -static void fb_mask_irq(unsigned int irq) +static void fb_mask_irq(struct irq_data *d) { - *CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(irq)]; + *CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(d->irq)]; } -static void fb_unmask_irq(unsigned int irq) +static void fb_unmask_irq(struct irq_data *d) { - *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(irq)]; + *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(d->irq)]; } static struct irq_chip fb_chip = { - .ack = fb_mask_irq, - .mask = fb_mask_irq, - .unmask = fb_unmask_irq, + .irq_ack = fb_mask_irq, + .irq_mask = fb_mask_irq, + .irq_unmask = fb_unmask_irq, }; static void __init __fb_init_irq(void) diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c index 8bfd06aeb64..de7a5cb5dbe 100644 --- a/arch/arm/mach-footbridge/isa-irq.c +++ b/arch/arm/mach-footbridge/isa-irq.c @@ -30,61 +30,61 @@ #include "common.h" -static void isa_mask_pic_lo_irq(unsigned int irq) +static void isa_mask_pic_lo_irq(struct irq_data *d) { - unsigned int mask = 1 << (irq & 7); + unsigned int mask = 1 << (d->irq & 7); outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO); } -static void isa_ack_pic_lo_irq(unsigned int irq) +static void isa_ack_pic_lo_irq(struct irq_data *d) { - unsigned int mask = 1 << (irq & 7); + unsigned int mask = 1 << (d->irq & 7); outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO); outb(0x20, PIC_LO); } -static void isa_unmask_pic_lo_irq(unsigned int irq) +static void isa_unmask_pic_lo_irq(struct irq_data *d) { - unsigned int mask = 1 << (irq & 7); + unsigned int mask = 1 << (d->irq & 7); outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO); } static struct irq_chip isa_lo_chip = { - .ack = isa_ack_pic_lo_irq, - .mask = isa_mask_pic_lo_irq, - .unmask = isa_unmask_pic_lo_irq, + .irq_ack = isa_ack_pic_lo_irq, + .irq_mask = isa_mask_pic_lo_irq, + .irq_unmask = isa_unmask_pic_lo_irq, }; -static void isa_mask_pic_hi_irq(unsigned int irq) +static void isa_mask_pic_hi_irq(struct irq_data *d) { - unsigned int mask = 1 << (irq & 7); + unsigned int mask = 1 << (d->irq & 7); outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI); } -static void isa_ack_pic_hi_irq(unsigned int irq) +static void isa_ack_pic_hi_irq(struct irq_data *d) { - unsigned int mask = 1 << (irq & 7); + unsigned int mask = 1 << (d->irq & 7); outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI); outb(0x62, PIC_LO); outb(0x20, PIC_HI); } -static void isa_unmask_pic_hi_irq(unsigned int irq) +static void isa_unmask_pic_hi_irq(struct irq_data *d) { - unsigned int mask = 1 << (irq & 7); + unsigned int mask = 1 << (d->irq & 7); outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI); } static struct irq_chip isa_hi_chip = { - .ack = isa_ack_pic_hi_irq, - .mask = isa_mask_pic_hi_irq, - .unmask = isa_unmask_pic_hi_irq, + .irq_ack = isa_ack_pic_hi_irq, + .irq_mask = isa_mask_pic_hi_irq, + .irq_unmask = isa_unmask_pic_hi_irq, }; static void diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c index fe3bd5ac8b1..fa3d333f21e 100644 --- a/arch/arm/mach-gemini/gpio.c +++ b/arch/arm/mach-gemini/gpio.c @@ -54,33 +54,33 @@ static void _set_gpio_irqenable(unsigned int base, unsigned int index, __raw_writel(reg, base + GPIO_INT_EN); } -static void gpio_ack_irq(unsigned int irq) +static void gpio_ack_irq(struct irq_data *d) { - unsigned int gpio = irq_to_gpio(irq); + unsigned int gpio = irq_to_gpio(d->irq); unsigned int base = GPIO_BASE(gpio / 32); __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR); } -static void gpio_mask_irq(unsigned int irq) +static void gpio_mask_irq(struct irq_data *d) { - unsigned int gpio = irq_to_gpio(irq); + unsigned int gpio = irq_to_gpio(d->irq); unsigned int base = GPIO_BASE(gpio / 32); _set_gpio_irqenable(base, gpio % 32, 0); } -static void gpio_unmask_irq(unsigned int irq) +static void gpio_unmask_irq(struct irq_data *d) { - unsigned int gpio = irq_to_gpio(irq); + unsigned int gpio = irq_to_gpio(d->irq); unsigned int base = GPIO_BASE(gpio / 32); _set_gpio_irqenable(base, gpio % 32, 1); } -static int gpio_set_irq_type(unsigned int irq, unsigned int type) +static int gpio_set_irq_type(struct irq_data *d, unsigned int type) { - unsigned int gpio = irq_to_gpio(irq); + unsigned int gpio = irq_to_gpio(d->irq); unsigned int gpio_mask = 1 << (gpio % 32); unsigned int base = GPIO_BASE(gpio / 32); unsigned int reg_both, reg_level, reg_type; @@ -120,7 +120,7 @@ static int gpio_set_irq_type(unsigned int irq, unsigned int type) __raw_writel(reg_level, base + GPIO_INT_LEVEL); __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE); - gpio_ack_irq(irq); + gpio_ack_irq(d->irq); return 0; } @@ -146,10 +146,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) static struct irq_chip gpio_irq_chip = { .name = "GPIO", - .ack = gpio_ack_irq, - .mask = gpio_mask_irq, - .unmask = gpio_unmask_irq, - .set_type = gpio_set_irq_type, + .irq_ack = gpio_ack_irq, + .irq_mask = gpio_mask_irq, + .irq_unmask = gpio_unmask_irq, + .irq_set_type = gpio_set_irq_type, }; static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c index 9e613ca8120..96bc227dd84 100644 --- a/arch/arm/mach-gemini/irq.c +++ b/arch/arm/mach-gemini/irq.c @@ -32,34 +32,34 @@ #define FIQ_LEVEL(base_addr) (base_addr + 0x30) #define FIQ_STATUS(base_addr) (base_addr + 0x34) -static void gemini_ack_irq(unsigned int irq) +static void gemini_ack_irq(struct irq_data *d) { - __raw_writel(1 << irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); + __raw_writel(1 << d->irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); } -static void gemini_mask_irq(unsigned int irq) +static void gemini_mask_irq(struct irq_data *d) { unsigned int mask; mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); - mask &= ~(1 << irq); + mask &= ~(1 << d->irq); __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); } -static void gemini_unmask_irq(unsigned int irq) +static void gemini_unmask_irq(struct irq_data *d) { unsigned int mask; mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); - mask |= (1 << irq); + mask |= (1 << d->irq); __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); } static struct irq_chip gemini_irq_chip = { - .name = "INTC", - .ack = gemini_ack_irq, - .mask = gemini_mask_irq, - .unmask = gemini_unmask_irq, + .name = "INTC", + .irq_ack = gemini_ack_irq, + .irq_mask = gemini_mask_irq, + .irq_unmask = gemini_unmask_irq, }; static struct resource irq_resource = { diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c index bdb3f670680..1f28c90932c 100644 --- a/arch/arm/mach-h720x/common.c +++ b/arch/arm/mach-h720x/common.c @@ -52,17 +52,17 @@ unsigned long h720x_gettimeoffset(void) /* * mask Global irq's */ -static void mask_global_irq (unsigned int irq ) +static void mask_global_irq(struct irq_data *d) { - CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq); + CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << d->irq); } /* * unmask Global irq's */ -static void unmask_global_irq (unsigned int irq ) +static void unmask_global_irq(struct irq_data *d) { - CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq); + CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << d->irq); } @@ -70,10 +70,10 @@ static void unmask_global_irq (unsigned int irq ) * ack GPIO irq's * Ack only for edge triggered int's valid */ -static void inline ack_gpio_irq(u32 irq) +static void inline ack_gpio_irq(struct irq_data *d) { - u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq)); - u32 bit = IRQ_TO_BIT(irq); + u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq)); + u32 bit = IRQ_TO_BIT(d->irq); if ( (CPU_REG (reg_base, GPIO_EDGE) & bit)) CPU_REG (reg_base, GPIO_CLR) = bit; } @@ -81,20 +81,20 @@ static void inline ack_gpio_irq(u32 irq) /* * mask GPIO irq's */ -static void inline mask_gpio_irq(u32 irq) +static void inline mask_gpio_irq(struct irq_data *d) { - u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq)); - u32 bit = IRQ_TO_BIT(irq); + u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq)); + u32 bit = IRQ_TO_BIT(d->irq); CPU_REG (reg_base, GPIO_MASK) &= ~bit; } /* * unmask GPIO irq's */ -static void inline unmask_gpio_irq(u32 irq) +static void inline unmask_gpio_irq(struct irq_data *d) { - u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq)); - u32 bit = IRQ_TO_BIT(irq); + u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq)); + u32 bit = IRQ_TO_BIT(d->irq); CPU_REG (reg_base, GPIO_MASK) |= bit; } @@ -170,15 +170,15 @@ h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc) #endif static struct irq_chip h720x_global_chip = { - .ack = mask_global_irq, - .mask = mask_global_irq, - .unmask = unmask_global_irq, + .irq_ack = mask_global_irq, + .irq_mask = mask_global_irq, + .irq_unmask = unmask_global_irq, }; static struct irq_chip h720x_gpio_chip = { - .ack = ack_gpio_irq, - .mask = mask_gpio_irq, - .unmask = unmask_gpio_irq, + .irq_ack = ack_gpio_irq, + .irq_mask = mask_gpio_irq, + .irq_unmask = unmask_gpio_irq, }; /* diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c index fd33a19c813..ac3f9144237 100644 --- a/arch/arm/mach-h720x/cpu-h7202.c +++ b/arch/arm/mach-h720x/cpu-h7202.c @@ -141,27 +141,27 @@ h7202_timer_interrupt(int irq, void *dev_id) /* * mask multiplexed timer IRQs */ -static void inline mask_timerx_irq (u32 irq) +static void inline mask_timerx_irq(struct irq_data *d) { unsigned int bit; - bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1)); + bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1)); CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit; } /* * unmask multiplexed timer IRQs */ -static void inline unmask_timerx_irq (u32 irq) +static void inline unmask_timerx_irq(struct irq_data *d) { unsigned int bit; - bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1)); + bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1)); CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit; } static struct irq_chip h7202_timerx_chip = { - .ack = mask_timerx_irq, - .mask = mask_timerx_irq, - .unmask = unmask_timerx_irq, + .irq_ack = mask_timerx_irq, + .irq_mask = mask_timerx_irq, + .irq_unmask = unmask_timerx_irq, }; static struct irqaction h7202_timer_irq = { diff --git a/arch/arm/mach-h720x/h7201-eval.c b/arch/arm/mach-h720x/h7201-eval.c index 79f0b896e44..629454d71c8 100644 --- a/arch/arm/mach-h720x/h7201-eval.c +++ b/arch/arm/mach-h720x/h7201-eval.c @@ -23,7 +23,6 @@ #include <asm/types.h> #include <asm/mach-types.h> #include <asm/page.h> -#include <asm/pgtable.h> #include <asm/mach/arch.h> #include <mach/hardware.h> #include "common.h" diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c index cc28b1efe04..e9f46b69635 100644 --- a/arch/arm/mach-h720x/h7202-eval.c +++ b/arch/arm/mach-h720x/h7202-eval.c @@ -23,7 +23,6 @@ #include <asm/types.h> #include <asm/mach-types.h> #include <asm/page.h> -#include <asm/pgtable.h> #include <asm/mach/arch.h> #include <mach/irqs.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 17d2e608a21..56684b51707 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -243,6 +243,7 @@ config MACH_MX27_3DS select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_SPI_IMX + select MXC_DEBUG_BOARD select MXC_ULPI if USB_ULPI help Include support for MX27PDK platform. This includes specific diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index 6fd0f8f6deb..164331518bd 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -37,12 +37,15 @@ #include <mach/common.h> #include <mach/iomux-mx27.h> #include <mach/ulpi.h> +#include <mach/irqs.h> +#include <mach/3ds_debugboard.h> #include "devices-imx27.h" #define SD1_EN_GPIO (GPIO_PORTB + 25) #define OTG_PHY_RESET_GPIO (GPIO_PORTB + 23) #define SPI2_SS0 (GPIO_PORTD + 21) +#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTC + 28) static const int mx27pdk_pins[] __initconst = { /* UART1 */ @@ -215,10 +218,10 @@ static struct regulator_init_data vgen_init = { static struct mc13783_regulator_init_data mx27_3ds_regulators[] = { { - .id = MC13783_REGU_VMMC1, + .id = MC13783_REG_VMMC1, .init_data = &vmmc1_init, }, { - .id = MC13783_REGU_VGEN, + .id = MC13783_REG_VGEN, .init_data = &vgen_init, }, }; @@ -276,6 +279,9 @@ static void __init mx27pdk_init(void) imx27_add_spi_imx1(&spi2_pdata); spi_register_board_info(mx27_3ds_spi_devs, ARRAY_SIZE(mx27_3ds_spi_devs)); + + if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT)) + pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n"); } static void __init mx27pdk_timer_init(void) diff --git a/arch/arm/mach-integrator/cpu.c b/arch/arm/mach-integrator/cpu.c index a3fbcb3adc2..fbb45777989 100644 --- a/arch/arm/mach-integrator/cpu.c +++ b/arch/arm/mach-integrator/cpu.c @@ -173,7 +173,7 @@ static unsigned int integrator_get(unsigned int cpu) if (machine_is_integrator()) { vco.s = (cm_osc >> 8) & 7; - } else if (machine_is_cintegrator()) { + } else { vco.s = 1; } vco.v = cm_osc & 255; diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 2774df8021d..b666443b5cb 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -156,21 +156,21 @@ static void __init ap_map_io(void) #define INTEGRATOR_SC_VALID_INT 0x003fffff -static void sc_mask_irq(unsigned int irq) +static void sc_mask_irq(struct irq_data *d) { - writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_CLEAR); + writel(1 << d->irq, VA_IC_BASE + IRQ_ENABLE_CLEAR); } -static void sc_unmask_irq(unsigned int irq) +static void sc_unmask_irq(struct irq_data *d) { - writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_SET); + writel(1 << d->irq, VA_IC_BASE + IRQ_ENABLE_SET); } static struct irq_chip sc_chip = { - .name = "SC", - .ack = sc_mask_irq, - .mask = sc_mask_irq, - .unmask = sc_unmask_irq, + .name = "SC", + .irq_ack = sc_mask_irq, + .irq_mask = sc_mask_irq, + .irq_unmask = sc_unmask_irq, }; static void __init ap_init_irq(void) diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 85e48a5f77b..e9327da1382 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -146,61 +146,61 @@ static void __init intcp_map_io(void) #define sic_writel __raw_writel #define sic_readl __raw_readl -static void cic_mask_irq(unsigned int irq) +static void cic_mask_irq(struct irq_data *d) { - irq -= IRQ_CIC_START; + unsigned int irq = d->irq - IRQ_CIC_START; cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); } -static void cic_unmask_irq(unsigned int irq) +static void cic_unmask_irq(struct irq_data *d) { - irq -= IRQ_CIC_START; + unsigned int irq = d->irq - IRQ_CIC_START; cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET); } static struct irq_chip cic_chip = { - .name = "CIC", - .ack = cic_mask_irq, - .mask = cic_mask_irq, - .unmask = cic_unmask_irq, + .name = "CIC", + .irq_ack = cic_mask_irq, + .irq_mask = cic_mask_irq, + .irq_unmask = cic_unmask_irq, }; -static void pic_mask_irq(unsigned int irq) +static void pic_mask_irq(struct irq_data *d) { - irq -= IRQ_PIC_START; + unsigned int irq = d->irq - IRQ_PIC_START; pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); } -static void pic_unmask_irq(unsigned int irq) +static void pic_unmask_irq(struct irq_data *d) { - irq -= IRQ_PIC_START; + unsigned int irq = d->irq - IRQ_PIC_START; pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET); } static struct irq_chip pic_chip = { - .name = "PIC", - .ack = pic_mask_irq, - .mask = pic_mask_irq, - .unmask = pic_unmask_irq, + .name = "PIC", + .irq_ack = pic_mask_irq, + .irq_mask = pic_mask_irq, + .irq_unmask = pic_unmask_irq, }; -static void sic_mask_irq(unsigned int irq) +static void sic_mask_irq(struct irq_data *d) { - irq -= IRQ_SIC_START; + unsigned int irq = d->irq - IRQ_SIC_START; sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); } -static void sic_unmask_irq(unsigned int irq) +static void sic_unmask_irq(struct irq_data *d) { - irq -= IRQ_SIC_START; + unsigned int irq = d->irq - IRQ_SIC_START; sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET); } static struct irq_chip sic_chip = { - .name = "SIC", - .ack = sic_mask_irq, - .mask = sic_mask_irq, - .unmask = sic_unmask_irq, + .name = "SIC", + .irq_ack = sic_mask_irq, + .irq_mask = sic_mask_irq, + .irq_unmask = sic_unmask_irq, }; static void diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index 0d099ca87bd..a233470dd10 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c @@ -123,79 +123,79 @@ static void write_intsize(u32 val) /* 0 = Interrupt Masked and 1 = Interrupt not masked */ static void -iop13xx_irq_mask0 (unsigned int irq) +iop13xx_irq_mask0 (struct irq_data *d) { - write_intctl_0(read_intctl_0() & ~(1 << (irq - 0))); + write_intctl_0(read_intctl_0() & ~(1 << (d->irq - 0))); } static void -iop13xx_irq_mask1 (unsigned int irq) +iop13xx_irq_mask1 (struct irq_data *d) { - write_intctl_1(read_intctl_1() & ~(1 << (irq - 32))); + write_intctl_1(read_intctl_1() & ~(1 << (d->irq - 32))); } static void -iop13xx_irq_mask2 (unsigned int irq) +iop13xx_irq_mask2 (struct irq_data *d) { - write_intctl_2(read_intctl_2() & ~(1 << (irq - 64))); + write_intctl_2(read_intctl_2() & ~(1 << (d->irq - 64))); } static void -iop13xx_irq_mask3 (unsigned int irq) +iop13xx_irq_mask3 (struct irq_data *d) { - write_intctl_3(read_intctl_3() & ~(1 << (irq - 96))); + write_intctl_3(read_intctl_3() & ~(1 << (d->irq - 96))); } static void -iop13xx_irq_unmask0(unsigned int irq) +iop13xx_irq_unmask0(struct irq_data *d) { - write_intctl_0(read_intctl_0() | (1 << (irq - 0))); + write_intctl_0(read_intctl_0() | (1 << (d->irq - 0))); } static void -iop13xx_irq_unmask1(unsigned int irq) +iop13xx_irq_unmask1(struct irq_data *d) { - write_intctl_1(read_intctl_1() | (1 << (irq - 32))); + write_intctl_1(read_intctl_1() | (1 << (d->irq - 32))); } static void -iop13xx_irq_unmask2(unsigned int irq) +iop13xx_irq_unmask2(struct irq_data *d) { - write_intctl_2(read_intctl_2() | (1 << (irq - 64))); + write_intctl_2(read_intctl_2() | (1 << (d->irq - 64))); } static void -iop13xx_irq_unmask3(unsigned int irq) +iop13xx_irq_unmask3(struct irq_data *d) { - write_intctl_3(read_intctl_3() | (1 << (irq - 96))); + write_intctl_3(read_intctl_3() | (1 << (d->irq - 96))); } static struct irq_chip iop13xx_irqchip1 = { - .name = "IOP13xx-1", - .ack = iop13xx_irq_mask0, - .mask = iop13xx_irq_mask0, - .unmask = iop13xx_irq_unmask0, + .name = "IOP13xx-1", + .irq_ack = iop13xx_irq_mask0, + .irq_mask = iop13xx_irq_mask0, + .irq_unmask = iop13xx_irq_unmask0, }; static struct irq_chip iop13xx_irqchip2 = { - .name = "IOP13xx-2", - .ack = iop13xx_irq_mask1, - .mask = iop13xx_irq_mask1, - .unmask = iop13xx_irq_unmask1, + .name = "IOP13xx-2", + .irq_ack = iop13xx_irq_mask1, + .irq_mask = iop13xx_irq_mask1, + .irq_unmask = iop13xx_irq_unmask1, }; static struct irq_chip iop13xx_irqchip3 = { - .name = "IOP13xx-3", - .ack = iop13xx_irq_mask2, - .mask = iop13xx_irq_mask2, - .unmask = iop13xx_irq_unmask2, + .name = "IOP13xx-3", + .irq_ack = iop13xx_irq_mask2, + .irq_mask = iop13xx_irq_mask2, + .irq_unmask = iop13xx_irq_unmask2, }; static struct irq_chip iop13xx_irqchip4 = { - .name = "IOP13xx-4", - .ack = iop13xx_irq_mask3, - .mask = iop13xx_irq_mask3, - .unmask = iop13xx_irq_unmask3, + .name = "IOP13xx-4", + .irq_ack = iop13xx_irq_mask3, + .irq_mask = iop13xx_irq_mask3, + .irq_unmask = iop13xx_irq_unmask3, }; extern void iop_init_cp6_handler(void); diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c index 7149fcc16c8..c9c02e3698b 100644 --- a/arch/arm/mach-iop13xx/msi.c +++ b/arch/arm/mach-iop13xx/msi.c @@ -156,14 +156,14 @@ void arch_teardown_msi_irq(unsigned int irq) destroy_irq(irq); } -static void iop13xx_msi_nop(unsigned int irq) +static void iop13xx_msi_nop(struct irq_data *d) { return; } static struct irq_chip iop13xx_msi_chip = { .name = "PCI-MSI", - .ack = iop13xx_msi_nop, + .irq_ack = iop13xx_msi_nop, .irq_enable = unmask_msi_irq, .irq_disable = mask_msi_irq, .irq_mask = mask_msi_irq, diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index ba59b2d17db..d3426a12059 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -32,24 +32,24 @@ static void intstr_write(u32 val) } static void -iop32x_irq_mask(unsigned int irq) +iop32x_irq_mask(struct irq_data *d) { - iop32x_mask &= ~(1 << irq); + iop32x_mask &= ~(1 << d->irq); intctl_write(iop32x_mask); } static void -iop32x_irq_unmask(unsigned int irq) +iop32x_irq_unmask(struct irq_data *d) { - iop32x_mask |= 1 << irq; + iop32x_mask |= 1 << d->irq; intctl_write(iop32x_mask); } struct irq_chip ext_chip = { - .name = "IOP32x", - .ack = iop32x_irq_mask, - .mask = iop32x_irq_mask, - .unmask = iop32x_irq_unmask, + .name = "IOP32x", + .irq_ack = iop32x_irq_mask, + .irq_mask = iop32x_irq_mask, + .irq_unmask = iop32x_irq_unmask, }; void __init iop32x_init_irq(void) diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index abb4ea2ed4f..0ff2f74363a 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -53,45 +53,45 @@ static void intsize_write(u32 val) } static void -iop33x_irq_mask1 (unsigned int irq) +iop33x_irq_mask1 (struct irq_data *d) { - iop33x_mask0 &= ~(1 << irq); + iop33x_mask0 &= ~(1 << d->irq); intctl0_write(iop33x_mask0); } static void -iop33x_irq_mask2 (unsigned int irq) +iop33x_irq_mask2 (struct irq_data *d) { - iop33x_mask1 &= ~(1 << (irq - 32)); + iop33x_mask1 &= ~(1 << (d->irq - 32)); intctl1_write(iop33x_mask1); } static void -iop33x_irq_unmask1(unsigned int irq) +iop33x_irq_unmask1(struct irq_data *d) { - iop33x_mask0 |= 1 << irq; + iop33x_mask0 |= 1 << d->irq; intctl0_write(iop33x_mask0); } static void -iop33x_irq_unmask2(unsigned int irq) +iop33x_irq_unmask2(struct irq_data *d) { - iop33x_mask1 |= (1 << (irq - 32)); + iop33x_mask1 |= (1 << (d->irq - 32)); intctl1_write(iop33x_mask1); } struct irq_chip iop33x_irqchip1 = { - .name = "IOP33x-1", - .ack = iop33x_irq_mask1, - .mask = iop33x_irq_mask1, - .unmask = iop33x_irq_unmask1, + .name = "IOP33x-1", + .irq_ack = iop33x_irq_mask1, + .irq_mask = iop33x_irq_mask1, + .irq_unmask = iop33x_irq_unmask1, }; struct irq_chip iop33x_irqchip2 = { - .name = "IOP33x-2", - .ack = iop33x_irq_mask2, - .mask = iop33x_irq_mask2, - .unmask = iop33x_irq_unmask2, + .name = "IOP33x-2", + .irq_ack = iop33x_irq_mask2, + .irq_mask = iop33x_irq_mask2, + .irq_unmask = iop33x_irq_unmask2, }; void __init iop33x_init_irq(void) diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c index e24e3d05397..5fc4e064b65 100644 --- a/arch/arm/mach-ixp2000/core.c +++ b/arch/arm/mach-ixp2000/core.c @@ -309,9 +309,9 @@ static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc) } } -static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type) +static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type) { - int line = irq - IRQ_IXP2000_GPIO0; + int line = d->irq - IRQ_IXP2000_GPIO0; /* * First, configure this GPIO line as an input. @@ -342,8 +342,10 @@ static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type) return 0; } -static void ixp2000_GPIO_irq_mask_ack(unsigned int irq) +static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d) { + unsigned int irq = d->irq; + ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0))); ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0))); @@ -351,38 +353,42 @@ static void ixp2000_GPIO_irq_mask_ack(unsigned int irq) ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0))); } -static void ixp2000_GPIO_irq_mask(unsigned int irq) +static void ixp2000_GPIO_irq_mask(struct irq_data *d) { + unsigned int irq = d->irq; + ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0))); } -static void ixp2000_GPIO_irq_unmask(unsigned int irq) +static void ixp2000_GPIO_irq_unmask(struct irq_data *d) { + unsigned int irq = d->irq; + ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0))); } static struct irq_chip ixp2000_GPIO_irq_chip = { - .ack = ixp2000_GPIO_irq_mask_ack, - .mask = ixp2000_GPIO_irq_mask, - .unmask = ixp2000_GPIO_irq_unmask, - .set_type = ixp2000_GPIO_irq_type, + .irq_ack = ixp2000_GPIO_irq_mask_ack, + .irq_mask = ixp2000_GPIO_irq_mask, + .irq_unmask = ixp2000_GPIO_irq_unmask, + .irq_set_type = ixp2000_GPIO_irq_type, }; -static void ixp2000_pci_irq_mask(unsigned int irq) +static void ixp2000_pci_irq_mask(struct irq_data *d) { unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE; - if (irq == IRQ_IXP2000_PCIA) + if (d->irq == IRQ_IXP2000_PCIA) ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26))); - else if (irq == IRQ_IXP2000_PCIB) + else if (d->irq == IRQ_IXP2000_PCIB) ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27))); } -static void ixp2000_pci_irq_unmask(unsigned int irq) +static void ixp2000_pci_irq_unmask(struct irq_data *d) { unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE; - if (irq == IRQ_IXP2000_PCIA) + if (d->irq == IRQ_IXP2000_PCIA) ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26))); - else if (irq == IRQ_IXP2000_PCIB) + else if (d->irq == IRQ_IXP2000_PCIB) ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27))); } @@ -401,44 +407,44 @@ static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc) } } -static void ixp2000_err_irq_mask(unsigned int irq) +static void ixp2000_err_irq_mask(struct irq_data *d) { ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR, - (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))); + (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR))); } -static void ixp2000_err_irq_unmask(unsigned int irq) +static void ixp2000_err_irq_unmask(struct irq_data *d) { ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET, - (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))); + (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR))); } static struct irq_chip ixp2000_err_irq_chip = { - .ack = ixp2000_err_irq_mask, - .mask = ixp2000_err_irq_mask, - .unmask = ixp2000_err_irq_unmask + .irq_ack = ixp2000_err_irq_mask, + .irq_mask = ixp2000_err_irq_mask, + .irq_unmask = ixp2000_err_irq_unmask }; static struct irq_chip ixp2000_pci_irq_chip = { - .ack = ixp2000_pci_irq_mask, - .mask = ixp2000_pci_irq_mask, - .unmask = ixp2000_pci_irq_unmask + .irq_ack = ixp2000_pci_irq_mask, + .irq_mask = ixp2000_pci_irq_mask, + .irq_unmask = ixp2000_pci_irq_unmask }; -static void ixp2000_irq_mask(unsigned int irq) +static void ixp2000_irq_mask(struct irq_data *d) { - ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq)); + ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq)); } -static void ixp2000_irq_unmask(unsigned int irq) +static void ixp2000_irq_unmask(struct irq_data *d) { - ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq)); + ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq)); } static struct irq_chip ixp2000_irq_chip = { - .ack = ixp2000_irq_mask, - .mask = ixp2000_irq_mask, - .unmask = ixp2000_irq_unmask + .irq_ack = ixp2000_irq_mask, + .irq_mask = ixp2000_irq_mask, + .irq_unmask = ixp2000_irq_unmask }; void __init ixp2000_init_irq(void) diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c index 91fffb9b208..7d90d3f13ee 100644 --- a/arch/arm/mach-ixp2000/ixdp2x00.c +++ b/arch/arm/mach-ixp2000/ixdp2x00.c @@ -63,7 +63,7 @@ static struct slowport_cfg slowport_cpld_cfg = { }; #endif -static void ixdp2x00_irq_mask(unsigned int irq) +static void ixdp2x00_irq_mask(struct irq_data *d) { unsigned long dummy; static struct slowport_cfg old_cfg; @@ -78,7 +78,7 @@ static void ixdp2x00_irq_mask(unsigned int irq) #endif dummy = *board_irq_mask; - dummy |= IXP2000_BOARD_IRQ_MASK(irq); + dummy |= IXP2000_BOARD_IRQ_MASK(d->irq); ixp2000_reg_wrb(board_irq_mask, dummy); #ifdef CONFIG_ARCH_IXDP2400 @@ -87,7 +87,7 @@ static void ixdp2x00_irq_mask(unsigned int irq) #endif } -static void ixdp2x00_irq_unmask(unsigned int irq) +static void ixdp2x00_irq_unmask(struct irq_data *d) { unsigned long dummy; static struct slowport_cfg old_cfg; @@ -98,7 +98,7 @@ static void ixdp2x00_irq_unmask(unsigned int irq) #endif dummy = *board_irq_mask; - dummy &= ~IXP2000_BOARD_IRQ_MASK(irq); + dummy &= ~IXP2000_BOARD_IRQ_MASK(d->irq); ixp2000_reg_wrb(board_irq_mask, dummy); if (machine_is_ixdp2400()) @@ -111,7 +111,7 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc) static struct slowport_cfg old_cfg; int i; - desc->chip->mask(irq); + desc->irq_data.chip->irq_mask(&desc->irq_data); #ifdef CONFIG_ARCH_IXDP2400 if (machine_is_ixdp2400()) @@ -133,13 +133,13 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc) } } - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); } static struct irq_chip ixdp2x00_cpld_irq_chip = { - .ack = ixdp2x00_irq_mask, - .mask = ixdp2x00_irq_mask, - .unmask = ixdp2x00_irq_unmask + .irq_ack = ixdp2x00_irq_mask, + .irq_mask = ixdp2x00_irq_mask, + .irq_unmask = ixdp2x00_irq_unmask }; void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_of_irqs) diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c index 6c121bdbe31..34b1b2af37c 100644 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ b/arch/arm/mach-ixp2000/ixdp2x01.c @@ -48,16 +48,16 @@ /************************************************************************* * IXDP2x01 IRQ Handling *************************************************************************/ -static void ixdp2x01_irq_mask(unsigned int irq) +static void ixdp2x01_irq_mask(struct irq_data *d) { ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG, - IXP2000_BOARD_IRQ_MASK(irq)); + IXP2000_BOARD_IRQ_MASK(d->irq)); } -static void ixdp2x01_irq_unmask(unsigned int irq) +static void ixdp2x01_irq_unmask(struct irq_data *d) { ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG, - IXP2000_BOARD_IRQ_MASK(irq)); + IXP2000_BOARD_IRQ_MASK(d->irq)); } static u32 valid_irq_mask; @@ -67,7 +67,7 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc) u32 ex_interrupt; int i; - desc->chip->mask(irq); + desc->irq_data.chip->irq_mask(&desc->irq_data); ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask; @@ -83,13 +83,13 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc) } } - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); } static struct irq_chip ixdp2x01_irq_chip = { - .mask = ixdp2x01_irq_mask, - .ack = ixdp2x01_irq_mask, - .unmask = ixdp2x01_irq_unmask + .irq_mask = ixdp2x01_irq_mask, + .irq_ack = ixdp2x01_irq_mask, + .irq_unmask = ixdp2x01_irq_unmask }; /* diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c index aa4c4420ff3..9c8a3390321 100644 --- a/arch/arm/mach-ixp23xx/core.c +++ b/arch/arm/mach-ixp23xx/core.c @@ -111,9 +111,9 @@ enum ixp23xx_irq_type { static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type); -static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type) +static int ixp23xx_irq_set_type(struct irq_data *d, unsigned int type) { - int line = irq - IRQ_IXP23XX_GPIO6 + 6; + int line = d->irq - IRQ_IXP23XX_GPIO6 + 6; u32 int_style; enum ixp23xx_irq_type irq_type; volatile u32 *int_reg; @@ -149,7 +149,7 @@ static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type) return -EINVAL; } - ixp23xx_config_irq(irq, irq_type); + ixp23xx_config_irq(d->irq, irq_type); if (line >= 8) { /* pins 8-15 */ line -= 8; @@ -173,9 +173,10 @@ static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type) return 0; } -static void ixp23xx_irq_mask(unsigned int irq) +static void ixp23xx_irq_mask(struct irq_data *d) { volatile unsigned long *intr_reg; + unsigned int irq = d->irq; if (irq >= 56) irq += 8; @@ -184,9 +185,9 @@ static void ixp23xx_irq_mask(unsigned int irq) *intr_reg &= ~(1 << (irq % 32)); } -static void ixp23xx_irq_ack(unsigned int irq) +static void ixp23xx_irq_ack(struct irq_data *d) { - int line = irq - IRQ_IXP23XX_GPIO6 + 6; + int line = d->irq - IRQ_IXP23XX_GPIO6 + 6; if ((line < 6) || (line > 15)) return; @@ -198,11 +199,12 @@ static void ixp23xx_irq_ack(unsigned int irq) * Level triggered interrupts on GPIO lines can only be cleared when the * interrupt condition disappears. */ -static void ixp23xx_irq_level_unmask(unsigned int irq) +static void ixp23xx_irq_level_unmask(struct irq_data *d) { volatile unsigned long *intr_reg; + unsigned int irq = d->irq; - ixp23xx_irq_ack(irq); + ixp23xx_irq_ack(d); if (irq >= 56) irq += 8; @@ -211,9 +213,10 @@ static void ixp23xx_irq_level_unmask(unsigned int irq) *intr_reg |= (1 << (irq % 32)); } -static void ixp23xx_irq_edge_unmask(unsigned int irq) +static void ixp23xx_irq_edge_unmask(struct irq_data *d) { volatile unsigned long *intr_reg; + unsigned int irq = d->irq; if (irq >= 56) irq += 8; @@ -223,26 +226,30 @@ static void ixp23xx_irq_edge_unmask(unsigned int irq) } static struct irq_chip ixp23xx_irq_level_chip = { - .ack = ixp23xx_irq_mask, - .mask = ixp23xx_irq_mask, - .unmask = ixp23xx_irq_level_unmask, - .set_type = ixp23xx_irq_set_type + .irq_ack = ixp23xx_irq_mask, + .irq_mask = ixp23xx_irq_mask, + .irq_unmask = ixp23xx_irq_level_unmask, + .irq_set_type = ixp23xx_irq_set_type }; static struct irq_chip ixp23xx_irq_edge_chip = { - .ack = ixp23xx_irq_ack, - .mask = ixp23xx_irq_mask, - .unmask = ixp23xx_irq_edge_unmask, - .set_type = ixp23xx_irq_set_type + .irq_ack = ixp23xx_irq_ack, + .irq_mask = ixp23xx_irq_mask, + .irq_unmask = ixp23xx_irq_edge_unmask, + .irq_set_type = ixp23xx_irq_set_type }; -static void ixp23xx_pci_irq_mask(unsigned int irq) +static void ixp23xx_pci_irq_mask(struct irq_data *d) { + unsigned int irq = d->irq; + *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq)); } -static void ixp23xx_pci_irq_unmask(unsigned int irq) +static void ixp23xx_pci_irq_unmask(struct irq_data *d) { + unsigned int irq = d->irq; + *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq)); } @@ -256,7 +263,7 @@ static void pci_handler(unsigned int irq, struct irq_desc *desc) pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS; - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); /* See which PCI_INTA, or PCI_INTB interrupted */ if (pci_interrupt & (1 << 26)) { @@ -269,13 +276,13 @@ static void pci_handler(unsigned int irq, struct irq_desc *desc) generic_handle_irq(irqno); - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); } static struct irq_chip ixp23xx_pci_irq_chip = { - .ack = ixp23xx_pci_irq_mask, - .mask = ixp23xx_pci_irq_mask, - .unmask = ixp23xx_pci_irq_unmask + .irq_ack = ixp23xx_pci_irq_mask, + .irq_mask = ixp23xx_pci_irq_mask, + .irq_unmask = ixp23xx_pci_irq_unmask }; static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type) diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c index 664e39c2a90..181116aa659 100644 --- a/arch/arm/mach-ixp23xx/ixdp2351.c +++ b/arch/arm/mach-ixp23xx/ixdp2351.c @@ -48,14 +48,14 @@ /* * IXDP2351 Interrupt Handling */ -static void ixdp2351_inta_mask(unsigned int irq) +static void ixdp2351_inta_mask(struct irq_data *d) { - *IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(irq); + *IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(d->irq); } -static void ixdp2351_inta_unmask(unsigned int irq) +static void ixdp2351_inta_unmask(struct irq_data *d) { - *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq); + *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(d->irq); } static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc) @@ -64,7 +64,7 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc) *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID; int i; - desc->chip->mask(irq); + desc->irq_data.chip->irq_mask(&desc->irq_data); for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) { if (ex_interrupt & (1 << i)) { @@ -74,23 +74,23 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc) } } - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); } static struct irq_chip ixdp2351_inta_chip = { - .ack = ixdp2351_inta_mask, - .mask = ixdp2351_inta_mask, - .unmask = ixdp2351_inta_unmask + .irq_ack = ixdp2351_inta_mask, + .irq_mask = ixdp2351_inta_mask, + .irq_unmask = ixdp2351_inta_unmask }; -static void ixdp2351_intb_mask(unsigned int irq) +static void ixdp2351_intb_mask(struct irq_data *d) { - *IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(irq); + *IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(d->irq); } -static void ixdp2351_intb_unmask(unsigned int irq) +static void ixdp2351_intb_unmask(struct irq_data *d) { - *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq); + *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(d->irq); } static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc) @@ -99,7 +99,7 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc) *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID; int i; - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) { if (ex_interrupt & (1 << i)) { @@ -109,13 +109,13 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc) } } - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); } static struct irq_chip ixdp2351_intb_chip = { - .ack = ixdp2351_intb_mask, - .mask = ixdp2351_intb_mask, - .unmask = ixdp2351_intb_unmask + .irq_ack = ixdp2351_intb_mask, + .irq_mask = ixdp2351_intb_mask, + .irq_unmask = ixdp2351_intb_unmask }; void __init ixdp2351_init_irq(void) diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 4dbfcbb9163..4dc68d6bb6b 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -128,9 +128,9 @@ int irq_to_gpio(unsigned int irq) } EXPORT_SYMBOL(irq_to_gpio); -static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type) +static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type) { - int line = irq2gpio[irq]; + int line = irq2gpio[d->irq]; u32 int_style; enum ixp4xx_irq_type irq_type; volatile u32 *int_reg; @@ -167,9 +167,9 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type) } if (irq_type == IXP4XX_IRQ_EDGE) - ixp4xx_irq_edge |= (1 << irq); + ixp4xx_irq_edge |= (1 << d->irq); else - ixp4xx_irq_edge &= ~(1 << irq); + ixp4xx_irq_edge &= ~(1 << d->irq); if (line >= 8) { /* pins 8-15 */ line -= 8; @@ -188,22 +188,22 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type) *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); /* Configure the line as an input */ - gpio_line_config(irq2gpio[irq], IXP4XX_GPIO_IN); + gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN); return 0; } -static void ixp4xx_irq_mask(unsigned int irq) +static void ixp4xx_irq_mask(struct irq_data *d) { - if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32) - *IXP4XX_ICMR2 &= ~(1 << (irq - 32)); + if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32) + *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32)); else - *IXP4XX_ICMR &= ~(1 << irq); + *IXP4XX_ICMR &= ~(1 << d->irq); } -static void ixp4xx_irq_ack(unsigned int irq) +static void ixp4xx_irq_ack(struct irq_data *d) { - int line = (irq < 32) ? irq2gpio[irq] : -1; + int line = (d->irq < 32) ? irq2gpio[d->irq] : -1; if (line >= 0) *IXP4XX_GPIO_GPISR = (1 << line); @@ -213,23 +213,23 @@ static void ixp4xx_irq_ack(unsigned int irq) * Level triggered interrupts on GPIO lines can only be cleared when the * interrupt condition disappears. */ -static void ixp4xx_irq_unmask(unsigned int irq) +static void ixp4xx_irq_unmask(struct irq_data *d) { - if (!(ixp4xx_irq_edge & (1 << irq))) - ixp4xx_irq_ack(irq); + if (!(ixp4xx_irq_edge & (1 << d->irq))) + ixp4xx_irq_ack(d); - if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32) - *IXP4XX_ICMR2 |= (1 << (irq - 32)); + if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32) + *IXP4XX_ICMR2 |= (1 << (d->irq - 32)); else - *IXP4XX_ICMR |= (1 << irq); + *IXP4XX_ICMR |= (1 << d->irq); } static struct irq_chip ixp4xx_irq_chip = { .name = "IXP4xx", - .ack = ixp4xx_irq_ack, - .mask = ixp4xx_irq_mask, - .unmask = ixp4xx_irq_unmask, - .set_type = ixp4xx_set_irq_type, + .irq_ack = ixp4xx_irq_ack, + .irq_mask = ixp4xx_irq_mask, + .irq_unmask = ixp4xx_irq_unmask, + .irq_set_type = ixp4xx_set_irq_type, }; void __init ixp4xx_init_irq(void) diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c index e375c1d53f8..7998ccaa633 100644 --- a/arch/arm/mach-ks8695/irq.c +++ b/arch/arm/mach-ks8695/irq.c @@ -34,29 +34,29 @@ #include <mach/regs-irq.h> #include <mach/regs-gpio.h> -static void ks8695_irq_mask(unsigned int irqno) +static void ks8695_irq_mask(struct irq_data *d) { unsigned long inten; inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN); - inten &= ~(1 << irqno); + inten &= ~(1 << d->irq); __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN); } -static void ks8695_irq_unmask(unsigned int irqno) +static void ks8695_irq_unmask(struct irq_data *d) { unsigned long inten; inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN); - inten |= (1 << irqno); + inten |= (1 << d->irq); __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN); } -static void ks8695_irq_ack(unsigned int irqno) +static void ks8695_irq_ack(struct irq_data *d) { - __raw_writel((1 << irqno), KS8695_IRQ_VA + KS8695_INTST); + __raw_writel((1 << d->irq), KS8695_IRQ_VA + KS8695_INTST); } @@ -64,7 +64,7 @@ static struct irq_chip ks8695_irq_level_chip; static struct irq_chip ks8695_irq_edge_chip; -static int ks8695_irq_set_type(unsigned int irqno, unsigned int type) +static int ks8695_irq_set_type(struct irq_data *d, unsigned int type) { unsigned long ctrl, mode; unsigned short level_triggered = 0; @@ -93,7 +93,7 @@ static int ks8695_irq_set_type(unsigned int irqno, unsigned int type) return -EINVAL; } - switch (irqno) { + switch (d->irq) { case KS8695_IRQ_EXTERN0: ctrl &= ~IOPC_IOEINT0TM; ctrl |= IOPC_IOEINT0_MODE(mode); @@ -115,12 +115,12 @@ static int ks8695_irq_set_type(unsigned int irqno, unsigned int type) } if (level_triggered) { - set_irq_chip(irqno, &ks8695_irq_level_chip); - set_irq_handler(irqno, handle_level_irq); + set_irq_chip(d->irq, &ks8695_irq_level_chip); + set_irq_handler(d->irq, handle_level_irq); } else { - set_irq_chip(irqno, &ks8695_irq_edge_chip); - set_irq_handler(irqno, handle_edge_irq); + set_irq_chip(d->irq, &ks8695_irq_edge_chip); + set_irq_handler(d->irq, handle_edge_irq); } __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); @@ -128,17 +128,17 @@ static int ks8695_irq_set_type(unsigned int irqno, unsigned int type) } static struct irq_chip ks8695_irq_level_chip = { - .ack = ks8695_irq_mask, - .mask = ks8695_irq_mask, - .unmask = ks8695_irq_unmask, - .set_type = ks8695_irq_set_type, + .irq_ack = ks8695_irq_mask, + .irq_mask = ks8695_irq_mask, + .irq_unmask = ks8695_irq_unmask, + .irq_set_type = ks8695_irq_set_type, }; static struct irq_chip ks8695_irq_edge_chip = { - .ack = ks8695_irq_ack, - .mask = ks8695_irq_mask, - .unmask = ks8695_irq_unmask, - .set_type = ks8695_irq_set_type, + .irq_ack = ks8695_irq_ack, + .irq_mask = ks8695_irq_mask, + .irq_unmask = ks8695_irq_unmask, + .irq_set_type = ks8695_irq_set_type, }; void __init ks8695_init_irq(void) @@ -164,7 +164,8 @@ void __init ks8695_init_irq(void) /* Edge-triggered interrupts */ default: - ks8695_irq_ack(irq); /* clear pending bit */ + /* clear pending bit */ + ks8695_irq_ack(irq_get_irq_data(irq)); set_irq_chip(irq, &ks8695_irq_edge_chip); set_irq_handler(irq, handle_edge_irq); } diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c index 9088c16662e..71129c33c7d 100644 --- a/arch/arm/mach-lh7a40x/arch-kev7a400.c +++ b/arch/arm/mach-lh7a40x/arch-kev7a400.c @@ -46,28 +46,28 @@ void __init kev7a400_map_io(void) static u16 CPLD_IRQ_mask; /* Mask for CPLD IRQs, 1 == unmasked */ -static void kev7a400_ack_cpld_irq (u32 irq) +static void kev7a400_ack_cpld_irq(struct irq_data *d) { - CPLD_CL_INT = 1 << (irq - IRQ_KEV7A400_CPLD); + CPLD_CL_INT = 1 << (d->irq - IRQ_KEV7A400_CPLD); } -static void kev7a400_mask_cpld_irq (u32 irq) +static void kev7a400_mask_cpld_irq(struct irq_data *d) { - CPLD_IRQ_mask &= ~(1 << (irq - IRQ_KEV7A400_CPLD)); + CPLD_IRQ_mask &= ~(1 << (d->irq - IRQ_KEV7A400_CPLD)); CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask; } -static void kev7a400_unmask_cpld_irq (u32 irq) +static void kev7a400_unmask_cpld_irq(struct irq_data *d) { - CPLD_IRQ_mask |= 1 << (irq - IRQ_KEV7A400_CPLD); + CPLD_IRQ_mask |= 1 << (d->irq - IRQ_KEV7A400_CPLD); CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask; } static struct irq_chip kev7a400_cpld_chip = { - .name = "CPLD", - .ack = kev7a400_ack_cpld_irq, - .mask = kev7a400_mask_cpld_irq, - .unmask = kev7a400_unmask_cpld_irq, + .name = "CPLD", + .irq_ack = kev7a400_ack_cpld_irq, + .irq_mask = kev7a400_mask_cpld_irq, + .irq_unmask = kev7a400_unmask_cpld_irq, }; diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c index 7315a569aea..e735546181a 100644 --- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c +++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c @@ -159,7 +159,7 @@ static void __init lpd7a40x_init (void) #endif } -static void lh7a40x_ack_cpld_irq (u32 irq) +static void lh7a40x_ack_cpld_irq(struct irq_data *d) { /* CPLD doesn't have ack capability, but some devices may */ @@ -167,14 +167,14 @@ static void lh7a40x_ack_cpld_irq (u32 irq) /* The touch control *must* mask the interrupt because the * interrupt bit is read by the driver to determine if the pen * is still down. */ - if (irq == IRQ_TOUCH) + if (d->irq == IRQ_TOUCH) CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH; #endif } -static void lh7a40x_mask_cpld_irq (u32 irq) +static void lh7a40x_mask_cpld_irq(struct irq_data *d) { - switch (irq) { + switch (d->irq) { case IRQ_LPD7A40X_ETH_INT: CPLD_INTERRUPTS |= CPLD_INTMASK_ETHERNET; break; @@ -186,9 +186,9 @@ static void lh7a40x_mask_cpld_irq (u32 irq) } } -static void lh7a40x_unmask_cpld_irq (u32 irq) +static void lh7a40x_unmask_cpld_irq(struct irq_data *d) { - switch (irq) { + switch (d->irq) { case IRQ_LPD7A40X_ETH_INT: CPLD_INTERRUPTS &= ~CPLD_INTMASK_ETHERNET; break; @@ -201,17 +201,17 @@ static void lh7a40x_unmask_cpld_irq (u32 irq) } static struct irq_chip lpd7a40x_cpld_chip = { - .name = "CPLD", - .ack = lh7a40x_ack_cpld_irq, - .mask = lh7a40x_mask_cpld_irq, - .unmask = lh7a40x_unmask_cpld_irq, + .name = "CPLD", + .irq_ack = lh7a40x_ack_cpld_irq, + .irq_mask = lh7a40x_mask_cpld_irq, + .irq_unmask = lh7a40x_unmask_cpld_irq, }; static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc) { unsigned int mask = CPLD_INTERRUPTS; - desc->chip->ack (irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); if ((mask & (1<<0)) == 0) /* WLAN */ generic_handle_irq(IRQ_LPD7A40X_ETH_INT); @@ -221,7 +221,8 @@ static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc) generic_handle_irq(IRQ_TOUCH); #endif - desc->chip->unmask (irq); /* Level-triggered need this */ + /* Level-triggered need this */ + desc->irq_data.chip->irq_unmask(&desc->irq_data); } diff --git a/arch/arm/mach-lh7a40x/irq-lh7a400.c b/arch/arm/mach-lh7a40x/irq-lh7a400.c index 1ad3afcf6b3..f2e7e655ca3 100644 --- a/arch/arm/mach-lh7a40x/irq-lh7a400.c +++ b/arch/arm/mach-lh7a40x/irq-lh7a400.c @@ -21,34 +21,34 @@ /* CPU IRQ handling */ -static void lh7a400_mask_irq (u32 irq) +static void lh7a400_mask_irq(struct irq_data *d) { - INTC_INTENC = (1 << irq); + INTC_INTENC = (1 << d->irq); } -static void lh7a400_unmask_irq (u32 irq) +static void lh7a400_unmask_irq(struct irq_data *d) { - INTC_INTENS = (1 << irq); + INTC_INTENS = (1 << d->irq); } -static void lh7a400_ack_gpio_irq (u32 irq) +static void lh7a400_ack_gpio_irq(struct irq_data *d) { - GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq)); - INTC_INTENC = (1 << irq); + GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq)); + INTC_INTENC = (1 << d->irq); } static struct irq_chip lh7a400_internal_chip = { - .name = "MPU", - .ack = lh7a400_mask_irq, /* Level triggering -> mask is ack */ - .mask = lh7a400_mask_irq, - .unmask = lh7a400_unmask_irq, + .name = "MPU", + .irq_ack = lh7a400_mask_irq, /* Level triggering -> mask is ack */ + .irq_mask = lh7a400_mask_irq, + .irq_unmask = lh7a400_unmask_irq, }; static struct irq_chip lh7a400_gpio_chip = { - .name = "GPIO", - .ack = lh7a400_ack_gpio_irq, - .mask = lh7a400_mask_irq, - .unmask = lh7a400_unmask_irq, + .name = "GPIO", + .irq_ack = lh7a400_ack_gpio_irq, + .irq_mask = lh7a400_mask_irq, + .irq_unmask = lh7a400_unmask_irq, }; diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c index 12b045b688c..14b17338957 100644 --- a/arch/arm/mach-lh7a40x/irq-lh7a404.c +++ b/arch/arm/mach-lh7a40x/irq-lh7a404.c @@ -43,64 +43,64 @@ static unsigned char irq_pri_vic2[] = { /* CPU IRQ handling */ -static void lh7a404_vic1_mask_irq (u32 irq) +static void lh7a404_vic1_mask_irq(struct irq_data *d) { - VIC1_INTENCLR = (1 << irq); + VIC1_INTENCLR = (1 << d->irq); } -static void lh7a404_vic1_unmask_irq (u32 irq) +static void lh7a404_vic1_unmask_irq(struct irq_data *d) { - VIC1_INTEN = (1 << irq); + VIC1_INTEN = (1 << d->irq); } -static void lh7a404_vic2_mask_irq (u32 irq) +static void lh7a404_vic2_mask_irq(struct irq_data *d) { - VIC2_INTENCLR = (1 << (irq - 32)); + VIC2_INTENCLR = (1 << (d->irq - 32)); } -static void lh7a404_vic2_unmask_irq (u32 irq) +static void lh7a404_vic2_unmask_irq(struct irq_data *d) { - VIC2_INTEN = (1 << (irq - 32)); + VIC2_INTEN = (1 << (d->irq - 32)); } -static void lh7a404_vic1_ack_gpio_irq (u32 irq) +static void lh7a404_vic1_ack_gpio_irq(struct irq_data *d) { - GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq)); - VIC1_INTENCLR = (1 << irq); + GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq)); + VIC1_INTENCLR = (1 << d->irq); } -static void lh7a404_vic2_ack_gpio_irq (u32 irq) +static void lh7a404_vic2_ack_gpio_irq(struct irq_data *d) { - GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq)); - VIC2_INTENCLR = (1 << irq); + GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq)); + VIC2_INTENCLR = (1 << d->irq); } static struct irq_chip lh7a404_vic1_chip = { - .name = "VIC1", - .ack = lh7a404_vic1_mask_irq, /* Because level-triggered */ - .mask = lh7a404_vic1_mask_irq, - .unmask = lh7a404_vic1_unmask_irq, + .name = "VIC1", + .irq_ack = lh7a404_vic1_mask_irq, /* Because level-triggered */ + .irq_mask = lh7a404_vic1_mask_irq, + .irq_unmask = lh7a404_vic1_unmask_irq, }; static struct irq_chip lh7a404_vic2_chip = { - .name = "VIC2", - .ack = lh7a404_vic2_mask_irq, /* Because level-triggered */ - .mask = lh7a404_vic2_mask_irq, - .unmask = lh7a404_vic2_unmask_irq, + .name = "VIC2", + .irq_ack = lh7a404_vic2_mask_irq, /* Because level-triggered */ + .irq_mask = lh7a404_vic2_mask_irq, + .irq_unmask = lh7a404_vic2_unmask_irq, }; static struct irq_chip lh7a404_gpio_vic1_chip = { - .name = "GPIO-VIC1", - .ack = lh7a404_vic1_ack_gpio_irq, - .mask = lh7a404_vic1_mask_irq, - .unmask = lh7a404_vic1_unmask_irq, + .name = "GPIO-VIC1", + .irq_ack = lh7a404_vic1_ack_gpio_irq, + .irq_mask = lh7a404_vic1_mask_irq, + .irq_unmask = lh7a404_vic1_unmask_irq, }; static struct irq_chip lh7a404_gpio_vic2_chip = { - .name = "GPIO-VIC2", - .ack = lh7a404_vic2_ack_gpio_irq, - .mask = lh7a404_vic2_mask_irq, - .unmask = lh7a404_vic2_unmask_irq, + .name = "GPIO-VIC2", + .irq_ack = lh7a404_vic2_ack_gpio_irq, + .irq_mask = lh7a404_vic2_mask_irq, + .irq_unmask = lh7a404_vic2_unmask_irq, }; /* IRQ initialization */ diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c index fd033bb4342..1bfdcddcb93 100644 --- a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c +++ b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c @@ -20,14 +20,14 @@ #include "common.h" -static void lh7a40x_ack_cpld_irq (u32 irq) +static void lh7a40x_ack_cpld_irq(struct irq_data *d) { /* CPLD doesn't have ack capability */ } -static void lh7a40x_mask_cpld_irq (u32 irq) +static void lh7a40x_mask_cpld_irq(struct irq_data *d) { - switch (irq) { + switch (d->irq) { case IRQ_LPD7A40X_ETH_INT: CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x4; break; @@ -37,9 +37,9 @@ static void lh7a40x_mask_cpld_irq (u32 irq) } } -static void lh7a40x_unmask_cpld_irq (u32 irq) +static void lh7a40x_unmask_cpld_irq(struct irq_data *d) { - switch (irq) { + switch (d->irq) { case IRQ_LPD7A40X_ETH_INT: CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x4; break; @@ -50,17 +50,17 @@ static void lh7a40x_unmask_cpld_irq (u32 irq) } static struct irq_chip lh7a40x_cpld_chip = { - .name = "CPLD", - .ack = lh7a40x_ack_cpld_irq, - .mask = lh7a40x_mask_cpld_irq, - .unmask = lh7a40x_unmask_cpld_irq, + .name = "CPLD", + .irq_ack = lh7a40x_ack_cpld_irq, + .irq_mask = lh7a40x_mask_cpld_irq, + .irq_unmask = lh7a40x_unmask_cpld_irq, }; static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc) { unsigned int mask = CPLD_INTERRUPTS; - desc->chip->ack (irq); + desc->irq_data.chip->ack (irq); if ((mask & 0x1) == 0) /* WLAN */ generic_handle_irq(IRQ_LPD7A40X_ETH_INT); @@ -68,7 +68,7 @@ static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc) if ((mask & 0x2) == 0) /* Touch */ generic_handle_irq(IRQ_LPD7A400_TS); - desc->chip->unmask (irq); /* Level-triggered need this */ + desc->irq_data.chip->unmask (irq); /* Level-triggered need this */ } diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index bd0df26c415..316ecbf6c58 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c @@ -191,38 +191,38 @@ static void get_controller(unsigned int irq, unsigned int *base, } } -static void lpc32xx_mask_irq(unsigned int irq) +static void lpc32xx_mask_irq(struct irq_data *d) { unsigned int reg, ctrl, mask; - get_controller(irq, &ctrl, &mask); + get_controller(d->irq, &ctrl, &mask); reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask; __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); } -static void lpc32xx_unmask_irq(unsigned int irq) +static void lpc32xx_unmask_irq(struct irq_data *d) { unsigned int reg, ctrl, mask; - get_controller(irq, &ctrl, &mask); + get_controller(d->irq, &ctrl, &mask); reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask; __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); } -static void lpc32xx_ack_irq(unsigned int irq) +static void lpc32xx_ack_irq(struct irq_data *d) { unsigned int ctrl, mask; - get_controller(irq, &ctrl, &mask); + get_controller(d->irq, &ctrl, &mask); __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); /* Also need to clear pending wake event */ - if (lpc32xx_events[irq].mask != 0) - __raw_writel(lpc32xx_events[irq].mask, - lpc32xx_events[irq].event_group->rawstat_reg); + if (lpc32xx_events[d->irq].mask != 0) + __raw_writel(lpc32xx_events[d->irq].mask, + lpc32xx_events[d->irq].event_group->rawstat_reg); } static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level, @@ -261,27 +261,27 @@ static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level, } } -static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type) +static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) { switch (type) { case IRQ_TYPE_EDGE_RISING: /* Rising edge sensitive */ - __lpc32xx_set_irq_type(irq, 1, 1); + __lpc32xx_set_irq_type(d->irq, 1, 1); break; case IRQ_TYPE_EDGE_FALLING: /* Falling edge sensitive */ - __lpc32xx_set_irq_type(irq, 0, 1); + __lpc32xx_set_irq_type(d->irq, 0, 1); break; case IRQ_TYPE_LEVEL_LOW: /* Low level sensitive */ - __lpc32xx_set_irq_type(irq, 0, 0); + __lpc32xx_set_irq_type(d->irq, 0, 0); break; case IRQ_TYPE_LEVEL_HIGH: /* High level sensitive */ - __lpc32xx_set_irq_type(irq, 1, 0); + __lpc32xx_set_irq_type(d->irq, 1, 0); break; /* Other modes are not supported */ @@ -290,33 +290,33 @@ static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type) } /* Ok to use the level handler for all types */ - set_irq_handler(irq, handle_level_irq); + set_irq_handler(d->irq, handle_level_irq); return 0; } -static int lpc32xx_irq_wake(unsigned int irqno, unsigned int state) +static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state) { unsigned long eventreg; - if (lpc32xx_events[irqno].mask != 0) { - eventreg = __raw_readl(lpc32xx_events[irqno]. + if (lpc32xx_events[d->irq].mask != 0) { + eventreg = __raw_readl(lpc32xx_events[d->irq]. event_group->enab_reg); if (state) - eventreg |= lpc32xx_events[irqno].mask; + eventreg |= lpc32xx_events[d->irq].mask; else - eventreg &= ~lpc32xx_events[irqno].mask; + eventreg &= ~lpc32xx_events[d->irq].mask; __raw_writel(eventreg, - lpc32xx_events[irqno].event_group->enab_reg); + lpc32xx_events[d->irq].event_group->enab_reg); return 0; } /* Clear event */ - __raw_writel(lpc32xx_events[irqno].mask, - lpc32xx_events[irqno].event_group->rawstat_reg); + __raw_writel(lpc32xx_events[d->irq].mask, + lpc32xx_events[d->irq].event_group->rawstat_reg); return -ENODEV; } @@ -336,11 +336,11 @@ static void __init lpc32xx_set_default_mappings(unsigned int apr, } static struct irq_chip lpc32xx_irq_chip = { - .ack = lpc32xx_ack_irq, - .mask = lpc32xx_mask_irq, - .unmask = lpc32xx_unmask_irq, - .set_type = lpc32xx_set_irq_type, - .set_wake = lpc32xx_irq_wake + .irq_ack = lpc32xx_ack_irq, + .irq_mask = lpc32xx_mask_irq, + .irq_unmask = lpc32xx_unmask_irq, + .irq_set_type = lpc32xx_set_irq_type, + .irq_set_wake = lpc32xx_irq_wake }; static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc) diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h index 117e3036608..4ad38629c3f 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h +++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h @@ -6,7 +6,7 @@ #define MFP_DRIVE_VERY_SLOW (0x0 << 13) #define MFP_DRIVE_SLOW (0x2 << 13) #define MFP_DRIVE_MEDIUM (0x4 << 13) -#define MFP_DRIVE_FAST (0x8 << 13) +#define MFP_DRIVE_FAST (0x6 << 13) /* GPIO */ #define GPIO0_GPIO MFP_CFG(GPIO0, AF0) diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h index 7e8a80f25dd..fbd7ee8e489 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h @@ -6,7 +6,7 @@ #define MFP_DRIVE_VERY_SLOW (0x0 << 13) #define MFP_DRIVE_SLOW (0x2 << 13) #define MFP_DRIVE_MEDIUM (0x4 << 13) -#define MFP_DRIVE_FAST (0x8 << 13) +#define MFP_DRIVE_FAST (0x6 << 13) /* UART2 */ #define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6) diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c index 01342be91c3..fa037038e7b 100644 --- a/arch/arm/mach-mmp/irq-mmp2.c +++ b/arch/arm/mach-mmp/irq-mmp2.c @@ -20,48 +20,48 @@ #include "common.h" -static void icu_mask_irq(unsigned int irq) +static void icu_mask_irq(struct irq_data *d) { - uint32_t r = __raw_readl(ICU_INT_CONF(irq)); + uint32_t r = __raw_readl(ICU_INT_CONF(d->irq)); r &= ~ICU_INT_ROUTE_PJ4_IRQ; - __raw_writel(r, ICU_INT_CONF(irq)); + __raw_writel(r, ICU_INT_CONF(d->irq)); } -static void icu_unmask_irq(unsigned int irq) +static void icu_unmask_irq(struct irq_data *d) { - uint32_t r = __raw_readl(ICU_INT_CONF(irq)); + uint32_t r = __raw_readl(ICU_INT_CONF(d->irq)); r |= ICU_INT_ROUTE_PJ4_IRQ; - __raw_writel(r, ICU_INT_CONF(irq)); + __raw_writel(r, ICU_INT_CONF(d->irq)); } static struct irq_chip icu_irq_chip = { .name = "icu_irq", - .mask = icu_mask_irq, - .mask_ack = icu_mask_irq, - .unmask = icu_unmask_irq, + .irq_mask = icu_mask_irq, + .irq_mask_ack = icu_mask_irq, + .irq_unmask = icu_unmask_irq, }; -static void pmic_irq_ack(unsigned int irq) +static void pmic_irq_ack(struct irq_data *d) { - if (irq == IRQ_MMP2_PMIC) + if (d->irq == IRQ_MMP2_PMIC) mmp2_clear_pmic_int(); } #define SECOND_IRQ_MASK(_name_, irq_base, prefix) \ -static void _name_##_mask_irq(unsigned int irq) \ +static void _name_##_mask_irq(struct irq_data *d) \ { \ uint32_t r; \ - r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base)); \ + r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base)); \ __raw_writel(r, prefix##_MASK); \ } #define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ -static void _name_##_unmask_irq(unsigned int irq) \ +static void _name_##_unmask_irq(struct irq_data *d) \ { \ uint32_t r; \ - r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base)); \ + r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base)); \ __raw_writel(r, prefix##_MASK); \ } @@ -88,8 +88,8 @@ SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ static struct irq_chip _name_##_irq_chip = { \ .name = #_name_, \ - .mask = _name_##_mask_irq, \ - .unmask = _name_##_unmask_irq, \ + .irq_mask = _name_##_mask_irq, \ + .irq_unmask = _name_##_unmask_irq, \ } SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4); @@ -103,10 +103,12 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num) int irq; for (irq = start; num > 0; irq++, num--) { + struct irq_data *d = irq_get_irq_data(irq); + /* mask and clear the IRQ */ - chip->mask(irq); - if (chip->ack) - chip->ack(irq); + chip->irq_mask(d); + if (chip->irq_ack) + chip->irq_ack(d); set_irq_chip(irq, chip); set_irq_flags(irq, IRQF_VALID); @@ -119,7 +121,7 @@ void __init mmp2_init_icu(void) int irq; for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { - icu_mask_irq(irq); + icu_mask_irq(irq_get_irq_data(irq)); set_irq_chip(irq, &icu_irq_chip); set_irq_flags(irq, IRQF_VALID); @@ -139,7 +141,7 @@ void __init mmp2_init_icu(void) /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register * to be written to clear the interrupt */ - pmic_irq_chip.ack = pmic_irq_ack; + pmic_irq_chip.irq_ack = pmic_irq_ack; init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2); init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2); diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c index 52ff2f065eb..f86b450cb93 100644 --- a/arch/arm/mach-mmp/irq-pxa168.c +++ b/arch/arm/mach-mmp/irq-pxa168.c @@ -25,21 +25,21 @@ #define PRIORITY_DEFAULT 0x1 #define PRIORITY_NONE 0x0 /* means IRQ disabled */ -static void icu_mask_irq(unsigned int irq) +static void icu_mask_irq(struct irq_data *d) { - __raw_writel(PRIORITY_NONE, ICU_INT_CONF(irq)); + __raw_writel(PRIORITY_NONE, ICU_INT_CONF(d->irq)); } -static void icu_unmask_irq(unsigned int irq) +static void icu_unmask_irq(struct irq_data *d) { - __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(irq)); + __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(d->irq)); } static struct irq_chip icu_irq_chip = { - .name = "icu_irq", - .ack = icu_mask_irq, - .mask = icu_mask_irq, - .unmask = icu_unmask_irq, + .name = "icu_irq", + .irq_ack = icu_mask_irq, + .irq_mask = icu_mask_irq, + .irq_unmask = icu_unmask_irq, }; void __init icu_init_irq(void) @@ -47,7 +47,7 @@ void __init icu_init_irq(void) int irq; for (irq = 0; irq < 64; irq++) { - icu_mask_irq(irq); + icu_mask_irq(irq_get_irq_data(irq)); set_irq_chip(irq, &icu_irq_chip); set_irq_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 2e8391307f5..6dde8185205 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -43,7 +43,7 @@ static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156; * at run-time: they vary from board to board, and the true * configuration won't be known until boot. */ -static struct resource smc91x_resources[] __initdata = { +static struct resource smc91x_resources[] = { [0] = { .flags = IORESOURCE_MEM, }, @@ -52,7 +52,7 @@ static struct resource smc91x_resources[] __initdata = { }, }; -static struct platform_device smc91x_device __initdata = { +static struct platform_device smc91x_device = { .name = "smc91x", .id = 0, .num_resources = ARRAY_SIZE(smc91x_resources), diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c index f8c09ef6666..a604ec1e44b 100644 --- a/arch/arm/mach-msm/board-trout-gpio.c +++ b/arch/arm/mach-msm/board-trout-gpio.c @@ -113,52 +113,52 @@ static struct msm_gpio_chip msm_gpio_banks[] = { TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0), }; -static void trout_gpio_irq_ack(unsigned int irq) +static void trout_gpio_irq_ack(struct irq_data *d) { - int bank = TROUT_INT_TO_BANK(irq); - uint8_t mask = TROUT_INT_TO_MASK(irq); + int bank = TROUT_INT_TO_BANK(d->irq); + uint8_t mask = TROUT_INT_TO_MASK(d->irq); int reg = TROUT_BANK_TO_STAT_REG(bank); - /*printk(KERN_INFO "trout_gpio_irq_ack irq %d\n", irq);*/ + /*printk(KERN_INFO "trout_gpio_irq_ack irq %d\n", d->irq);*/ writeb(mask, TROUT_CPLD_BASE + reg); } -static void trout_gpio_irq_mask(unsigned int irq) +static void trout_gpio_irq_mask(struct irq_data *d) { unsigned long flags; uint8_t reg_val; - int bank = TROUT_INT_TO_BANK(irq); - uint8_t mask = TROUT_INT_TO_MASK(irq); + int bank = TROUT_INT_TO_BANK(d->irq); + uint8_t mask = TROUT_INT_TO_MASK(d->irq); int reg = TROUT_BANK_TO_MASK_REG(bank); local_irq_save(flags); reg_val = trout_int_mask[bank] |= mask; /*printk(KERN_INFO "trout_gpio_irq_mask irq %d => %d:%02x\n", - irq, bank, reg_val);*/ + d->irq, bank, reg_val);*/ writeb(reg_val, TROUT_CPLD_BASE + reg); local_irq_restore(flags); } -static void trout_gpio_irq_unmask(unsigned int irq) +static void trout_gpio_irq_unmask(struct irq_data *d) { unsigned long flags; uint8_t reg_val; - int bank = TROUT_INT_TO_BANK(irq); - uint8_t mask = TROUT_INT_TO_MASK(irq); + int bank = TROUT_INT_TO_BANK(d->irq); + uint8_t mask = TROUT_INT_TO_MASK(d->irq); int reg = TROUT_BANK_TO_MASK_REG(bank); local_irq_save(flags); reg_val = trout_int_mask[bank] &= ~mask; /*printk(KERN_INFO "trout_gpio_irq_unmask irq %d => %d:%02x\n", - irq, bank, reg_val);*/ + d->irq, bank, reg_val);*/ writeb(reg_val, TROUT_CPLD_BASE + reg); local_irq_restore(flags); } -int trout_gpio_irq_set_wake(unsigned int irq, unsigned int on) +int trout_gpio_irq_set_wake(struct irq_data *d, unsigned int on) { unsigned long flags; - int bank = TROUT_INT_TO_BANK(irq); - uint8_t mask = TROUT_INT_TO_MASK(irq); + int bank = TROUT_INT_TO_BANK(d->irq); + uint8_t mask = TROUT_INT_TO_MASK(d->irq); local_irq_save(flags); if(on) @@ -198,15 +198,15 @@ static void trout_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) } int_base += TROUT_INT_BANK0_COUNT; } - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); } static struct irq_chip trout_gpio_irq_chip = { - .name = "troutgpio", - .ack = trout_gpio_irq_ack, - .mask = trout_gpio_irq_mask, - .unmask = trout_gpio_irq_unmask, - .set_wake = trout_gpio_irq_set_wake, + .name = "troutgpio", + .irq_ack = trout_gpio_irq_ack, + .irq_mask = trout_gpio_irq_mask, + .irq_unmask = trout_gpio_irq_unmask, + .irq_set_wake = trout_gpio_irq_set_wake, }; /* diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c index 33051b509e8..176af9dcb8e 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/arch/arm/mach-msm/gpio.c @@ -225,21 +225,21 @@ struct msm_gpio_chip msm_gpio_chips[] = { #endif }; -static void msm_gpio_irq_ack(unsigned int irq) +static void msm_gpio_irq_ack(struct irq_data *d) { unsigned long irq_flags; - struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); + struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d); spin_lock_irqsave(&msm_chip->lock, irq_flags); msm_gpio_clear_detect_status(msm_chip, - irq - gpio_to_irq(msm_chip->chip.base)); + d->irq - gpio_to_irq(msm_chip->chip.base)); spin_unlock_irqrestore(&msm_chip->lock, irq_flags); } -static void msm_gpio_irq_mask(unsigned int irq) +static void msm_gpio_irq_mask(struct irq_data *d) { unsigned long irq_flags; - struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); - unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); + struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d); + unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); spin_lock_irqsave(&msm_chip->lock, irq_flags); /* level triggered interrupts are also latched */ @@ -250,11 +250,11 @@ static void msm_gpio_irq_mask(unsigned int irq) spin_unlock_irqrestore(&msm_chip->lock, irq_flags); } -static void msm_gpio_irq_unmask(unsigned int irq) +static void msm_gpio_irq_unmask(struct irq_data *d) { unsigned long irq_flags; - struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); - unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); + struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d); + unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); spin_lock_irqsave(&msm_chip->lock, irq_flags); /* level triggered interrupts are also latched */ @@ -265,11 +265,11 @@ static void msm_gpio_irq_unmask(unsigned int irq) spin_unlock_irqrestore(&msm_chip->lock, irq_flags); } -static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) +static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) { unsigned long irq_flags; - struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); - unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); + struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d); + unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); spin_lock_irqsave(&msm_chip->lock, irq_flags); @@ -282,21 +282,21 @@ static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) return 0; } -static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) +static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) { unsigned long irq_flags; - struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); - unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); + struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d); + unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); unsigned val, mask = BIT(offset); spin_lock_irqsave(&msm_chip->lock, irq_flags); val = readl(msm_chip->regs.int_edge); if (flow_type & IRQ_TYPE_EDGE_BOTH) { writel(val | mask, msm_chip->regs.int_edge); - irq_desc[irq].handle_irq = handle_edge_irq; + irq_desc[d->irq].handle_irq = handle_edge_irq; } else { writel(val & ~mask, msm_chip->regs.int_edge); - irq_desc[irq].handle_irq = handle_level_irq; + irq_desc[d->irq].handle_irq = handle_level_irq; } if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { msm_chip->both_edge_detect |= mask; @@ -333,16 +333,16 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) msm_chip->chip.base + j); } } - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); } static struct irq_chip msm_gpio_irq_chip = { - .name = "msmgpio", - .ack = msm_gpio_irq_ack, - .mask = msm_gpio_irq_mask, - .unmask = msm_gpio_irq_unmask, - .set_wake = msm_gpio_irq_set_wake, - .set_type = msm_gpio_irq_set_type, + .name = "msmgpio", + .irq_ack = msm_gpio_irq_ack, + .irq_mask = msm_gpio_irq_mask, + .irq_unmask = msm_gpio_irq_unmask, + .irq_set_wake = msm_gpio_irq_set_wake, + .irq_set_type = msm_gpio_irq_set_type, }; static int __init msm_init_gpio(void) diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c index 99f2c347303..68c28bbdc96 100644 --- a/arch/arm/mach-msm/irq-vic.c +++ b/arch/arm/mach-msm/irq-vic.c @@ -226,19 +226,18 @@ static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val) writel(val, base + (i * 4)); } -static void msm_irq_ack(unsigned int irq) +static void msm_irq_ack(struct irq_data *d) { - void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, irq); - irq = 1 << (irq & 31); - writel(irq, reg); + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, d->irq); + writel(1 << (d->irq & 31), reg); } -static void msm_irq_mask(unsigned int irq) +static void msm_irq_mask(struct irq_data *d) { - void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, irq); - unsigned index = VIC_INT_TO_REG_INDEX(irq); - uint32_t mask = 1UL << (irq & 31); - int smsm_irq = msm_irq_to_smsm[irq]; + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, d->irq); + unsigned index = VIC_INT_TO_REG_INDEX(d->irq); + uint32_t mask = 1UL << (d->irq & 31); + int smsm_irq = msm_irq_to_smsm[d->irq]; msm_irq_shadow_reg[index].int_en[0] &= ~mask; writel(mask, reg); @@ -250,12 +249,12 @@ static void msm_irq_mask(unsigned int irq) } } -static void msm_irq_unmask(unsigned int irq) +static void msm_irq_unmask(struct irq_data *d) { - void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, irq); - unsigned index = VIC_INT_TO_REG_INDEX(irq); - uint32_t mask = 1UL << (irq & 31); - int smsm_irq = msm_irq_to_smsm[irq]; + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, d->irq); + unsigned index = VIC_INT_TO_REG_INDEX(d->irq); + uint32_t mask = 1UL << (d->irq & 31); + int smsm_irq = msm_irq_to_smsm[d->irq]; msm_irq_shadow_reg[index].int_en[0] |= mask; writel(mask, reg); @@ -268,14 +267,14 @@ static void msm_irq_unmask(unsigned int irq) } } -static int msm_irq_set_wake(unsigned int irq, unsigned int on) +static int msm_irq_set_wake(struct irq_data *d, unsigned int on) { - unsigned index = VIC_INT_TO_REG_INDEX(irq); - uint32_t mask = 1UL << (irq & 31); - int smsm_irq = msm_irq_to_smsm[irq]; + unsigned index = VIC_INT_TO_REG_INDEX(d->irq); + uint32_t mask = 1UL << (d->irq & 31); + int smsm_irq = msm_irq_to_smsm[d->irq]; if (smsm_irq == 0) { - printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", irq); + printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", d->irq); return -EINVAL; } if (on) @@ -294,12 +293,12 @@ static int msm_irq_set_wake(unsigned int irq, unsigned int on) return 0; } -static int msm_irq_set_type(unsigned int irq, unsigned int flow_type) +static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) { - void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, irq); - void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, irq); - unsigned index = VIC_INT_TO_REG_INDEX(irq); - int b = 1 << (irq & 31); + void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, d->irq); + void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, d->irq); + unsigned index = VIC_INT_TO_REG_INDEX(d->irq); + int b = 1 << (d->irq & 31); uint32_t polarity; uint32_t type; @@ -314,11 +313,11 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type) type = msm_irq_shadow_reg[index].int_type; if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { type |= b; - irq_desc[irq].handle_irq = handle_edge_irq; + irq_desc[d->irq].handle_irq = handle_edge_irq; } if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { type &= ~b; - irq_desc[irq].handle_irq = handle_level_irq; + irq_desc[d->irq].handle_irq = handle_level_irq; } writel(type, treg); msm_irq_shadow_reg[index].int_type = type; @@ -326,13 +325,13 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type) } static struct irq_chip msm_irq_chip = { - .name = "msm", - .disable = msm_irq_mask, - .ack = msm_irq_ack, - .mask = msm_irq_mask, - .unmask = msm_irq_unmask, - .set_wake = msm_irq_set_wake, - .set_type = msm_irq_set_type, + .name = "msm", + .irq_disable = msm_irq_mask, + .irq_ack = msm_irq_ack, + .irq_mask = msm_irq_mask, + .irq_unmask = msm_irq_unmask, + .irq_set_wake = msm_irq_set_wake, + .irq_set_type = msm_irq_set_type, }; void __init msm_init_irq(void) diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c index 6c8d5f8caef..0b27d899f40 100644 --- a/arch/arm/mach-msm/irq.c +++ b/arch/arm/mach-msm/irq.c @@ -64,35 +64,34 @@ #define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4)) #define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4)) -static void msm_irq_ack(unsigned int irq) +static void msm_irq_ack(struct irq_data *d) { - void __iomem *reg = VIC_INT_CLEAR0 + ((irq & 32) ? 4 : 0); - irq = 1 << (irq & 31); - writel(irq, reg); + void __iomem *reg = VIC_INT_CLEAR0 + ((d->irq & 32) ? 4 : 0); + writel(1 << (d->irq & 31), reg); } -static void msm_irq_mask(unsigned int irq) +static void msm_irq_mask(struct irq_data *d) { - void __iomem *reg = VIC_INT_ENCLEAR0 + ((irq & 32) ? 4 : 0); - writel(1 << (irq & 31), reg); + void __iomem *reg = VIC_INT_ENCLEAR0 + ((d->irq & 32) ? 4 : 0); + writel(1 << (d->irq & 31), reg); } -static void msm_irq_unmask(unsigned int irq) +static void msm_irq_unmask(struct irq_data *d) { - void __iomem *reg = VIC_INT_ENSET0 + ((irq & 32) ? 4 : 0); - writel(1 << (irq & 31), reg); + void __iomem *reg = VIC_INT_ENSET0 + ((d->irq & 32) ? 4 : 0); + writel(1 << (d->irq & 31), reg); } -static int msm_irq_set_wake(unsigned int irq, unsigned int on) +static int msm_irq_set_wake(struct irq_data *d, unsigned int on) { return -EINVAL; } -static int msm_irq_set_type(unsigned int irq, unsigned int flow_type) +static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) { - void __iomem *treg = VIC_INT_TYPE0 + ((irq & 32) ? 4 : 0); - void __iomem *preg = VIC_INT_POLARITY0 + ((irq & 32) ? 4 : 0); - int b = 1 << (irq & 31); + void __iomem *treg = VIC_INT_TYPE0 + ((d->irq & 32) ? 4 : 0); + void __iomem *preg = VIC_INT_POLARITY0 + ((d->irq & 32) ? 4 : 0); + int b = 1 << (d->irq & 31); if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW)) writel(readl(preg) | b, preg); @@ -101,22 +100,22 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type) if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { writel(readl(treg) | b, treg); - irq_desc[irq].handle_irq = handle_edge_irq; + irq_desc[d->irq].handle_irq = handle_edge_irq; } if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { writel(readl(treg) & (~b), treg); - irq_desc[irq].handle_irq = handle_level_irq; + irq_desc[d->irq].handle_irq = handle_level_irq; } return 0; } static struct irq_chip msm_irq_chip = { - .name = "msm", - .ack = msm_irq_ack, - .mask = msm_irq_mask, - .unmask = msm_irq_unmask, - .set_wake = msm_irq_set_wake, - .set_type = msm_irq_set_type, + .name = "msm", + .irq_ack = msm_irq_ack, + .irq_mask = msm_irq_mask, + .irq_unmask = msm_irq_unmask, + .irq_set_wake = msm_irq_set_wake, + .irq_set_type = msm_irq_set_type, }; void __init msm_init_irq(void) diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c index 152eefda3ce..11b54c7aeb0 100644 --- a/arch/arm/mach-msm/sirc.c +++ b/arch/arm/mach-msm/sirc.c @@ -42,12 +42,11 @@ static struct sirc_cascade_regs sirc_reg_table[] = { /* Mask off the given interrupt. Keep the int_enable mask in sync with the enable reg, so it can be restored after power collapse. */ -static void sirc_irq_mask(unsigned int irq) +static void sirc_irq_mask(struct irq_data *d) { unsigned int mask; - - mask = 1 << (irq - FIRST_SIRC_IRQ); + mask = 1 << (d->irq - FIRST_SIRC_IRQ); writel(mask, sirc_regs.int_enable_clear); int_enable &= ~mask; return; @@ -55,31 +54,31 @@ static void sirc_irq_mask(unsigned int irq) /* Unmask the given interrupt. Keep the int_enable mask in sync with the enable reg, so it can be restored after power collapse. */ -static void sirc_irq_unmask(unsigned int irq) +static void sirc_irq_unmask(struct irq_data *d) { unsigned int mask; - mask = 1 << (irq - FIRST_SIRC_IRQ); + mask = 1 << (d->irq - FIRST_SIRC_IRQ); writel(mask, sirc_regs.int_enable_set); int_enable |= mask; return; } -static void sirc_irq_ack(unsigned int irq) +static void sirc_irq_ack(struct irq_data *d) { unsigned int mask; - mask = 1 << (irq - FIRST_SIRC_IRQ); + mask = 1 << (d->irq - FIRST_SIRC_IRQ); writel(mask, sirc_regs.int_clear); return; } -static int sirc_irq_set_wake(unsigned int irq, unsigned int on) +static int sirc_irq_set_wake(struct irq_data *d, unsigned int on) { unsigned int mask; /* Used to set the interrupt enable mask during power collapse. */ - mask = 1 << (irq - FIRST_SIRC_IRQ); + mask = 1 << (d->irq - FIRST_SIRC_IRQ); if (on) wake_enable |= mask; else @@ -88,12 +87,12 @@ static int sirc_irq_set_wake(unsigned int irq, unsigned int on) return 0; } -static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type) +static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type) { unsigned int mask; unsigned int val; - mask = 1 << (irq - FIRST_SIRC_IRQ); + mask = 1 << (d->irq - FIRST_SIRC_IRQ); val = readl(sirc_regs.int_polarity); if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING)) @@ -106,10 +105,10 @@ static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type) val = readl(sirc_regs.int_type); if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { val |= mask; - irq_desc[irq].handle_irq = handle_edge_irq; + irq_desc[d->irq].handle_irq = handle_edge_irq; } else { val &= ~mask; - irq_desc[irq].handle_irq = handle_level_irq; + irq_desc[d->irq].handle_irq = handle_level_irq; } writel(val, sirc_regs.int_type); @@ -139,16 +138,16 @@ static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc) ; generic_handle_irq(sirq+FIRST_SIRC_IRQ); - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); } static struct irq_chip sirc_irq_chip = { - .name = "sirc", - .ack = sirc_irq_ack, - .mask = sirc_irq_mask, - .unmask = sirc_irq_unmask, - .set_wake = sirc_irq_set_wake, - .set_type = sirc_irq_set_type, + .name = "sirc", + .irq_ack = sirc_irq_ack, + .irq_mask = sirc_irq_mask, + .irq_unmask = sirc_irq_unmask, + .irq_set_wake = sirc_irq_set_wake, + .irq_set_type = sirc_irq_set_type, }; void __init msm_init_sirc(void) diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 899a969e92f..0d65db885be 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -147,10 +147,10 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { .init_data = &pwgtx_init, }, { - .id = MC13783_REGU_GPO1, /* Turn on 1.8V */ + .id = MC13783_REG_GPO1, /* Turn on 1.8V */ .init_data = &gpo_init, }, { - .id = MC13783_REGU_GPO3, /* Turn on 3.3V */ + .id = MC13783_REG_GPO3, /* Turn on 3.3V */ .init_data = &gpo_init, }, }; diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index b993b9bf617..88b97d62b57 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -162,9 +162,9 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc) * Disable an expio pin's interrupt by setting the bit in the imr. * @param irq an expio virtual irq number */ -static void expio_mask_irq(u32 irq) +static void expio_mask_irq(struct irq_data *d) { - u32 expio = MXC_IRQ_TO_EXPIO(irq); + u32 expio = MXC_IRQ_TO_EXPIO(d->irq); /* mask the interrupt */ __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG); __raw_readw(PBC_INTMASK_CLEAR_REG); @@ -174,9 +174,9 @@ static void expio_mask_irq(u32 irq) * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. * @param irq an expanded io virtual irq number */ -static void expio_ack_irq(u32 irq) +static void expio_ack_irq(struct irq_data *d) { - u32 expio = MXC_IRQ_TO_EXPIO(irq); + u32 expio = MXC_IRQ_TO_EXPIO(d->irq); /* clear the interrupt status */ __raw_writew(1 << expio, PBC_INTSTATUS_REG); } @@ -185,18 +185,18 @@ static void expio_ack_irq(u32 irq) * Enable a expio pin's interrupt by clearing the bit in the imr. * @param irq a expio virtual irq number */ -static void expio_unmask_irq(u32 irq) +static void expio_unmask_irq(struct irq_data *d) { - u32 expio = MXC_IRQ_TO_EXPIO(irq); + u32 expio = MXC_IRQ_TO_EXPIO(d->irq); /* unmask the interrupt */ __raw_writew(1 << expio, PBC_INTMASK_SET_REG); } static struct irq_chip expio_irq_chip = { .name = "EXPIO(CPLD)", - .ack = expio_ack_irq, - .mask = expio_mask_irq, - .unmask = expio_unmask_irq, + .irq_ack = expio_ack_irq, + .irq_mask = expio_mask_irq, + .irq_unmask = expio_unmask_irq, }; static void __init mx31ads_init_expio(void) diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 55254b6e946..de4fa992fc3 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -50,6 +50,7 @@ config MACH_MX51_BABBAGE config MACH_MX51_3DS bool "Support MX51PDK (3DS)" select SOC_IMX51 + select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_SPI_IMX @@ -77,6 +78,7 @@ choice config MACH_EUKREA_MBIMX51_BASEBOARD prompt "Eukrea MBIMX51 development board" bool + select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX help This adds board specific devices that can be found on Eukrea's @@ -124,10 +126,28 @@ config MACH_MX53_EVK bool "Support MX53 EVK platforms" select SOC_IMX53 select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select IMX_HAVE_PLATFORM_SPI_IMX help Include support for MX53 EVK platform. This includes specific configurations for the board and its peripherals. +config MACH_MX53_SMD + bool "Support MX53 SMD platforms" + select SOC_IMX53 + select IMX_HAVE_PLATFORM_IMX_UART + help + Include support for MX53 SMD platform. This includes specific + configurations for the board and its peripherals. + +config MACH_MX53_LOCO + bool "Support MX53 LOCO platforms" + select SOC_IMX53 + select IMX_HAVE_PLATFORM_IMX_UART + help + Include support for MX53 LOCO platform. This includes specific + configurations for the board and its peripherals. config MACH_MX50_RDP bool "Support MX50 reference design platform" diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 0c398baf11f..0d43be98e51 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -10,6 +10,8 @@ obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o +obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o +obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index e42bd2eb034..49d64484237 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -12,7 +12,6 @@ #include <linux/irq.h> #include <linux/platform_device.h> -#include <linux/input/matrix_keypad.h> #include <linux/spi/spi.h> #include <asm/mach-types.h> @@ -120,14 +119,14 @@ static int mx51_3ds_board_keymap[] = { KEY(3, 5, KEY_BACK) }; -static struct matrix_keymap_data mx51_3ds_map_data = { +static const struct matrix_keymap_data mx51_3ds_map_data __initconst = { .keymap = mx51_3ds_board_keymap, .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap), }; static void mxc_init_keypad(void) { - mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data); + imx51_add_imx_keypad(&mx51_3ds_map_data); } #else static inline void mxc_init_keypad(void) diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c index fa97d0d5dd0..caee04c0823 100644 --- a/arch/arm/mach-mx5/board-mx53_evk.c +++ b/arch/arm/mach-mx5/board-mx53_evk.c @@ -21,6 +21,11 @@ #include <linux/init.h> #include <linux/clk.h> +#include <linux/fec.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/spi/flash.h> +#include <linux/spi/spi.h> #include <mach/common.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -29,6 +34,10 @@ #include <mach/imx-uart.h> #include <mach/iomux-mx53.h> +#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) +#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) +#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) + #include "crm_regs.h" #include "devices-imx53.h" @@ -47,6 +56,14 @@ static iomux_v3_cfg_t mx53_evk_pads[] = { MX53_PAD_ATA_CS_1__UART3_RXD, MX53_PAD_ATA_DA_1__UART3_CTS, MX53_PAD_ATA_DA_2__UART3_RTS, + + MX53_PAD_EIM_D16__CSPI1_SCLK, + MX53_PAD_EIM_D17__CSPI1_MISO, + MX53_PAD_EIM_D18__CSPI1_MOSI, + + /* ecspi chip select lines */ + MX53_PAD_EIM_EB2__GPIO_2_30, + MX53_PAD_EIM_D19__GPIO_3_19, }; static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { @@ -60,11 +77,68 @@ static inline void mx53_evk_init_uart(void) imx53_add_imx_uart(2, &mx53_evk_uart_pdata); } +static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = { + .bitrate = 100000, +}; + +static inline void mx53_evk_fec_reset(void) +{ + int ret; + + /* reset FEC PHY */ + ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset"); + if (ret) { + printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); + return; + } + gpio_direction_output(SMD_FEC_PHY_RST, 0); + gpio_set_value(SMD_FEC_PHY_RST, 0); + msleep(1); + gpio_set_value(SMD_FEC_PHY_RST, 1); +} + +static struct fec_platform_data mx53_evk_fec_pdata = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +static struct spi_board_info mx53_evk_spi_board_info[] __initdata = { + { + .modalias = "mtd_dataflash", + .max_speed_hz = 25000000, + .bus_num = 0, + .chip_select = 1, + .mode = SPI_MODE_0, + .platform_data = NULL, + }, +}; + +static int mx53_evk_spi_cs[] = { + EVK_ECSPI1_CS0, + EVK_ECSPI1_CS1, +}; + +static const struct spi_imx_master mx53_evk_spi_data __initconst = { + .chipselect = mx53_evk_spi_cs, + .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs), +}; + static void __init mx53_evk_board_init(void) { mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads, ARRAY_SIZE(mx53_evk_pads)); mx53_evk_init_uart(); + mx53_evk_fec_reset(); + imx53_add_fec(&mx53_evk_fec_pdata); + + imx53_add_imx_i2c(0, &mx53_evk_i2c_data); + imx53_add_imx_i2c(1, &mx53_evk_i2c_data); + + imx53_add_sdhci_esdhc_imx(0, NULL); + imx53_add_sdhci_esdhc_imx(1, NULL); + + spi_register_board_info(mx53_evk_spi_board_info, + ARRAY_SIZE(mx53_evk_spi_board_info)); + imx53_add_ecspi(0, &mx53_evk_spi_data); } static void __init mx53_evk_timer_init(void) diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c new file mode 100644 index 00000000000..d1348e04ace --- /dev/null +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/fec.h> +#include <linux/delay.h> +#include <linux/gpio.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx53.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include "crm_regs.h" +#include "devices-imx53.h" + +#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) + +static iomux_v3_cfg_t mx53_loco_pads[] = { + MX53_PAD_CSI0_D10__UART1_TXD, + MX53_PAD_CSI0_D11__UART1_RXD, + MX53_PAD_ATA_DIOW__UART1_TXD, + MX53_PAD_ATA_DMACK__UART1_RXD, + + MX53_PAD_ATA_BUFFER_EN__UART2_RXD, + MX53_PAD_ATA_DMARQ__UART2_TXD, + MX53_PAD_ATA_DIOR__UART2_RTS, + MX53_PAD_ATA_INTRQ__UART2_CTS, + + MX53_PAD_ATA_CS_0__UART3_TXD, + MX53_PAD_ATA_CS_1__UART3_RXD, + MX53_PAD_ATA_DA_1__UART3_CTS, + MX53_PAD_ATA_DA_2__UART3_RTS, +}; + +static const struct imxuart_platform_data mx53_loco_uart_data __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static inline void mx53_loco_init_uart(void) +{ + imx53_add_imx_uart(0, &mx53_loco_uart_data); + imx53_add_imx_uart(1, &mx53_loco_uart_data); + imx53_add_imx_uart(2, &mx53_loco_uart_data); +} + +static inline void mx53_loco_fec_reset(void) +{ + int ret; + + /* reset FEC PHY */ + ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset"); + if (ret) { + printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); + return; + } + gpio_direction_output(LOCO_FEC_PHY_RST, 0); + msleep(1); + gpio_set_value(LOCO_FEC_PHY_RST, 1); +} + +static struct fec_platform_data mx53_loco_fec_data = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +static void __init mx53_loco_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, + ARRAY_SIZE(mx53_loco_pads)); + mx53_loco_init_uart(); + mx53_loco_fec_reset(); + imx53_add_fec(&mx53_loco_fec_data); +} + +static void __init mx53_loco_timer_init(void) +{ + mx53_clocks_init(32768, 24000000, 0, 0); +} + +static struct sys_timer mx53_loco_timer = { + .init = mx53_loco_timer_init, +}; + +MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board") + .map_io = mx53_map_io, + .init_irq = mx53_init_irq, + .init_machine = mx53_loco_board_init, + .timer = &mx53_loco_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c new file mode 100644 index 00000000000..7970f7a4858 --- /dev/null +++ b/arch/arm/mach-mx5/board-mx53_smd.c @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/fec.h> +#include <linux/delay.h> +#include <linux/gpio.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx53.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include "crm_regs.h" +#include "devices-imx53.h" + +#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) + +static iomux_v3_cfg_t mx53_smd_pads[] = { + MX53_PAD_CSI0_D10__UART1_TXD, + MX53_PAD_CSI0_D11__UART1_RXD, + MX53_PAD_ATA_DIOW__UART1_TXD, + MX53_PAD_ATA_DMACK__UART1_RXD, + + MX53_PAD_ATA_BUFFER_EN__UART2_RXD, + MX53_PAD_ATA_DMARQ__UART2_TXD, + MX53_PAD_ATA_DIOR__UART2_RTS, + MX53_PAD_ATA_INTRQ__UART2_CTS, + + MX53_PAD_ATA_CS_0__UART3_TXD, + MX53_PAD_ATA_CS_1__UART3_RXD, + MX53_PAD_ATA_DA_1__UART3_CTS, + MX53_PAD_ATA_DA_2__UART3_RTS, +}; + +static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static inline void mx53_smd_init_uart(void) +{ + imx53_add_imx_uart(0, &mx53_smd_uart_data); + imx53_add_imx_uart(1, &mx53_smd_uart_data); + imx53_add_imx_uart(2, &mx53_smd_uart_data); +} + +static inline void mx53_smd_fec_reset(void) +{ + int ret; + + /* reset FEC PHY */ + ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset"); + if (ret) { + printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); + return; + } + gpio_direction_output(SMD_FEC_PHY_RST, 0); + msleep(1); + gpio_set_value(SMD_FEC_PHY_RST, 1); +} + +static struct fec_platform_data mx53_smd_fec_data = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +static void __init mx53_smd_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads, + ARRAY_SIZE(mx53_smd_pads)); + mx53_smd_init_uart(); + mx53_smd_fec_reset(); + imx53_add_fec(&mx53_smd_fec_data); +} + +static void __init mx53_smd_timer_init(void) +{ + mx53_clocks_init(32768, 24000000, 22579200, 0); +} + +static struct sys_timer mx53_smd_timer = { + .init = mx53_smd_timer_init, +}; + +MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board") + .map_io = mx53_map_io, + .init_irq = mx53_init_irq, + .init_machine = mx53_smd_board_init, + .timer = &mx53_smd_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 785e1a33618..0a19e7567c0 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -1191,6 +1191,11 @@ DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, NULL, NULL, &ipg_clk, &gpt_ipg_clk); +DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET, + NULL, NULL, &ipg_clk, NULL); +DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET, + NULL, NULL, &ipg_clk, NULL); + /* I2C */ DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET, NULL, NULL, &ipg_clk, NULL); @@ -1283,6 +1288,8 @@ static struct clk_lookup mx51_lookups[] = { _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) _REGISTER_CLOCK(NULL, "gpt", gpt_clk) _REGISTER_CLOCK("fec.0", NULL, fec_clk) + _REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk) + _REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk) _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk) @@ -1295,7 +1302,7 @@ static struct clk_lookup mx51_lookups[] = { _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) - _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) + _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk) _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) @@ -1326,6 +1333,13 @@ static struct clk_lookup mx53_lookups[] = { _REGISTER_CLOCK(NULL, "gpt", gpt_clk) _REGISTER_CLOCK("fec.0", NULL, fec_clk) _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) + _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) + _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) + _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) + _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) + _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk) + _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk) + _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk) }; static void clk_tree_init(void) @@ -1363,7 +1377,6 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, clk_tree_init(); - clk_set_parent(&uart_root_clk, &pll3_sw_clk); clk_enable(&cpu_clk); clk_enable(&main_bus_clk); @@ -1406,6 +1419,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, clk_tree_init(); + clk_set_parent(&uart_root_clk, &pll3_sw_clk); clk_enable(&cpu_clk); clk_enable(&main_bus_clk); diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h index 6302e467000..7fff485e560 100644 --- a/arch/arm/mach-mx5/devices-imx51.h +++ b/arch/arm/mach-mx5/devices-imx51.h @@ -47,3 +47,11 @@ extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst; extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst; #define imx51_add_imx2_wdt(id, pdata) \ imx_add_imx2_wdt(&imx51_imx2_wdt_data[id]) + +extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst; +#define imx51_add_mxc_pwm(id) \ + imx_add_mxc_pwm(&imx51_mxc_pwm_data[id]) + +extern const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst; +#define imx51_add_imx_keypad(pdata) \ + imx_add_imx_keypad(&imx51_imx_keypad_data, pdata) diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h index 9d0ec2507fa..8639735a117 100644 --- a/arch/arm/mach-mx5/devices-imx53.h +++ b/arch/arm/mach-mx5/devices-imx53.h @@ -8,6 +8,24 @@ #include <mach/mx53.h> #include <mach/devices-common.h> +extern const struct imx_fec_data imx53_fec_data __initconst; +#define imx53_add_fec(pdata) \ + imx_add_fec(&imx53_fec_data, pdata) + extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst; #define imx53_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata) + + +extern const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst; +#define imx53_add_imx_i2c(id, pdata) \ + imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata) + +extern const struct imx_sdhci_esdhc_imx_data +imx53_sdhci_esdhc_imx_data[] __initconst; +#define imx53_add_sdhci_esdhc_imx(id, pdata) \ + imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata) + +extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst; +#define imx53_add_ecspi(id, pdata) \ + imx_add_spi_imx(&imx53_ecspi_data[id], pdata) diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index 1bda5cb339d..153ada53e57 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -120,25 +120,6 @@ struct platform_device mxc_usbh2_device = { }, }; -static struct resource mxc_kpp_resources[] = { - { - .start = MX51_MXC_INT_KPP, - .end = MX51_MXC_INT_KPP, - .flags = IORESOURCE_IRQ, - } , { - .start = MX51_KPP_BASE_ADDR, - .end = MX51_KPP_BASE_ADDR + 0x8 - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxc_keypad_device = { - .name = "imx-keypad", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_kpp_resources), - .resource = mxc_kpp_resources, -}; - static struct mxc_gpio_port mxc_gpio_ports[] = { { .chip.label = "gpio-0", diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index 16891aa3573..55a5129bc29 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h @@ -3,4 +3,3 @@ extern struct platform_device mxc_usbh1_device; extern struct platform_device mxc_usbh2_device; extern struct platform_device mxc_usbdr_udc_device; extern struct platform_device mxc_hsi2c_device; -extern struct platform_device mxc_keypad_device; diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c index c96d018ff8a..e83ffadb65f 100644 --- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c @@ -21,7 +21,6 @@ #include <linux/fsl_devices.h> #include <linux/i2c/tsc2007.h> #include <linux/leds.h> -#include <linux/input/matrix_keypad.h> #include <mach/common.h> #include <mach/hardware.h> @@ -157,7 +156,7 @@ static int mbimx51_keymap[] = { KEY(3, 3, KEY_ENTER), }; -static struct matrix_keymap_data mbimx51_map_data = { +static const struct matrix_keymap_data mbimx51_map_data __initconst = { .keymap = mbimx51_keymap, .keymap_size = ARRAY_SIZE(mbimx51_keymap), }; @@ -209,7 +208,7 @@ void __init eukrea_mbimx51_baseboard_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); - mxc_register_device(&mxc_keypad_device, &mbimx51_map_data); + imx51_add_imx_keypad(&mbimx51_map_data); gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq"); gpio_direction_input(MBIMX51_TSC2007_GPIO); diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index c4ac7b41519..8bfc8df5461 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -15,7 +15,7 @@ comment "MXS platforms:" config MACH_MX23EVK bool "Support MX23EVK Platform" select SOC_IMX23 - select MXS_HAVE_PLATFORM_DUART + select MXS_HAVE_AMBA_DUART default y help Include support for MX23EVK platform. This includes specific @@ -24,7 +24,7 @@ config MACH_MX23EVK config MACH_MX28EVK bool "Support MX28EVK Platform" select SOC_IMX28 - select MXS_HAVE_PLATFORM_DUART + select MXS_HAVE_AMBA_DUART select MXS_HAVE_PLATFORM_FEC default y help diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c index 8f5a19ab558..b1a362ebfde 100644 --- a/arch/arm/mach-mxs/clock-mx23.c +++ b/arch/arm/mach-mxs/clock-mx23.c @@ -21,6 +21,7 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/jiffies.h> +#include <linux/clkdev.h> #include <asm/clkdev.h> #include <asm/div64.h> @@ -437,10 +438,12 @@ _DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk); }, static struct clk_lookup lookups[] = { - _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk) + /* for amba bus driver */ + _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk) + /* for amba-pl011 driver */ + _REGISTER_CLOCK("duart", NULL, uart_clk) _REGISTER_CLOCK("rtc", NULL, rtc_clk) _REGISTER_CLOCK(NULL, "hclk", hbus_clk) - _REGISTER_CLOCK(NULL, "xclk", xbus_clk) _REGISTER_CLOCK(NULL, "usb", usb_clk) _REGISTER_CLOCK(NULL, "audio", audio_clk) _REGISTER_CLOCK(NULL, "pwm", pwm_clk) @@ -518,6 +521,12 @@ int __init mx23_clocks_init(void) { clk_misc_init(); + clk_enable(&cpu_clk); + clk_enable(&hbus_clk); + clk_enable(&xbus_clk); + clk_enable(&emi_clk); + clk_enable(&uart_clk); + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0); diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 74e2103c601..56312c092a9 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -21,6 +21,7 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/jiffies.h> +#include <linux/clkdev.h> #include <asm/clkdev.h> #include <asm/div64.h> @@ -602,7 +603,12 @@ _DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk); }, static struct clk_lookup lookups[] = { - _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk) + /* for amba bus driver */ + _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk) + /* for amba-pl011 driver */ + _REGISTER_CLOCK("duart", NULL, uart_clk) + _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk) + _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk) _REGISTER_CLOCK("fec.0", NULL, fec_clk) _REGISTER_CLOCK("rtc", NULL, rtc_clk) _REGISTER_CLOCK("pll2", NULL, pll2_clk) @@ -726,6 +732,12 @@ int __init mx28_clocks_init(void) { clk_misc_init(); + clk_enable(&cpu_clk); + clk_enable(&hbus_clk); + clk_enable(&xbus_clk); + clk_enable(&emi_clk); + clk_enable(&uart_clk); + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0); diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h index d0f49fc0abb..1256788561d 100644 --- a/arch/arm/mach-mxs/devices-mx23.h +++ b/arch/arm/mach-mxs/devices-mx23.h @@ -11,6 +11,6 @@ #include <mach/mx23.h> #include <mach/devices-common.h> -extern const struct mxs_duart_data mx23_duart_data __initconst; +extern const struct amba_device mx23_duart_device __initconst; #define mx23_add_duart() \ - mxs_add_duart(&mx23_duart_data) + mxs_add_duart(&mx23_duart_device) diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 00b736c434b..33773a6333a 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -11,9 +11,9 @@ #include <mach/mx28.h> #include <mach/devices-common.h> -extern const struct mxs_duart_data mx28_duart_data __initconst; +extern const struct amba_device mx28_duart_device __initconst; #define mx28_add_duart() \ - mxs_add_duart(&mx28_duart_data) + mxs_add_duart(&mx28_duart_device) extern const struct mxs_fec_data mx28_fec_data[] __initconst; #define mx28_add_fec(id, pdata) \ diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c index 6b60f02ca2e..c20d54740b0 100644 --- a/arch/arm/mach-mxs/devices.c +++ b/arch/arm/mach-mxs/devices.c @@ -19,9 +19,8 @@ #include <linux/kernel.h> #include <linux/slab.h> #include <linux/init.h> -#include <linux/err.h> #include <linux/platform_device.h> -#include <mach/common.h> +#include <linux/amba/bus.h> struct platform_device *__init mxs_add_platform_device_dmamask( const char *name, int id, @@ -73,3 +72,17 @@ err: return pdev; } + +int __init mxs_add_amba_device(const struct amba_device *dev) +{ + struct amba_device *adev = kmalloc(sizeof(*adev), GFP_KERNEL); + + if (!adev) { + pr_err("%s: failed to allocate memory", __func__); + return -ENOMEM; + } + + *adev = *dev; + + return amba_device_register(adev, &iomem_resource); +} diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig index a35a2dc5539..cf7dc1ae575 100644 --- a/arch/arm/mach-mxs/devices/Kconfig +++ b/arch/arm/mach-mxs/devices/Kconfig @@ -1,5 +1,6 @@ -config MXS_HAVE_PLATFORM_DUART +config MXS_HAVE_AMBA_DUART bool + select ARM_AMBA config MXS_HAVE_PLATFORM_FEC bool diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index 4b5266a3e6d..d0a09f6934b 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile @@ -1,2 +1,2 @@ -obj-$(CONFIG_MXS_HAVE_PLATFORM_DUART) += platform-duart.o +obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o diff --git a/arch/arm/mach-mxs/devices/amba-duart.c b/arch/arm/mach-mxs/devices/amba-duart.c new file mode 100644 index 00000000000..a559db09b49 --- /dev/null +++ b/arch/arm/mach-mxs/devices/amba-duart.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/irq.h> +#include <mach/mx23.h> +#include <mach/mx28.h> +#include <mach/devices-common.h> + +#define MXS_AMBA_DUART_DEVICE(name, soc) \ +const struct amba_device name##_device __initconst = { \ + .dev = { \ + .init_name = "duart", \ + }, \ + .res = { \ + .start = soc ## _DUART_BASE_ADDR, \ + .end = (soc ## _DUART_BASE_ADDR) + SZ_8K - 1, \ + .flags = IORESOURCE_MEM, \ + }, \ + .irq = {soc ## _INT_DUART, NO_IRQ}, \ +} + +#ifdef CONFIG_SOC_IMX23 +MXS_AMBA_DUART_DEVICE(mx23_duart, MX23); +#endif + +#ifdef CONFIG_SOC_IMX28 +MXS_AMBA_DUART_DEVICE(mx28_duart, MX28); +#endif + +int __init mxs_add_duart(const struct amba_device *dev) +{ + return mxs_add_amba_device(dev); +} diff --git a/arch/arm/mach-mxs/devices/platform-duart.c b/arch/arm/mach-mxs/devices/platform-duart.c deleted file mode 100644 index 2fe0df5b0aa..00000000000 --- a/arch/arm/mach-mxs/devices/platform-duart.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <mach/mx23.h> -#include <mach/mx28.h> -#include <mach/devices-common.h> - -#define mxs_duart_data_entry(soc) \ - { \ - .iobase = soc ## _DUART_BASE_ADDR, \ - .irq = soc ## _INT_DUART, \ - } - -#ifdef CONFIG_SOC_IMX23 -const struct mxs_duart_data mx23_duart_data __initconst = - mxs_duart_data_entry(MX23); -#endif - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_duart_data mx28_duart_data __initconst = - mxs_duart_data_entry(MX28); -#endif - -struct platform_device *__init mxs_add_duart( - const struct mxs_duart_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device("mxs-duart", 0, res, ARRAY_SIZE(res), - NULL, 0); -} diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c index c08168cf3de..c42dff72b46 100644 --- a/arch/arm/mach-mxs/devices/platform-fec.c +++ b/arch/arm/mach-mxs/devices/platform-fec.c @@ -45,6 +45,6 @@ struct platform_device *__init mxs_add_fec( }, }; - return mxs_add_platform_device("fec", data->id, + return mxs_add_platform_device("imx28-fec", data->id, res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); } diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h index 3da48d4d327..6c3d1a10343 100644 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ b/arch/arm/mach-mxs/include/mach/devices-common.h @@ -9,6 +9,7 @@ #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/init.h> +#include <linux/amba/bus.h> struct platform_device *mxs_add_platform_device_dmamask( const char *name, int id, @@ -24,14 +25,10 @@ static inline struct platform_device *mxs_add_platform_device( name, id, res, num_resources, data, size_data, 0); } +int __init mxs_add_amba_device(const struct amba_device *dev); + /* duart */ -struct mxs_duart_data { - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init mxs_add_duart( - const struct mxs_duart_data *data); +int __init mxs_add_duart(const struct amba_device *dev); /* fec */ #include <linux/fec.h> diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c index d162e95910f..8e2c5975001 100644 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ b/arch/arm/mach-mxs/mach-mx28evk.c @@ -57,6 +57,19 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = { (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), MX28_PAD_ENET_CLK__CLKCTRL_ENET | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + /* fec1 */ + MX28_PAD_ENET0_CRS__ENET1_RX_EN | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET0_RXD2__ENET1_RXD0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET0_RXD3__ENET1_RXD1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET0_COL__ENET1_TX_EN | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET0_TXD2__ENET1_TXD0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET0_TXD3__ENET1_TXD1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), /* phy power line */ MX28_PAD_SSP1_DATA3__GPIO_2_15 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), @@ -106,8 +119,14 @@ static void __init mx28evk_fec_reset(void) gpio_set_value(MX28EVK_FEC_PHY_RESET, 1); } -static const struct fec_platform_data mx28_fec_pdata __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, +static struct fec_platform_data mx28_fec_pdata[] = { + { + /* fec0 */ + .phy = PHY_INTERFACE_MODE_RMII, + }, { + /* fec1 */ + .phy = PHY_INTERFACE_MODE_RMII, + }, }; static void __init mx28evk_init(void) @@ -117,7 +136,8 @@ static void __init mx28evk_init(void) mx28_add_duart(); mx28evk_fec_reset(); - mx28_add_fec(0, &mx28_fec_pdata); + mx28_add_fec(0, &mx28_fec_pdata[0]); + mx28_add_fec(1, &mx28_fec_pdata[1]); } static void __init mx28evk_timer_init(void) diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c index 43da8bb4926..29ffa750fbe 100644 --- a/arch/arm/mach-netx/generic.c +++ b/arch/arm/mach-netx/generic.c @@ -88,13 +88,13 @@ netx_hif_demux_handler(unsigned int irq_unused, struct irq_desc *desc) } static int -netx_hif_irq_type(unsigned int _irq, unsigned int type) +netx_hif_irq_type(struct irq_data *d, unsigned int type) { unsigned int val, irq; val = readl(NETX_DPMAS_IF_CONF1); - irq = _irq - NETX_IRQ_HIF_CHAINED(0); + irq = d->irq - NETX_IRQ_HIF_CHAINED(0); if (type & IRQ_TYPE_EDGE_RISING) { DEBUG_IRQ("rising edges\n"); @@ -119,49 +119,49 @@ netx_hif_irq_type(unsigned int _irq, unsigned int type) } static void -netx_hif_ack_irq(unsigned int _irq) +netx_hif_ack_irq(struct irq_data *d) { unsigned int val, irq; - irq = _irq - NETX_IRQ_HIF_CHAINED(0); + irq = d->irq - NETX_IRQ_HIF_CHAINED(0); writel((1 << 24) << irq, NETX_DPMAS_INT_STAT); val = readl(NETX_DPMAS_INT_EN); val &= ~((1 << 24) << irq); writel(val, NETX_DPMAS_INT_EN); - DEBUG_IRQ("%s: irq %d\n", __func__, _irq); + DEBUG_IRQ("%s: irq %d\n", __func__, d->irq); } static void -netx_hif_mask_irq(unsigned int _irq) +netx_hif_mask_irq(struct irq_data *d) { unsigned int val, irq; - irq = _irq - NETX_IRQ_HIF_CHAINED(0); + irq = d->irq - NETX_IRQ_HIF_CHAINED(0); val = readl(NETX_DPMAS_INT_EN); val &= ~((1 << 24) << irq); writel(val, NETX_DPMAS_INT_EN); - DEBUG_IRQ("%s: irq %d\n", __func__, _irq); + DEBUG_IRQ("%s: irq %d\n", __func__, d->irq); } static void -netx_hif_unmask_irq(unsigned int _irq) +netx_hif_unmask_irq(struct irq_data *d) { unsigned int val, irq; - irq = _irq - NETX_IRQ_HIF_CHAINED(0); + irq = d->irq - NETX_IRQ_HIF_CHAINED(0); val = readl(NETX_DPMAS_INT_EN); val |= (1 << 24) << irq; writel(val, NETX_DPMAS_INT_EN); - DEBUG_IRQ("%s: irq %d\n", __func__, _irq); + DEBUG_IRQ("%s: irq %d\n", __func__, d->irq); } static struct irq_chip netx_hif_chip = { - .ack = netx_hif_ack_irq, - .mask = netx_hif_mask_irq, - .unmask = netx_hif_unmask_irq, - .set_type = netx_hif_irq_type, + .irq_ack = netx_hif_ack_irq, + .irq_mask = netx_hif_mask_irq, + .irq_unmask = netx_hif_unmask_irq, + .irq_set_type = netx_hif_irq_type, }; void __init netx_init_irq(void) diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c index b45bb3b802f..0c0d5248c36 100644 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c @@ -37,44 +37,44 @@ void __init board_a9m9750dev_map_io(void) ARRAY_SIZE(board_a9m9750dev_io_desc)); } -static void a9m9750dev_fpga_ack_irq(unsigned int irq) +static void a9m9750dev_fpga_ack_irq(struct irq_data *d) { /* nothing */ } -static void a9m9750dev_fpga_mask_irq(unsigned int irq) +static void a9m9750dev_fpga_mask_irq(struct irq_data *d) { u8 ier; ier = __raw_readb(FPGA_IER); - ier &= ~(1 << (irq - FPGA_IRQ(0))); + ier &= ~(1 << (d->irq - FPGA_IRQ(0))); __raw_writeb(ier, FPGA_IER); } -static void a9m9750dev_fpga_maskack_irq(unsigned int irq) +static void a9m9750dev_fpga_maskack_irq(struct irq_data *d) { - a9m9750dev_fpga_mask_irq(irq); - a9m9750dev_fpga_ack_irq(irq); + a9m9750dev_fpga_mask_irq(d); + a9m9750dev_fpga_ack_irq(d); } -static void a9m9750dev_fpga_unmask_irq(unsigned int irq) +static void a9m9750dev_fpga_unmask_irq(struct irq_data *d) { u8 ier; ier = __raw_readb(FPGA_IER); - ier |= 1 << (irq - FPGA_IRQ(0)); + ier |= 1 << (d->irq - FPGA_IRQ(0)); __raw_writeb(ier, FPGA_IER); } static struct irq_chip a9m9750dev_fpga_chip = { - .ack = a9m9750dev_fpga_ack_irq, - .mask = a9m9750dev_fpga_mask_irq, - .mask_ack = a9m9750dev_fpga_maskack_irq, - .unmask = a9m9750dev_fpga_unmask_irq, + .irq_ack = a9m9750dev_fpga_ack_irq, + .irq_mask = a9m9750dev_fpga_mask_irq, + .irq_mask_ack = a9m9750dev_fpga_maskack_irq, + .irq_unmask = a9m9750dev_fpga_unmask_irq, }; static void a9m9750dev_fpga_demux_handler(unsigned int irq, @@ -82,7 +82,7 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq, { u8 stat = __raw_readb(FPGA_ISR); - desc->chip->mask_ack(irq); + desc->irq_data.chip->irq_mask_ack(&desc->irq_data); while (stat != 0) { int irqno = fls(stat) - 1; @@ -92,7 +92,7 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq, generic_handle_irq(FPGA_IRQ(irqno)); } - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); } void __init board_a9m9750dev_init_irq(void) diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c index 038f24d4702..389fa5c669d 100644 --- a/arch/arm/mach-ns9xxx/irq.c +++ b/arch/arm/mach-ns9xxx/irq.c @@ -22,40 +22,40 @@ #define irq2prio(i) (i) #define prio2irq(p) (p) -static void ns9xxx_mask_irq(unsigned int irq) +static void ns9xxx_mask_irq(struct irq_data *d) { /* XXX: better use cpp symbols */ - int prio = irq2prio(irq); + int prio = irq2prio(d->irq); u32 ic = __raw_readl(SYS_IC(prio / 4)); ic &= ~(1 << (7 + 8 * (3 - (prio & 3)))); __raw_writel(ic, SYS_IC(prio / 4)); } -static void ns9xxx_ack_irq(unsigned int irq) +static void ns9xxx_ack_irq(struct irq_data *d) { __raw_writel(0, SYS_ISRADDR); } -static void ns9xxx_maskack_irq(unsigned int irq) +static void ns9xxx_maskack_irq(struct irq_data *d) { - ns9xxx_mask_irq(irq); - ns9xxx_ack_irq(irq); + ns9xxx_mask_irq(d); + ns9xxx_ack_irq(d); } -static void ns9xxx_unmask_irq(unsigned int irq) +static void ns9xxx_unmask_irq(struct irq_data *d) { /* XXX: better use cpp symbols */ - int prio = irq2prio(irq); + int prio = irq2prio(d->irq); u32 ic = __raw_readl(SYS_IC(prio / 4)); ic |= 1 << (7 + 8 * (3 - (prio & 3))); __raw_writel(ic, SYS_IC(prio / 4)); } static struct irq_chip ns9xxx_chip = { - .ack = ns9xxx_ack_irq, - .mask = ns9xxx_mask_irq, - .mask_ack = ns9xxx_maskack_irq, - .unmask = ns9xxx_unmask_irq, + .irq_ack = ns9xxx_ack_irq, + .irq_mask = ns9xxx_mask_irq, + .irq_mask_ack = ns9xxx_maskack_irq, + .irq_unmask = ns9xxx_unmask_irq, }; #if 0 @@ -92,10 +92,10 @@ static void handle_prio_irq(unsigned int irq, struct irq_desc *desc) if (desc->status & IRQ_DISABLED) out_mask: - desc->chip->mask(irq); + desc->irq_data.chip->irq_mask(&desc->irq_data); /* ack unconditionally to unmask lower prio irqs */ - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); raw_spin_unlock(&desc->lock); } diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c index a7a88ea4ec3..1f8a05a2283 100644 --- a/arch/arm/mach-nuc93x/irq.c +++ b/arch/arm/mach-nuc93x/irq.c @@ -25,9 +25,9 @@ #include <mach/hardware.h> #include <mach/regs-irq.h> -static void nuc93x_irq_mask(unsigned int irq) +static void nuc93x_irq_mask(struct irq_data *d) { - __raw_writel(1 << irq, REG_AIC_MDCR); + __raw_writel(1 << d->irq, REG_AIC_MDCR); } /* @@ -35,21 +35,21 @@ static void nuc93x_irq_mask(unsigned int irq) * to REG_AIC_EOSCR for ACK */ -static void nuc93x_irq_ack(unsigned int irq) +static void nuc93x_irq_ack(struct irq_data *d) { __raw_writel(0x01, REG_AIC_EOSCR); } -static void nuc93x_irq_unmask(unsigned int irq) +static void nuc93x_irq_unmask(struct irq_data *d) { - __raw_writel(1 << irq, REG_AIC_MECR); + __raw_writel(1 << d->irq, REG_AIC_MECR); } static struct irq_chip nuc93x_irq_chip = { - .ack = nuc93x_irq_ack, - .mask = nuc93x_irq_mask, - .unmask = nuc93x_irq_unmask, + .irq_ack = nuc93x_irq_ack, + .irq_mask = nuc93x_irq_mask, + .irq_unmask = nuc93x_irq_unmask, }; void __init nuc93x_init_irq(void) diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 8d2f2daba0c..e0a028161dd 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -9,6 +9,7 @@ config ARCH_OMAP730 depends on ARCH_OMAP1 bool "OMAP730 Based System" select CPU_ARM926T + select OMAP_MPU_TIMER select ARCH_OMAP_OTG config ARCH_OMAP850 @@ -22,6 +23,7 @@ config ARCH_OMAP15XX default y bool "OMAP15xx Based System" select CPU_ARM925T + select OMAP_MPU_TIMER config ARCH_OMAP16XX depends on ARCH_OMAP1 diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 6ee19504845..ba6009f2767 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -3,12 +3,11 @@ # # Common support -obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o dma.o +obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o obj-y += clock.o clock_data.o opp_data.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o -obj-$(CONFIG_OMAP_MPU_TIMER) += time.o obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o # Power Management diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c index 6c994e2d887..152b32c15e2 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq.c +++ b/arch/arm/mach-omap1/ams-delta-fiq.c @@ -49,7 +49,7 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id) irq_desc = irq_to_desc(IH_GPIO_BASE); if (irq_desc) - irq_chip = irq_desc->chip; + irq_chip = irq_desc->irq_data.chip; /* * For each handled GPIO interrupt, keep calling its interrupt handler @@ -62,13 +62,15 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id) while (irq_counter[gpio] < fiq_count) { if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) { + struct irq_data *d = irq_get_irq_data(irq_num); + /* * It looks like handle_edge_irq() that * OMAP GPIO edge interrupts default to, * expects interrupt already unmasked. */ - if (irq_chip && irq_chip->unmask) - irq_chip->unmask(irq_num); + if (irq_chip && irq_chip->irq_unmask) + irq_chip->irq_unmask(d); } generic_handle_irq(irq_num); diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index bd0495a9ac3..22cc8c8df6c 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -179,6 +179,22 @@ static struct omap_board_config_kernel ams_delta_config[] = { { OMAP_TAG_LCD, &ams_delta_lcd_config }, }; +static struct resource ams_delta_nand_resources[] = { + [0] = { + .start = OMAP1_MPUIO_BASE, + .end = OMAP1_MPUIO_BASE + + OMAP_MPUIO_IO_CNTL + sizeof(u32) - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ams_delta_nand_device = { + .name = "ams-delta-nand", + .id = -1, + .num_resources = ARRAY_SIZE(ams_delta_nand_resources), + .resource = ams_delta_nand_resources, +}; + static struct resource ams_delta_kp_resources[] = { [0] = { .start = INT_KEYBOARD, @@ -265,6 +281,7 @@ static struct omap1_cam_platform_data ams_delta_camera_platform_data = { }; static struct platform_device *ams_delta_devices[] __initdata = { + &ams_delta_nand_device, &ams_delta_kp_device, &ams_delta_lcd_device, &ams_delta_led_device, diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 8780e75cdc3..0ace7998aaa 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c @@ -30,9 +30,9 @@ #include <plat/fpga.h> #include <mach/gpio.h> -static void fpga_mask_irq(unsigned int irq) +static void fpga_mask_irq(struct irq_data *d) { - irq -= OMAP_FPGA_IRQ_BASE; + unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE; if (irq < 8) __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) @@ -58,14 +58,14 @@ static inline u32 get_fpga_unmasked_irqs(void) } -static void fpga_ack_irq(unsigned int irq) +static void fpga_ack_irq(struct irq_data *d) { /* Don't need to explicitly ACK FPGA interrupts */ } -static void fpga_unmask_irq(unsigned int irq) +static void fpga_unmask_irq(struct irq_data *d) { - irq -= OMAP_FPGA_IRQ_BASE; + unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE; if (irq < 8) __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)), @@ -78,10 +78,10 @@ static void fpga_unmask_irq(unsigned int irq) | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2); } -static void fpga_mask_ack_irq(unsigned int irq) +static void fpga_mask_ack_irq(struct irq_data *d) { - fpga_mask_irq(irq); - fpga_ack_irq(irq); + fpga_mask_irq(d); + fpga_ack_irq(d); } void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc) @@ -105,17 +105,17 @@ void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc) static struct irq_chip omap_fpga_irq_ack = { .name = "FPGA-ack", - .ack = fpga_mask_ack_irq, - .mask = fpga_mask_irq, - .unmask = fpga_unmask_irq, + .irq_ack = fpga_mask_ack_irq, + .irq_mask = fpga_mask_irq, + .irq_unmask = fpga_unmask_irq, }; static struct irq_chip omap_fpga_irq = { .name = "FPGA", - .ack = fpga_ack_irq, - .mask = fpga_mask_irq, - .unmask = fpga_unmask_irq, + .irq_ack = fpga_ack_irq, + .irq_mask = fpga_mask_irq, + .irq_unmask = fpga_unmask_irq, }; /* diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index 6bddbc869f4..47701584df3 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c @@ -70,48 +70,48 @@ static inline void irq_bank_writel(unsigned long value, int bank, int offset) omap_writel(value, irq_banks[bank].base_reg + offset); } -static void omap_ack_irq(unsigned int irq) +static void omap_ack_irq(struct irq_data *d) { - if (irq > 31) + if (d->irq > 31) omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET); omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET); } -static void omap_mask_irq(unsigned int irq) +static void omap_mask_irq(struct irq_data *d) { - int bank = IRQ_BANK(irq); + int bank = IRQ_BANK(d->irq); u32 l; l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); - l |= 1 << IRQ_BIT(irq); + l |= 1 << IRQ_BIT(d->irq); omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); } -static void omap_unmask_irq(unsigned int irq) +static void omap_unmask_irq(struct irq_data *d) { - int bank = IRQ_BANK(irq); + int bank = IRQ_BANK(d->irq); u32 l; l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); - l &= ~(1 << IRQ_BIT(irq)); + l &= ~(1 << IRQ_BIT(d->irq)); omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); } -static void omap_mask_ack_irq(unsigned int irq) +static void omap_mask_ack_irq(struct irq_data *d) { - omap_mask_irq(irq); - omap_ack_irq(irq); + omap_mask_irq(d); + omap_ack_irq(d); } -static int omap_wake_irq(unsigned int irq, unsigned int enable) +static int omap_wake_irq(struct irq_data *d, unsigned int enable) { - int bank = IRQ_BANK(irq); + int bank = IRQ_BANK(d->irq); if (enable) - irq_banks[bank].wake_enable |= IRQ_BIT(irq); + irq_banks[bank].wake_enable |= IRQ_BIT(d->irq); else - irq_banks[bank].wake_enable &= ~IRQ_BIT(irq); + irq_banks[bank].wake_enable &= ~IRQ_BIT(d->irq); return 0; } @@ -168,10 +168,10 @@ static struct omap_irq_bank omap1610_irq_banks[] = { static struct irq_chip omap_irq_chip = { .name = "MPU", - .ack = omap_mask_ack_irq, - .mask = omap_mask_irq, - .unmask = omap_unmask_irq, - .set_wake = omap_wake_irq, + .irq_ack = omap_mask_ack_irq, + .irq_mask = omap_mask_irq, + .irq_unmask = omap_unmask_irq, + .irq_set_wake = omap_wake_irq, }; void __init omap_init_irq(void) @@ -239,9 +239,9 @@ void __init omap_init_irq(void) /* Unmask level 2 handler */ if (cpu_is_omap7xx()) - omap_unmask_irq(INT_7XX_IH2_IRQ); + omap_unmask_irq(irq_get_irq_data(INT_7XX_IH2_IRQ)); else if (cpu_is_omap15xx()) - omap_unmask_irq(INT_1510_IH2_IRQ); + omap_unmask_irq(irq_get_irq_data(INT_1510_IH2_IRQ)); else if (cpu_is_omap16xx()) - omap_unmask_irq(INT_1610_IH2_IRQ); + omap_unmask_irq(irq_get_irq_data(INT_1610_IH2_IRQ)); } diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index ed7a61ff916..f83fc335c61 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -44,16 +44,21 @@ #include <linux/clocksource.h> #include <linux/clockchips.h> #include <linux/io.h> +#include <linux/sched.h> #include <asm/system.h> #include <mach/hardware.h> #include <asm/leds.h> #include <asm/irq.h> +#include <asm/sched_clock.h> + #include <asm/mach/irq.h> #include <asm/mach/time.h> #include <plat/common.h> +#ifdef CONFIG_OMAP_MPU_TIMER + #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE #define OMAP_MPU_TIMER_OFFSET 0x100 @@ -67,7 +72,7 @@ typedef struct { ((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ (n)*OMAP_MPU_TIMER_OFFSET)) -static inline unsigned long omap_mpu_timer_read(int nr) +static inline unsigned long notrace omap_mpu_timer_read(int nr) { volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); return timer->read_tim; @@ -212,6 +217,32 @@ static struct clocksource clocksource_mpu = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +static DEFINE_CLOCK_DATA(cd); + +static inline unsigned long long notrace _omap_mpu_sched_clock(void) +{ + u32 cyc = mpu_read(&clocksource_mpu); + return cyc_to_sched_clock(&cd, cyc, (u32)~0); +} + +#ifndef CONFIG_OMAP_32K_TIMER +unsigned long long notrace sched_clock(void) +{ + return _omap_mpu_sched_clock(); +} +#else +static unsigned long long notrace omap_mpu_sched_clock(void) +{ + return _omap_mpu_sched_clock(); +} +#endif + +static void notrace mpu_update_sched_clock(void) +{ + u32 cyc = mpu_read(&clocksource_mpu); + update_sched_clock(&cd, cyc, (u32)~0); +} + static void __init omap_init_clocksource(unsigned long rate) { static char err[] __initdata = KERN_ERR @@ -219,17 +250,13 @@ static void __init omap_init_clocksource(unsigned long rate) setup_irq(INT_TIMER2, &omap_mpu_timer2_irq); omap_mpu_timer_start(1, ~0, 1); + init_sched_clock(&cd, mpu_update_sched_clock, 32, rate); if (clocksource_register_hz(&clocksource_mpu, rate)) printk(err, clocksource_mpu.name); } -/* - * --------------------------------------------------------------------------- - * Timer initialization - * --------------------------------------------------------------------------- - */ -static void __init omap_timer_init(void) +static void __init omap_mpu_timer_init(void) { struct clk *ck_ref = clk_get(NULL, "ck_ref"); unsigned long rate; @@ -246,6 +273,66 @@ static void __init omap_timer_init(void) omap_init_clocksource(rate); } +#else +static inline void omap_mpu_timer_init(void) +{ + pr_err("Bogus timer, should not happen\n"); +} +#endif /* CONFIG_OMAP_MPU_TIMER */ + +#if defined(CONFIG_OMAP_MPU_TIMER) && defined(CONFIG_OMAP_32K_TIMER) +static unsigned long long (*preferred_sched_clock)(void); + +unsigned long long notrace sched_clock(void) +{ + if (!preferred_sched_clock) + return 0; + + return preferred_sched_clock(); +} + +static inline void preferred_sched_clock_init(bool use_32k_sched_clock) +{ + if (use_32k_sched_clock) + preferred_sched_clock = omap_32k_sched_clock; + else + preferred_sched_clock = omap_mpu_sched_clock; +} +#else +static inline void preferred_sched_clock_init(bool use_32k_sched_clcok) +{ +} +#endif + +static inline int omap_32k_timer_usable(void) +{ + int res = false; + + if (cpu_is_omap730() || cpu_is_omap15xx()) + return res; + +#ifdef CONFIG_OMAP_32K_TIMER + res = omap_32k_timer_init(); +#endif + + return res; +} + +/* + * --------------------------------------------------------------------------- + * Timer initialization + * --------------------------------------------------------------------------- + */ +static void __init omap_timer_init(void) +{ + if (omap_32k_timer_usable()) { + preferred_sched_clock_init(1); + } else { + omap_mpu_timer_init(); + preferred_sched_clock_init(0); + } +} + struct sys_timer omap_timer = { .init = omap_timer_init, }; diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c index 20cfbcc6c60..13d7b8f145b 100644 --- a/arch/arm/mach-omap1/timer32k.c +++ b/arch/arm/mach-omap1/timer32k.c @@ -52,10 +52,9 @@ #include <asm/irq.h> #include <asm/mach/irq.h> #include <asm/mach/time.h> +#include <plat/common.h> #include <plat/dmtimer.h> -struct sys_timer omap_timer; - /* * --------------------------------------------------------------------------- * 32KHz OS timer @@ -181,14 +180,14 @@ static __init void omap_init_32k_timer(void) * Timer initialization * --------------------------------------------------------------------------- */ -static void __init omap_timer_init(void) +bool __init omap_32k_timer_init(void) { + omap_init_clocksource_32k(); + #ifdef CONFIG_OMAP_DM_TIMER omap_dm_timer_init(); #endif omap_init_32k_timer(); -} -struct sys_timer omap_timer = { - .init = omap_timer_init, -}; + return true; +} diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index a70bdf28e2b..07d1b20b114 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -554,6 +554,7 @@ static void __init omap_sfh7741prox_init(void) #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { + OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else @@ -576,11 +577,12 @@ static void __init omap_4430sdp_init(void) omap4_twl6030_hsmmc_init(mmc); /* Power on the ULPI PHY */ - if (gpio_is_valid(OMAP4SDP_MDM_PWR_EN_GPIO)) { - /* FIXME: Assumes pad is already muxed for GPIO mode */ - gpio_request(OMAP4SDP_MDM_PWR_EN_GPIO, "USBB1 PHY VMDM_3V3"); + status = gpio_request(OMAP4SDP_MDM_PWR_EN_GPIO, "USBB1 PHY VMDM_3V3"); + if (status) + pr_err("%s: Could not get USBB1 PHY GPIO\n", __func__); + else gpio_direction_output(OMAP4SDP_MDM_PWR_EN_GPIO, 1); - } + usb_ehci_init(&ehci_pdata); usb_musb_init(&musb_board_data); diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 5b0c77732df..8f9a64d650e 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -124,8 +124,9 @@ static inline void cm_t3517_init_hecc(void) {} #if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE) #define RTC_IO_GPIO (153) #define RTC_WR_GPIO (154) -#define RTC_RD_GPIO (160) +#define RTC_RD_GPIO (53) #define RTC_CS_GPIO (163) +#define RTC_CS_EN_GPIO (160) struct v3020_platform_data cm_t3517_v3020_pdata = { .use_gpio = 1, @@ -145,6 +146,16 @@ static struct platform_device cm_t3517_rtc_device = { static void __init cm_t3517_init_rtc(void) { + int err; + + err = gpio_request(RTC_CS_EN_GPIO, "rtc cs en"); + if (err) { + pr_err("CM-T3517: rtc cs en gpio request failed: %d\n", err); + return; + } + + gpio_direction_output(RTC_CS_EN_GPIO, 1); + platform_device_register(&cm_t3517_rtc_device); } #else @@ -214,12 +225,12 @@ static struct mtd_partition cm_t3517_nand_partitions[] = { }, { .name = "linux", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ + .offset = MTDPART_OFS_APPEND, /* Offset = 0x2A0000 */ .size = 32 * NAND_BLOCK_SIZE, }, { .name = "rootfs", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */ + .offset = MTDPART_OFS_APPEND, /* Offset = 0x6A0000 */ .size = MTDPART_SIZ_FULL, }, }; @@ -256,11 +267,19 @@ static void __init cm_t3517_init_irq(void) static struct omap_board_mux board_mux[] __initdata = { /* GPIO186 - Green LED */ OMAP3_MUX(SYS_CLKOUT2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), - /* RTC GPIOs: IO, WR#, RD#, CS# */ + + /* RTC GPIOs: */ + /* IO - GPIO153 */ OMAP3_MUX(MCBSP4_DR, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + /* WR# - GPIO154 */ OMAP3_MUX(MCBSP4_DX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), - OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + /* RD# - GPIO53 */ + OMAP3_MUX(GPMC_NCS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + /* CS# - GPIO163 */ OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + /* CS EN - GPIO160 */ + OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + /* HSUSB1 RESET */ OMAP3_MUX(UART2_TX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), /* HSUSB2 RESET */ diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 00bb1fc5e01..e906e05bb41 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -275,8 +275,7 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = { .irq_base = TWL4030_GPIO_IRQ_BASE, .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, - .pullups = BIT(1), - .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13) + .pulldowns = BIT(1) | BIT(2) | BIT(6) | BIT(8) | BIT(13) | BIT(15) | BIT(16) | BIT(17), .setup = devkit8000_twl_gpio_setup, }; diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index ebaa230e67e..3be85a1f55f 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -17,6 +17,7 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/interrupt.h> +#include <linux/input.h> #include <linux/regulator/machine.h> #include <linux/regulator/fixed.h> @@ -541,6 +542,37 @@ static struct twl4030_codec_data igep2_codec_data = { .audio = &igep2_audio_data, }; +static int igep2_keymap[] = { + KEY(0, 0, KEY_LEFT), + KEY(0, 1, KEY_RIGHT), + KEY(0, 2, KEY_A), + KEY(0, 3, KEY_B), + KEY(1, 0, KEY_DOWN), + KEY(1, 1, KEY_UP), + KEY(1, 2, KEY_E), + KEY(1, 3, KEY_F), + KEY(2, 0, KEY_ENTER), + KEY(2, 1, KEY_I), + KEY(2, 2, KEY_J), + KEY(2, 3, KEY_K), + KEY(3, 0, KEY_M), + KEY(3, 1, KEY_N), + KEY(3, 2, KEY_O), + KEY(3, 3, KEY_P) +}; + +static struct matrix_keymap_data igep2_keymap_data = { + .keymap = igep2_keymap, + .keymap_size = ARRAY_SIZE(igep2_keymap), +}; + +static struct twl4030_keypad_data igep2_keypad_pdata = { + .keymap_data = &igep2_keymap_data, + .rows = 4, + .cols = 4, + .rep = 1, +}; + static struct twl4030_platform_data igep2_twldata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, @@ -549,6 +581,7 @@ static struct twl4030_platform_data igep2_twldata = { .usb = &igep2_usb_data, .codec = &igep2_codec_data, .gpio = &igep2_twl4030_gpio_pdata, + .keypad = &igep2_keypad_pdata, .vmmc1 = &igep2_vmmc1, .vpll2 = &igep2_vpll2, .vio = &igep2_vio, diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c index bcccd68f185..4dc62a9b9cb 100644 --- a/arch/arm/mach-omap2/board-igep0030.c +++ b/arch/arm/mach-omap2/board-igep0030.c @@ -19,6 +19,7 @@ #include <linux/interrupt.h> #include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> #include <linux/i2c/twl.h> #include <linux/mmc/host.h> @@ -43,7 +44,7 @@ #define IGEP3_GPIO_WIFI_NRESET 139 #define IGEP3_GPIO_BT_NRESET 137 -#define IGEP3_GPIO_USBH_NRESET 115 +#define IGEP3_GPIO_USBH_NRESET 183 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ @@ -103,7 +104,7 @@ static struct platform_device igep3_onenand_device = { }, }; -void __init igep3_flash_init(void) +static void __init igep3_flash_init(void) { u8 cs = 0; u8 onenandcs = GPMC_CS_NUM + 1; @@ -137,12 +138,11 @@ void __init igep3_flash_init(void) } #else -void __init igep3_flash_init(void) {} +static void __init igep3_flash_init(void) {} #endif -static struct regulator_consumer_supply igep3_vmmc1_supply = { - .supply = "vmmc", -}; +static struct regulator_consumer_supply igep3_vmmc1_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ static struct regulator_init_data igep3_vmmc1 = { @@ -159,6 +159,52 @@ static struct regulator_init_data igep3_vmmc1 = { .consumer_supplies = &igep3_vmmc1_supply, }; +static struct regulator_consumer_supply igep3_vio_supply = + REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); + +static struct regulator_init_data igep3_vio = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &igep3_vio_supply, +}; + +static struct regulator_consumer_supply igep3_vmmc2_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); + +static struct regulator_init_data igep3_vmmc2 = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .always_on = 1, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &igep3_vmmc2_supply, +}; + +static struct fixed_voltage_config igep3_vwlan = { + .supply_name = "vwlan", + .microvolts = 3300000, + .gpio = -EINVAL, + .enabled_at_boot = 1, + .init_data = &igep3_vmmc2, +}; + +static struct platform_device igep3_vwlan_device = { + .name = "reg-fixed-voltage", + .id = 0, + .dev = { + .platform_data = &igep3_vwlan, + }, +}; + static struct omap2_hsmmc_info mmc[] = { [0] = { .mmc = 1, @@ -254,12 +300,6 @@ static int igep3_twl4030_gpio_setup(struct device *dev, mmc[0].gpio_cd = gpio + 0; omap2_hsmmc_init(mmc); - /* - * link regulators to MMC adapters ... we "know" the - * regulators will be set up only *after* we return. - */ - igep3_vmmc1_supply.dev = mmc[0].dev; - /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ #if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0) @@ -287,6 +327,10 @@ static struct twl4030_usb_data igep3_twl4030_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; +static struct platform_device *igep3_devices[] __initdata = { + &igep3_vwlan_device, +}; + static void __init igep3_init_irq(void) { omap2_init_common_infrastructure(); @@ -303,6 +347,7 @@ static struct twl4030_platform_data igep3_twl4030_pdata = { .usb = &igep3_twl4030_usb_data, .gpio = &igep3_twl4030_gpio_pdata, .vmmc1 = &igep3_vmmc1, + .vio = &igep3_vio, }; static struct i2c_board_info __initdata igep3_i2c_boardinfo[] = { @@ -363,8 +408,20 @@ static void __init igep3_wifi_bt_init(void) void __init igep3_wifi_bt_init(void) {} #endif +static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { + .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = IGEP3_GPIO_USBH_NRESET, + .reset_gpio_port[2] = -EINVAL, +}; + #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { + OMAP3_MUX(I2C2_SDA, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #endif @@ -375,9 +432,10 @@ static void __init igep3_init(void) /* Register I2C busses and drivers */ igep3_i2c_init(); - + platform_add_devices(igep3_devices, ARRAY_SIZE(igep3_devices)); omap_serial_init(); usb_musb_init(&musb_board_data); + usb_ehci_init(&ehci_pdata); igep3_flash_init(); igep3_leds_init(); @@ -392,6 +450,7 @@ static void __init igep3_init(void) MACHINE_START(IGEP0030, "IGEP OMAP3 module") .boot_params = 0x80000100, + .reserve = omap_reserve, .map_io = omap3_map_io, .init_irq = igep3_init_irq, .init_machine = igep3_init, diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index a4fe8e1ee1b..46d814ab565 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -207,7 +207,7 @@ static struct omap_dss_device beagle_dvi_device = { .driver_name = "generic_dpi_panel", .data = &dvi_panel, .phy.dpi.data_lines = 24, - .reset_gpio = 170, + .reset_gpio = -EINVAL, }; static struct omap_dss_device beagle_tv_device = { @@ -279,6 +279,8 @@ static struct gpio_led gpio_leds[]; static int beagle_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { + int r; + if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) { mmc[0].gpio_wp = -EINVAL; } else if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) || @@ -299,17 +301,63 @@ static int beagle_twl_gpio_setup(struct device *dev, /* REVISIT: need ehci-omap hooks for external VBUS * power switch and overcurrent detect */ + if (omap3_beagle_get_rev() != OMAP3BEAGLE_BOARD_XM) { + r = gpio_request(gpio + 1, "EHCI_nOC"); + if (!r) { + r = gpio_direction_input(gpio + 1); + if (r) + gpio_free(gpio + 1); + } + if (r) + pr_err("%s: unable to configure EHCI_nOC\n", __func__); + } - gpio_request(gpio + 1, "EHCI_nOC"); - gpio_direction_input(gpio + 1); - - /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */ + /* + * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active + * high / others active low) + */ gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR"); - gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); + if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) + gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1); + else + gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); + + /* DVI reset GPIO is different between beagle revisions */ + if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) + beagle_dvi_device.reset_gpio = 129; + else + beagle_dvi_device.reset_gpio = 170; /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; + /* + * gpio + 1 on Xm controls the TFP410's enable line (active low) + * gpio + 2 control varies depending on the board rev as follows: + * P7/P8 revisions(prototype): Camera EN + * A2+ revisions (production): LDO (supplies DVI, serial, led blocks) + */ + if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) { + r = gpio_request(gpio + 1, "nDVI_PWR_EN"); + if (!r) { + r = gpio_direction_output(gpio + 1, 0); + if (r) + gpio_free(gpio + 1); + } + if (r) + pr_err("%s: unable to configure nDVI_PWR_EN\n", + __func__); + r = gpio_request(gpio + 2, "DVI_LDO_EN"); + if (!r) { + r = gpio_direction_output(gpio + 2, 1); + if (r) + gpio_free(gpio + 2); + } + if (r) + pr_err("%s: unable to configure DVI_LDO_EN\n", + __func__); + } + return 0; } diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 3094e200784..e001a048dc0 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -19,6 +19,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/clk.h> #include <linux/io.h> #include <linux/leds.h> #include <linux/gpio.h> @@ -95,7 +96,16 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { static void __init omap4_ehci_init(void) { int ret; + struct clk *phy_ref_clk; + /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */ + phy_ref_clk = clk_get(NULL, "auxclk3_ck"); + if (IS_ERR(phy_ref_clk)) { + pr_err("Cannot request auxclk3\n"); + goto error1; + } + clk_set_rate(phy_ref_clk, 19200000); + clk_enable(phy_ref_clk); /* disable the power to the usb hub prior to init */ ret = gpio_request(GPIO_HUB_POWER, "hub_power"); diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 14d95afa3f0..e0e040f34c6 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -192,7 +192,7 @@ static struct platform_device omap_vwlan_device = { }, }; -struct wl12xx_platform_data omap_zoom_wlan_data __initdata = { +static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = { .irq = OMAP_GPIO_IRQ(OMAP_ZOOM_WLAN_IRQ_GPIO), /* ZOOM ref clock is 26 MHz */ .board_ref_clock = 1, @@ -286,7 +286,7 @@ static int zoom_twl_gpio_setup(struct device *dev, } /* EXTMUTE callback function */ -void zoom2_set_hs_extmute(int mute) +static void zoom2_set_hs_extmute(int mute) { gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute); } diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index d3ab1c9e50b..403a4a1d3f9 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3286,7 +3286,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("ehci-omap.0", "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), + CLK("ehci-omap.0", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index e8cb32fd7f1..de9ec8ddd2a 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -34,7 +34,6 @@ #include "cm2_44xx.h" #include "cm-regbits-44xx.h" #include "prm44xx.h" -#include "prm44xx.h" #include "prm-regbits-44xx.h" #include "control.h" #include "scrm44xx.h" diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index e20b98636ab..58e42f76603 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -423,6 +423,12 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) { struct clkdm_dep *cd; + if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) { + pr_err("clockdomain: %s/%s: %s: not yet implemented\n", + clkdm1->name, clkdm2->name, __func__); + return -EINVAL; + } + if (!clkdm1 || !clkdm2) return -EINVAL; @@ -458,6 +464,12 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) { struct clkdm_dep *cd; + if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) { + pr_err("clockdomain: %s/%s: %s: not yet implemented\n", + clkdm1->name, clkdm2->name, __func__); + return -EINVAL; + } + if (!clkdm1 || !clkdm2) return -EINVAL; @@ -500,6 +512,12 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) if (!clkdm1 || !clkdm2) return -EINVAL; + if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) { + pr_err("clockdomain: %s/%s: %s: not yet implemented\n", + clkdm1->name, clkdm2->name, __func__); + return -EINVAL; + } + cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); if (IS_ERR(cd)) { pr_debug("clockdomain: hardware cannot set/clear wake up of " @@ -527,6 +545,12 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) struct clkdm_dep *cd; u32 mask = 0; + if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) { + pr_err("clockdomain: %s: %s: not yet implemented\n", + clkdm->name, __func__); + return -EINVAL; + } + if (!clkdm) return -EINVAL; @@ -830,8 +854,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm) * dependency code and data for OMAP4. */ if (cpu_is_omap44xx()) { - WARN_ONCE(1, "clockdomain: OMAP4 wakeup/sleep dependency " - "support is not yet implemented\n"); + pr_err("clockdomain: %s: OMAP4 wakeup/sleep dependency support: not yet implemented\n", clkdm->name); } else { if (atomic_read(&clkdm->usecount) > 0) _clkdm_add_autodeps(clkdm); @@ -872,8 +895,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm) * dependency code and data for OMAP4. */ if (cpu_is_omap44xx()) { - WARN_ONCE(1, "clockdomain: OMAP4 wakeup/sleep dependency " - "support is not yet implemented\n"); + pr_err("clockdomain: %s: OMAP4 wakeup/sleep dependency support: not yet implemented\n", clkdm->name); } else { if (atomic_read(&clkdm->usecount) > 0) _clkdm_del_autodeps(clkdm); diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index de3faa20b46..9b459c26fb8 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -103,9 +103,7 @@ struct clockdomain { const char *name; struct powerdomain *ptr; } pwrdm; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) const u16 clktrctrl_mask; -#endif const u8 flags; const u8 dep_bit; const u8 prcm_partition; diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index 51920fc7fc5..10622c914ab 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -30,8 +30,6 @@ #include "cm1_44xx.h" #include "cm2_44xx.h" -#include "cm1_44xx.h" -#include "cm2_44xx.h" #include "cm-regbits-44xx.h" #include "prm44xx.h" #include "prcm44xx.h" diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 11b89e9687f..f7b22a16f38 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -47,6 +47,8 @@ #define OMAP3_STATE_MAX OMAP3_STATE_C7 +#define CPUIDLE_FLAG_CHECK_BM 0x10000 /* use omap3_enter_idle_bm() */ + struct omap3_processor_cx { u8 valid; u8 type; diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 381f4eb9235..2c9c912f2c4 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -978,7 +978,7 @@ static int __init omap2_init_devices(void) arch_initcall(omap2_init_devices); #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) -struct omap_device_pm_latency omap_wdt_latency[] = { +static struct omap_device_pm_latency omap_wdt_latency[] = { [0] = { .deactivate_func = omap_device_idle_hwmods, .activate_func = omap_device_enable_hwmods, diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 85bf8ca95fd..23049c487c4 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -100,13 +100,14 @@ static int omap_check_spurious(unsigned int irq) } /* XXX: FIQ and additional INTC support (only MPU at the moment) */ -static void omap_ack_irq(unsigned int irq) +static void omap_ack_irq(struct irq_data *d) { intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL); } -static void omap_mask_irq(unsigned int irq) +static void omap_mask_irq(struct irq_data *d) { + unsigned int irq = d->irq; int offset = irq & (~(IRQ_BITS_PER_REG - 1)); if (cpu_is_omap34xx()) { @@ -128,8 +129,9 @@ static void omap_mask_irq(unsigned int irq) intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset); } -static void omap_unmask_irq(unsigned int irq) +static void omap_unmask_irq(struct irq_data *d) { + unsigned int irq = d->irq; int offset = irq & (~(IRQ_BITS_PER_REG - 1)); irq &= (IRQ_BITS_PER_REG - 1); @@ -137,17 +139,17 @@ static void omap_unmask_irq(unsigned int irq) intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset); } -static void omap_mask_ack_irq(unsigned int irq) +static void omap_mask_ack_irq(struct irq_data *d) { - omap_mask_irq(irq); - omap_ack_irq(irq); + omap_mask_irq(d); + omap_ack_irq(d); } static struct irq_chip omap_irq_chip = { - .name = "INTC", - .ack = omap_mask_ack_irq, - .mask = omap_mask_irq, - .unmask = omap_unmask_irq, + .name = "INTC", + .irq_ack = omap_mask_ack_irq, + .irq_mask = omap_mask_irq, + .irq_unmask = omap_unmask_irq, }; static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 17bd6394d22..df8d2f2872c 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -893,7 +893,7 @@ static struct omap_mux * __init omap_mux_list_add( return NULL; m = &entry->mux; - memcpy(m, src, sizeof(struct omap_mux_entry)); + entry->mux = *src; #ifdef CONFIG_OMAP_MUX if (omap_mux_copy_names(src, m)) { diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index 440c98e9a51..17f80e4ab16 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c @@ -703,7 +703,7 @@ static struct omap_mux __initdata omap3_muxmodes[] = { * Signals different on CBC package compared to the superset */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBC) -struct omap_mux __initdata omap3_cbc_subset[] = { +static struct omap_mux __initdata omap3_cbc_subset[] = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else @@ -721,7 +721,7 @@ struct omap_mux __initdata omap3_cbc_subset[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined(CONFIG_OMAP_PACKAGE_CBC) -struct omap_ball __initdata omap3_cbc_ball[] = { +static struct omap_ball __initdata omap3_cbc_ball[] = { _OMAP3_BALLENTRY(CAM_D0, "ae16", NULL), _OMAP3_BALLENTRY(CAM_D1, "ae15", NULL), _OMAP3_BALLENTRY(CAM_D10, "d25", NULL), diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c index 980f11d45c7..c322e7bdaa1 100644 --- a/arch/arm/mach-omap2/mux44xx.c +++ b/arch/arm/mach-omap2/mux44xx.c @@ -544,7 +544,7 @@ static struct omap_mux __initdata omap4_core_muxmodes[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined(CONFIG_OMAP_PACKAGE_CBL) -struct omap_ball __initdata omap4_core_cbl_ball[] = { +static struct omap_ball __initdata omap4_core_cbl_ball[] = { _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL), _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL), _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL), @@ -1262,7 +1262,7 @@ static struct omap_mux __initdata omap4_es2_core_muxmodes[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined(CONFIG_OMAP_PACKAGE_CBS) -struct omap_ball __initdata omap4_core_cbs_ball[] = { +static struct omap_ball __initdata omap4_core_cbs_ball[] = { _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL), _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL), _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL), @@ -1546,7 +1546,7 @@ static struct omap_mux __initdata omap4_wkup_muxmodes[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined(CONFIG_OMAP_PACKAGE_CBL) -struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = { +static struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = { _OMAP4_BALLENTRY(SIM_IO, "h4", NULL), _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL), _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL), diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c index 15f8c6c1bb0..00e1d2b5368 100644 --- a/arch/arm/mach-omap2/omap_twl.c +++ b/arch/arm/mach-omap2/omap_twl.c @@ -20,6 +20,8 @@ #include <plat/voltage.h> +#include "pm.h" + #define OMAP3_SRI2C_SLAVE_ADDR 0x12 #define OMAP3_VDD_MPU_SR_CONTROL_REG 0x00 #define OMAP3_VDD_CORE_SR_CONTROL_REG 0x01 @@ -60,17 +62,17 @@ static u8 smps_offset; #define REG_SMPS_OFFSET 0xE0 -unsigned long twl4030_vsel_to_uv(const u8 vsel) +static unsigned long twl4030_vsel_to_uv(const u8 vsel) { return (((vsel * 125) + 6000)) * 100; } -u8 twl4030_uv_to_vsel(unsigned long uv) +static u8 twl4030_uv_to_vsel(unsigned long uv) { return DIV_ROUND_UP(uv - 600000, 12500); } -unsigned long twl6030_vsel_to_uv(const u8 vsel) +static unsigned long twl6030_vsel_to_uv(const u8 vsel) { /* * In TWL6030 depending on the value of SMPS_OFFSET @@ -102,7 +104,7 @@ unsigned long twl6030_vsel_to_uv(const u8 vsel) return ((((vsel - 1) * 125) + 6000)) * 100; } -u8 twl6030_uv_to_vsel(unsigned long uv) +static u8 twl6030_uv_to_vsel(unsigned long uv) { /* * In TWL6030 depending on the value of SMPS_OFFSET diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c index 784989f8f2f..5acd2ab298b 100644 --- a/arch/arm/mach-omap2/pm_bus.c +++ b/arch/arm/mach-omap2/pm_bus.c @@ -20,7 +20,7 @@ #include <plat/omap-pm.h> #ifdef CONFIG_PM_RUNTIME -int omap_pm_runtime_suspend(struct device *dev) +static int omap_pm_runtime_suspend(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); int r, ret = 0; @@ -37,7 +37,7 @@ int omap_pm_runtime_suspend(struct device *dev) return ret; }; -int omap_pm_runtime_resume(struct device *dev) +static int omap_pm_runtime_resume(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); int r; diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c index d5233890370..cf600e22bf8 100644 --- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c @@ -19,7 +19,6 @@ #include <plat/prcm.h> #include "powerdomain.h" -#include "prm-regbits-34xx.h" #include "prm.h" #include "prm-regbits-24xx.h" #include "prm-regbits-34xx.h" diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h index 53d44f6e373..49654c8d18f 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h @@ -228,7 +228,67 @@ #ifndef __ASSEMBLER__ - +/* + * Stub omap2xxx/omap3xxx functions so that common files + * continue to build when custom builds are used + */ +#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \ + defined(CONFIG_ARCH_OMAP3)) +static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx) +{ + WARN(1, "prm: omap2xxx/omap3xxx specific function and " + "not suppose to be used on omap4\n"); + return 0; +} +static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) +{ + WARN(1, "prm: omap2xxx/omap3xxx specific function and " + "not suppose to be used on omap4\n"); +} +static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, + s16 module, s16 idx) +{ + WARN(1, "prm: omap2xxx/omap3xxx specific function and " + "not suppose to be used on omap4\n"); + return 0; +} +static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) +{ + WARN(1, "prm: omap2xxx/omap3xxx specific function and " + "not suppose to be used on omap4\n"); + return 0; +} +static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) +{ + WARN(1, "prm: omap2xxx/omap3xxx specific function and " + "not suppose to be used on omap4\n"); + return 0; +} +static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) +{ + WARN(1, "prm: omap2xxx/omap3xxx specific function and " + "not suppose to be used on omap4\n"); + return 0; +} +static inline int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) +{ + WARN(1, "prm: omap2xxx/omap3xxx specific function and " + "not suppose to be used on omap4\n"); + return 0; +} +static inline int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) +{ + WARN(1, "prm: omap2xxx/omap3xxx specific function and " + "not suppose to be used on omap4\n"); + return 0; +} +static inline int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift) +{ + WARN(1, "prm: omap2xxx/omap3xxx specific function and " + "not suppose to be used on omap4\n"); + return 0; +} +#else /* Power/reset management domain register get/set */ extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx); extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx); @@ -242,6 +302,7 @@ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift); +#endif /* CONFIG_ARCH_OMAP4 */ #endif /* diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index 786d685c09a..b1e0af18a26 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -27,6 +27,7 @@ #include <plat/voltage.h> #include "control.h" +#include "pm.h" static bool sr_enable_on_init; diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index 4e48e786bec..7b7c2683ae7 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -42,6 +42,8 @@ #include "timer-gp.h" +#include <plat/common.h> + /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12 @@ -176,10 +178,14 @@ static void __init omap2_gp_clockevent_init(void) /* * When 32k-timer is enabled, don't use GPTimer for clocksource * instead, just leave default clocksource which uses the 32k - * sync counter. See clocksource setup in see plat-omap/common.c. + * sync counter. See clocksource setup in plat-omap/counter_32k.c */ -static inline void __init omap2_gp_clocksource_init(void) {} +static void __init omap2_gp_clocksource_init(void) +{ + omap_init_clocksource_32k(); +} + #else /* * clocksource diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c index b0c4907ab3c..4067669d96c 100644 --- a/arch/arm/mach-omap2/wd_timer.c +++ b/arch/arm/mach-omap2/wd_timer.c @@ -13,6 +13,8 @@ #include <plat/omap_hwmod.h> +#include "wd_timer.h" + /* * In order to avoid any assumptions from bootloader regarding WDT * settings, WDT module is reset during init. This enables the watchdog diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c index a9ce02b4bf1..c69c180aec7 100644 --- a/arch/arm/mach-pnx4008/irq.c +++ b/arch/arm/mach-pnx4008/irq.c @@ -36,44 +36,44 @@ static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES; -static void pnx4008_mask_irq(unsigned int irq) +static void pnx4008_mask_irq(struct irq_data *d) { - __raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */ + __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */ } -static void pnx4008_unmask_irq(unsigned int irq) +static void pnx4008_unmask_irq(struct irq_data *d) { - __raw_writel(__raw_readl(INTC_ER(irq)) | INTC_BIT(irq), INTC_ER(irq)); /* unmask interrupt */ + __raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq)); /* unmask interrupt */ } -static void pnx4008_mask_ack_irq(unsigned int irq) +static void pnx4008_mask_ack_irq(struct irq_data *d) { - __raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */ - __raw_writel(INTC_BIT(irq), INTC_SR(irq)); /* clear interrupt status */ + __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */ + __raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq)); /* clear interrupt status */ } -static int pnx4008_set_irq_type(unsigned int irq, unsigned int type) +static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type) { switch (type) { case IRQ_TYPE_EDGE_RISING: - __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ - __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */ - set_irq_handler(irq, handle_edge_irq); + __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ + __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */ + set_irq_handler(d->irq, handle_edge_irq); break; case IRQ_TYPE_EDGE_FALLING: - __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ - __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */ - set_irq_handler(irq, handle_edge_irq); + __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ + __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */ + set_irq_handler(d->irq, handle_edge_irq); break; case IRQ_TYPE_LEVEL_LOW: - __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ - __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */ - set_irq_handler(irq, handle_level_irq); + __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ + __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */ + set_irq_handler(d->irq, handle_level_irq); break; case IRQ_TYPE_LEVEL_HIGH: - __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ - __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */ - set_irq_handler(irq, handle_level_irq); + __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ + __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */ + set_irq_handler(d->irq, handle_level_irq); break; /* IRQ_TYPE_EDGE_BOTH is not supported */ @@ -85,10 +85,10 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type) } static struct irq_chip pnx4008_irq_chip = { - .ack = pnx4008_mask_ack_irq, - .mask = pnx4008_mask_irq, - .unmask = pnx4008_unmask_irq, - .set_type = pnx4008_set_irq_type, + .irq_ack = pnx4008_mask_ack_irq, + .irq_mask = pnx4008_mask_irq, + .irq_unmask = pnx4008_unmask_irq, + .irq_set_type = pnx4008_set_irq_type, }; void __init pnx4008_init_irq(void) @@ -99,14 +99,18 @@ void __init pnx4008_init_irq(void) for (i = 0; i < NR_IRQS; i++) { set_irq_flags(i, IRQF_VALID); set_irq_chip(i, &pnx4008_irq_chip); - pnx4008_set_irq_type(i, pnx4008_irq_type[i]); + pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]); } /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */ - pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]); - pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]); - pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]); - pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]); + pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N), + pnx4008_irq_type[SUB1_IRQ_N]); + pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N), + pnx4008_irq_type[SUB2_IRQ_N]); + pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N), + pnx4008_irq_type[SUB1_FIQ_N]); + pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N), + pnx4008_irq_type[SUB2_FIQ_N]); /* mask all others */ __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) | diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index ccb2d0cebcc..a134a1413e0 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -477,25 +477,25 @@ static inline void balloon3_leds_init(void) {} /****************************************************************************** * FPGA IRQ ******************************************************************************/ -static void balloon3_mask_irq(unsigned int irq) +static void balloon3_mask_irq(struct irq_data *d) { - int balloon3_irq = (irq - BALLOON3_IRQ(0)); + int balloon3_irq = (d->irq - BALLOON3_IRQ(0)); balloon3_irq_enabled &= ~(1 << balloon3_irq); __raw_writel(~balloon3_irq_enabled, BALLOON3_INT_CONTROL_REG); } -static void balloon3_unmask_irq(unsigned int irq) +static void balloon3_unmask_irq(struct irq_data *d) { - int balloon3_irq = (irq - BALLOON3_IRQ(0)); + int balloon3_irq = (d->irq - BALLOON3_IRQ(0)); balloon3_irq_enabled |= (1 << balloon3_irq); __raw_writel(~balloon3_irq_enabled, BALLOON3_INT_CONTROL_REG); } static struct irq_chip balloon3_irq_chip = { .name = "FPGA", - .ack = balloon3_mask_irq, - .mask = balloon3_mask_irq, - .unmask = balloon3_unmask_irq, + .irq_ack = balloon3_mask_irq, + .irq_mask = balloon3_mask_irq, + .irq_unmask = balloon3_unmask_irq, }; static void balloon3_irq_handler(unsigned int irq, struct irq_desc *desc) @@ -504,8 +504,13 @@ static void balloon3_irq_handler(unsigned int irq, struct irq_desc *desc) balloon3_irq_enabled; do { /* clear useless edge notification */ - if (desc->chip->ack) - desc->chip->ack(BALLOON3_AUX_NIRQ); + if (desc->irq_data.chip->irq_ack) { + struct irq_data *d; + + d = irq_get_irq_data(BALLOON3_AUX_NIRQ); + desc->irq_data.chip->irq_ack(d); + } + while (pending) { irq = BALLOON3_IRQ(0) + __ffs(pending); generic_handle_irq(irq); diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c index 1b08a34ab23..3f864cd0bd2 100644 --- a/arch/arm/mach-pxa/clock-pxa3xx.c +++ b/arch/arm/mach-pxa/clock-pxa3xx.c @@ -115,7 +115,6 @@ static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk) { unsigned long acsr = ACSR; unsigned long memclkcfg = __raw_readl(MEMCLKCFG); - unsigned int smcfs = (acsr >> 23) & 0x7; return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] / df_clkdiv[(memclkcfg >> 16) & 0x3]; diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index 0f313059977..a2380cd76f8 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c @@ -59,7 +59,7 @@ void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size, static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) { /* clear our parent irq */ - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); it8152_irq_demux(irq, desc); } diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index d6e15f71fc0..f5d91efc296 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -22,7 +22,6 @@ #include <mach/hardware.h> #include <asm/system.h> -#include <asm/pgtable.h> #include <asm/mach/map.h> #include <asm/mach-types.h> diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 6205dc9a2b9..a079d8baa45 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -9,11 +9,13 @@ * published by the Free Software Foundation. */ +struct irq_data; struct sys_timer; extern struct sys_timer pxa_timer; extern void __init pxa_init_irq(int irq_nr, - int (*set_wake)(unsigned int, unsigned int)); + int (*set_wake)(struct irq_data *, + unsigned int)); extern void __init pxa25x_init_irq(void); #ifdef CONFIG_CPU_PXA26x extern void __init pxa26x_init_irq(void); diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 54e91c9e71c..2693e3c3776 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -53,37 +53,48 @@ static inline int cpu_has_ipr(void) return !cpu_is_pxa25x(); } -static void pxa_mask_irq(unsigned int irq) +static inline void __iomem *irq_base(int i) +{ + static unsigned long phys_base[] = { + 0x40d00000, + 0x40d0009c, + 0x40d00130, + }; + + return (void __iomem *)io_p2v(phys_base[i]); +} + +static void pxa_mask_irq(struct irq_data *d) { - void __iomem *base = get_irq_chip_data(irq); + void __iomem *base = irq_data_get_irq_chip_data(d); uint32_t icmr = __raw_readl(base + ICMR); - icmr &= ~(1 << IRQ_BIT(irq)); + icmr &= ~(1 << IRQ_BIT(d->irq)); __raw_writel(icmr, base + ICMR); } -static void pxa_unmask_irq(unsigned int irq) +static void pxa_unmask_irq(struct irq_data *d) { - void __iomem *base = get_irq_chip_data(irq); + void __iomem *base = irq_data_get_irq_chip_data(d); uint32_t icmr = __raw_readl(base + ICMR); - icmr |= 1 << IRQ_BIT(irq); + icmr |= 1 << IRQ_BIT(d->irq); __raw_writel(icmr, base + ICMR); } static struct irq_chip pxa_internal_irq_chip = { .name = "SC", - .ack = pxa_mask_irq, - .mask = pxa_mask_irq, - .unmask = pxa_unmask_irq, + .irq_ack = pxa_mask_irq, + .irq_mask = pxa_mask_irq, + .irq_unmask = pxa_unmask_irq, }; /* * GPIO IRQs for GPIO 0 and 1 */ -static int pxa_set_low_gpio_type(unsigned int irq, unsigned int type) +static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type) { - int gpio = irq - IRQ_GPIO0; + int gpio = d->irq - IRQ_GPIO0; if (__gpio_is_occupied(gpio)) { pr_err("%s failed: GPIO is configured\n", __func__); @@ -103,31 +114,17 @@ static int pxa_set_low_gpio_type(unsigned int irq, unsigned int type) return 0; } -static void pxa_ack_low_gpio(unsigned int irq) -{ - GEDR0 = (1 << (irq - IRQ_GPIO0)); -} - -static void pxa_mask_low_gpio(unsigned int irq) -{ - struct irq_desc *desc = irq_to_desc(irq); - - desc->chip->mask(irq); -} - -static void pxa_unmask_low_gpio(unsigned int irq) +static void pxa_ack_low_gpio(struct irq_data *d) { - struct irq_desc *desc = irq_to_desc(irq); - - desc->chip->unmask(irq); + GEDR0 = (1 << (d->irq - IRQ_GPIO0)); } static struct irq_chip pxa_low_gpio_chip = { .name = "GPIO-l", - .ack = pxa_ack_low_gpio, - .mask = pxa_mask_low_gpio, - .unmask = pxa_unmask_low_gpio, - .set_type = pxa_set_low_gpio_type, + .irq_ack = pxa_ack_low_gpio, + .irq_mask = pxa_mask_irq, + .irq_unmask = pxa_unmask_irq, + .irq_set_type = pxa_set_low_gpio_type, }; static void __init pxa_init_low_gpio_irq(set_wake_t fn) @@ -141,22 +138,12 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn) for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { set_irq_chip(irq, &pxa_low_gpio_chip); + set_irq_chip_data(irq, irq_base(0)); set_irq_handler(irq, handle_edge_irq); set_irq_flags(irq, IRQF_VALID); } - pxa_low_gpio_chip.set_wake = fn; -} - -static inline void __iomem *irq_base(int i) -{ - static unsigned long phys_base[] = { - 0x40d00000, - 0x40d0009c, - 0x40d00130, - }; - - return (void __iomem *)io_p2v(phys_base[i >> 5]); + pxa_low_gpio_chip.irq_set_wake = fn; } void __init pxa_init_irq(int irq_nr, set_wake_t fn) @@ -168,7 +155,7 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) pxa_internal_irq_nr = irq_nr; for (n = 0; n < irq_nr; n += 32) { - void __iomem *base = irq_base(n); + void __iomem *base = irq_base(n >> 5); __raw_writel(0, base + ICMR); /* disable all IRQs */ __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ @@ -188,7 +175,7 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) /* only unmasked interrupts kick us out of idle */ __raw_writel(1, irq_base(0) + ICCR); - pxa_internal_irq_chip.set_wake = fn; + pxa_internal_irq_chip.irq_set_wake = fn; pxa_init_low_gpio_irq(fn); } @@ -200,7 +187,7 @@ static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) { int i; - for (i = 0; i < pxa_internal_irq_nr; i += 32) { + for (i = 0; i < pxa_internal_irq_nr / 32; i++) { void __iomem *base = irq_base(i); saved_icmr[i] = __raw_readl(base + ICMR); @@ -219,14 +206,14 @@ static int pxa_irq_resume(struct sys_device *dev) { int i; - for (i = 0; i < pxa_internal_irq_nr; i += 32) { + for (i = 0; i < pxa_internal_irq_nr / 32; i++) { void __iomem *base = irq_base(i); __raw_writel(saved_icmr[i], base + ICMR); __raw_writel(0, base + ICLR); } - if (!cpu_is_pxa25x()) + if (cpu_has_ipr()) for (i = 0; i < pxa_internal_irq_nr; i++) __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index 8ab62a67780..c9a3e775c2d 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -95,9 +95,9 @@ static unsigned long lpd270_pin_config[] __initdata = { static unsigned int lpd270_irq_enabled; -static void lpd270_mask_irq(unsigned int irq) +static void lpd270_mask_irq(struct irq_data *d) { - int lpd270_irq = irq - LPD270_IRQ(0); + int lpd270_irq = d->irq - LPD270_IRQ(0); __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS); @@ -105,9 +105,9 @@ static void lpd270_mask_irq(unsigned int irq) __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK); } -static void lpd270_unmask_irq(unsigned int irq) +static void lpd270_unmask_irq(struct irq_data *d) { - int lpd270_irq = irq - LPD270_IRQ(0); + int lpd270_irq = d->irq - LPD270_IRQ(0); lpd270_irq_enabled |= 1 << lpd270_irq; __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK); @@ -115,9 +115,9 @@ static void lpd270_unmask_irq(unsigned int irq) static struct irq_chip lpd270_irq_chip = { .name = "CPLD", - .ack = lpd270_mask_irq, - .mask = lpd270_mask_irq, - .unmask = lpd270_unmask_irq, + .irq_ack = lpd270_mask_irq, + .irq_mask = lpd270_mask_irq, + .irq_unmask = lpd270_unmask_irq, }; static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc) @@ -126,7 +126,8 @@ static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc) pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled; do { - desc->chip->ack(irq); /* clear useless edge notification */ + /* clear useless edge notification */ + desc->irq_data.chip->irq_ack(&desc->irq_data); if (likely(pending)) { irq = LPD270_IRQ(0) + __ffs(pending); generic_handle_irq(irq); diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 3072dbea5c1..dca20de306b 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -122,15 +122,15 @@ EXPORT_SYMBOL(lubbock_set_misc_wr); static unsigned long lubbock_irq_enabled; -static void lubbock_mask_irq(unsigned int irq) +static void lubbock_mask_irq(struct irq_data *d) { - int lubbock_irq = (irq - LUBBOCK_IRQ(0)); + int lubbock_irq = (d->irq - LUBBOCK_IRQ(0)); LUB_IRQ_MASK_EN = (lubbock_irq_enabled &= ~(1 << lubbock_irq)); } -static void lubbock_unmask_irq(unsigned int irq) +static void lubbock_unmask_irq(struct irq_data *d) { - int lubbock_irq = (irq - LUBBOCK_IRQ(0)); + int lubbock_irq = (d->irq - LUBBOCK_IRQ(0)); /* the irq can be acknowledged only if deasserted, so it's done here */ LUB_IRQ_SET_CLR &= ~(1 << lubbock_irq); LUB_IRQ_MASK_EN = (lubbock_irq_enabled |= (1 << lubbock_irq)); @@ -138,16 +138,17 @@ static void lubbock_unmask_irq(unsigned int irq) static struct irq_chip lubbock_irq_chip = { .name = "FPGA", - .ack = lubbock_mask_irq, - .mask = lubbock_mask_irq, - .unmask = lubbock_unmask_irq, + .irq_ack = lubbock_mask_irq, + .irq_mask = lubbock_mask_irq, + .irq_unmask = lubbock_unmask_irq, }; static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc) { unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled; do { - desc->chip->ack(irq); /* clear our parent irq */ + /* clear our parent irq */ + desc->irq_data.chip->irq_ack(&desc->irq_data); if (likely(pending)) { irq = LUBBOCK_IRQ(0) + __ffs(pending); generic_handle_irq(irq); diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 740c03590e3..d4b6f2375f2 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -123,15 +123,15 @@ static unsigned long mainstone_pin_config[] = { static unsigned long mainstone_irq_enabled; -static void mainstone_mask_irq(unsigned int irq) +static void mainstone_mask_irq(struct irq_data *d) { - int mainstone_irq = (irq - MAINSTONE_IRQ(0)); + int mainstone_irq = (d->irq - MAINSTONE_IRQ(0)); MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq)); } -static void mainstone_unmask_irq(unsigned int irq) +static void mainstone_unmask_irq(struct irq_data *d) { - int mainstone_irq = (irq - MAINSTONE_IRQ(0)); + int mainstone_irq = (d->irq - MAINSTONE_IRQ(0)); /* the irq can be acknowledged only if deasserted, so it's done here */ MST_INTSETCLR &= ~(1 << mainstone_irq); MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq)); @@ -139,16 +139,17 @@ static void mainstone_unmask_irq(unsigned int irq) static struct irq_chip mainstone_irq_chip = { .name = "FPGA", - .ack = mainstone_mask_irq, - .mask = mainstone_mask_irq, - .unmask = mainstone_unmask_irq, + .irq_ack = mainstone_mask_irq, + .irq_mask = mainstone_mask_irq, + .irq_unmask = mainstone_unmask_irq, }; static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc) { unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled; do { - desc->chip->ack(irq); /* clear useless edge notification */ + /* clear useless edge notification */ + desc->irq_data.chip->irq_ack(&desc->irq_data); if (likely(pending)) { irq = MAINSTONE_IRQ(0) + __ffs(pending); generic_handle_irq(irq); diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index f33647a8e0b..90820faa711 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -241,23 +241,23 @@ static struct platform_device pcm990_backlight_device = { static unsigned long pcm990_irq_enabled; -static void pcm990_mask_ack_irq(unsigned int irq) +static void pcm990_mask_ack_irq(struct irq_data *d) { - int pcm990_irq = (irq - PCM027_IRQ(0)); + int pcm990_irq = (d->irq - PCM027_IRQ(0)); PCM990_INTMSKENA = (pcm990_irq_enabled &= ~(1 << pcm990_irq)); } -static void pcm990_unmask_irq(unsigned int irq) +static void pcm990_unmask_irq(struct irq_data *d) { - int pcm990_irq = (irq - PCM027_IRQ(0)); + int pcm990_irq = (d->irq - PCM027_IRQ(0)); /* the irq can be acknowledged only if deasserted, so it's done here */ PCM990_INTSETCLR |= 1 << pcm990_irq; PCM990_INTMSKENA = (pcm990_irq_enabled |= (1 << pcm990_irq)); } static struct irq_chip pcm990_irq_chip = { - .mask_ack = pcm990_mask_ack_irq, - .unmask = pcm990_unmask_irq, + .irq_mask_ack = pcm990_mask_ack_irq, + .irq_unmask = pcm990_unmask_irq, }; static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc) @@ -265,7 +265,8 @@ static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc) unsigned long pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled; do { - desc->chip->ack(irq); /* clear our parent IRQ */ + /* clear our parent IRQ */ + desc->irq_data.chip->irq_ack(&desc->irq_data); if (likely(pending)) { irq = PCM027_IRQ(0) + __ffs(pending); generic_handle_irq(irq); diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 3f5241c8489..fbc5b775f89 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -22,6 +22,7 @@ #include <linux/platform_device.h> #include <linux/suspend.h> #include <linux/sysdev.h> +#include <linux/irq.h> #include <asm/mach/map.h> #include <mach/hardware.h> @@ -282,15 +283,15 @@ static inline void pxa25x_init_pm(void) {} /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm */ -static int pxa25x_set_wake(unsigned int irq, unsigned int on) +static int pxa25x_set_wake(struct irq_data *d, unsigned int on) { - int gpio = IRQ_TO_GPIO(irq); + int gpio = IRQ_TO_GPIO(d->irq); uint32_t mask = 0; if (gpio >= 0 && gpio < 85) return gpio_set_wake(gpio, on); - if (irq == IRQ_RTCAlrm) { + if (d->irq == IRQ_RTCAlrm) { mask = PWER_RTC; goto set_pwer; } diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index b2130b7a7b5..987301ff4c3 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -18,6 +18,7 @@ #include <linux/platform_device.h> #include <linux/sysdev.h> #include <linux/io.h> +#include <linux/irq.h> #include <asm/mach/map.h> #include <mach/hardware.h> @@ -343,18 +344,18 @@ static inline void pxa27x_init_pm(void) {} /* PXA27x: Various gpios can issue wakeup events. This logic only * handles the simple cases, not the WEMUX2 and WEMUX3 options */ -static int pxa27x_set_wake(unsigned int irq, unsigned int on) +static int pxa27x_set_wake(struct irq_data *d, unsigned int on) { - int gpio = IRQ_TO_GPIO(irq); + int gpio = IRQ_TO_GPIO(d->irq); uint32_t mask; if (gpio >= 0 && gpio < 128) return gpio_set_wake(gpio, on); - if (irq == IRQ_KEYPAD) + if (d->irq == IRQ_KEYPAD) return keypad_set_wake(on); - switch (irq) { + switch (d->irq) { case IRQ_RTCAlrm: mask = PWER_RTC; break; diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index e14818f5d95..a7a19e1cd64 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -229,11 +229,11 @@ static void __init pxa3xx_init_pm(void) pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; } -static int pxa3xx_set_wake(unsigned int irq, unsigned int on) +static int pxa3xx_set_wake(struct irq_data *d, unsigned int on) { unsigned long flags, mask = 0; - switch (irq) { + switch (d->irq) { case IRQ_SSP3: mask = ADXER_MFP_WSSP3; break; @@ -322,40 +322,40 @@ static inline void pxa3xx_init_pm(void) {} #define pxa3xx_set_wake NULL #endif -static void pxa_ack_ext_wakeup(unsigned int irq) +static void pxa_ack_ext_wakeup(struct irq_data *d) { - PECR |= PECR_IS(irq - IRQ_WAKEUP0); + PECR |= PECR_IS(d->irq - IRQ_WAKEUP0); } -static void pxa_mask_ext_wakeup(unsigned int irq) +static void pxa_mask_ext_wakeup(struct irq_data *d) { - ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f)); - PECR &= ~PECR_IE(irq - IRQ_WAKEUP0); + ICMR2 &= ~(1 << ((d->irq - PXA_IRQ(0)) & 0x1f)); + PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); } -static void pxa_unmask_ext_wakeup(unsigned int irq) +static void pxa_unmask_ext_wakeup(struct irq_data *d) { - ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f); - PECR |= PECR_IE(irq - IRQ_WAKEUP0); + ICMR2 |= 1 << ((d->irq - PXA_IRQ(0)) & 0x1f); + PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); } -static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type) +static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type) { if (flow_type & IRQ_TYPE_EDGE_RISING) - PWER |= 1 << (irq - IRQ_WAKEUP0); + PWER |= 1 << (d->irq - IRQ_WAKEUP0); if (flow_type & IRQ_TYPE_EDGE_FALLING) - PWER |= 1 << (irq - IRQ_WAKEUP0 + 2); + PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2); return 0; } static struct irq_chip pxa_ext_wakeup_chip = { .name = "WAKEUP", - .ack = pxa_ack_ext_wakeup, - .mask = pxa_mask_ext_wakeup, - .unmask = pxa_unmask_ext_wakeup, - .set_type = pxa_set_ext_wakeup_type, + .irq_ack = pxa_ack_ext_wakeup, + .irq_mask = pxa_mask_ext_wakeup, + .irq_unmask = pxa_unmask_ext_wakeup, + .irq_set_type = pxa_set_ext_wakeup_type, }; static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) @@ -368,7 +368,7 @@ static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) set_irq_flags(irq, IRQF_VALID); } - pxa_ext_wakeup_chip.set_wake = fn; + pxa_ext_wakeup_chip.irq_set_wake = fn; } void __init pxa3xx_init_irq(void) diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 0bc938729c4..b49a2c21124 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -25,6 +25,7 @@ #include <linux/spi/corgi_lcd.h> #include <linux/spi/pxa2xx_spi.h> #include <linux/mtd/sharpsl.h> +#include <linux/mtd/physmap.h> #include <linux/input/matrix_keypad.h> #include <linux/regulator/machine.h> #include <linux/io.h> diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index de69b203afa..49eeeab2368 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -249,9 +249,9 @@ static inline int viper_bit_to_irq(int bit) return viper_isa_irqs[bit] + PXA_ISA_IRQ(0); } -static void viper_ack_irq(unsigned int irq) +static void viper_ack_irq(struct irq_data *d) { - int viper_irq = viper_irq_to_bitmask(irq); + int viper_irq = viper_irq_to_bitmask(d->irq); if (viper_irq & 0xff) VIPER_LO_IRQ_STATUS = viper_irq; @@ -259,14 +259,14 @@ static void viper_ack_irq(unsigned int irq) VIPER_HI_IRQ_STATUS = (viper_irq >> 8); } -static void viper_mask_irq(unsigned int irq) +static void viper_mask_irq(struct irq_data *d) { - viper_irq_enabled_mask &= ~(viper_irq_to_bitmask(irq)); + viper_irq_enabled_mask &= ~(viper_irq_to_bitmask(d->irq)); } -static void viper_unmask_irq(unsigned int irq) +static void viper_unmask_irq(struct irq_data *d) { - viper_irq_enabled_mask |= viper_irq_to_bitmask(irq); + viper_irq_enabled_mask |= viper_irq_to_bitmask(d->irq); } static inline unsigned long viper_irq_pending(void) @@ -283,7 +283,7 @@ static void viper_irq_handler(unsigned int irq, struct irq_desc *desc) do { /* we're in a chained irq handler, * so ack the interrupt by hand */ - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); if (likely(pending)) { irq = viper_bit_to_irq(__ffs(pending)); @@ -294,10 +294,10 @@ static void viper_irq_handler(unsigned int irq, struct irq_desc *desc) } static struct irq_chip viper_irq_chip = { - .name = "ISA", - .ack = viper_ack_irq, - .mask = viper_mask_irq, - .unmask = viper_unmask_irq + .name = "ISA", + .irq_ack = viper_ack_irq, + .irq_mask = viper_mask_irq, + .irq_unmask = viper_unmask_irq }; static void __init viper_init_irq(void) diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index bf034c7670d..f4b053b3581 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -83,19 +83,19 @@ static inline int zeus_bit_to_irq(int bit) return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0); } -static void zeus_ack_irq(unsigned int irq) +static void zeus_ack_irq(struct irq_data *d) { - __raw_writew(zeus_irq_to_bitmask(irq), ZEUS_CPLD_ISA_IRQ); + __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ); } -static void zeus_mask_irq(unsigned int irq) +static void zeus_mask_irq(struct irq_data *d) { - zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(irq)); + zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq)); } -static void zeus_unmask_irq(unsigned int irq) +static void zeus_unmask_irq(struct irq_data *d) { - zeus_irq_enabled_mask |= zeus_irq_to_bitmask(irq); + zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq); } static inline unsigned long zeus_irq_pending(void) @@ -111,7 +111,7 @@ static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc) do { /* we're in a chained irq handler, * so ack the interrupt by hand */ - desc->chip->ack(gpio_to_irq(ZEUS_ISA_GPIO)); + desc->irq_data.chip->irq_ack(&desc->irq_data); if (likely(pending)) { irq = zeus_bit_to_irq(__ffs(pending)); @@ -122,10 +122,10 @@ static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc) } static struct irq_chip zeus_irq_chip = { - .name = "ISA", - .ack = zeus_ack_irq, - .mask = zeus_mask_irq, - .unmask = zeus_unmask_irq, + .name = "ISA", + .irq_ack = zeus_ack_irq, + .irq_mask = zeus_mask_irq, + .irq_unmask = zeus_unmask_irq, }; static void __init zeus_init_irq(void) @@ -830,8 +830,8 @@ static void __init zeus_init(void) pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f)); /* Fix timings for dm9000s (CS1/CS2)*/ - msc0 = __raw_readl(MSC0) & 0x0000ffff | (dm9000_msc << 16); - msc1 = __raw_readl(MSC1) & 0xffff0000 | dm9000_msc; + msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16); + msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc; __raw_writel(msc0, MSC0); __raw_writel(msc1, MSC1); diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c index 9dd15d679c5..d29cd9b737f 100644 --- a/arch/arm/mach-rpc/irq.c +++ b/arch/arm/mach-rpc/irq.c @@ -6,110 +6,110 @@ #include <asm/hardware/iomd.h> #include <asm/irq.h> -static void iomd_ack_irq_a(unsigned int irq) +static void iomd_ack_irq_a(struct irq_data *d) { unsigned int val, mask; - mask = 1 << irq; + mask = 1 << d->irq; val = iomd_readb(IOMD_IRQMASKA); iomd_writeb(val & ~mask, IOMD_IRQMASKA); iomd_writeb(mask, IOMD_IRQCLRA); } -static void iomd_mask_irq_a(unsigned int irq) +static void iomd_mask_irq_a(struct irq_data *d) { unsigned int val, mask; - mask = 1 << irq; + mask = 1 << d->irq; val = iomd_readb(IOMD_IRQMASKA); iomd_writeb(val & ~mask, IOMD_IRQMASKA); } -static void iomd_unmask_irq_a(unsigned int irq) +static void iomd_unmask_irq_a(struct irq_data *d) { unsigned int val, mask; - mask = 1 << irq; + mask = 1 << d->irq; val = iomd_readb(IOMD_IRQMASKA); iomd_writeb(val | mask, IOMD_IRQMASKA); } static struct irq_chip iomd_a_chip = { - .ack = iomd_ack_irq_a, - .mask = iomd_mask_irq_a, - .unmask = iomd_unmask_irq_a, + .irq_ack = iomd_ack_irq_a, + .irq_mask = iomd_mask_irq_a, + .irq_unmask = iomd_unmask_irq_a, }; -static void iomd_mask_irq_b(unsigned int irq) +static void iomd_mask_irq_b(struct irq_data *d) { unsigned int val, mask; - mask = 1 << (irq & 7); + mask = 1 << (d->irq & 7); val = iomd_readb(IOMD_IRQMASKB); iomd_writeb(val & ~mask, IOMD_IRQMASKB); } -static void iomd_unmask_irq_b(unsigned int irq) +static void iomd_unmask_irq_b(struct irq_data *d) { unsigned int val, mask; - mask = 1 << (irq & 7); + mask = 1 << (d->irq & 7); val = iomd_readb(IOMD_IRQMASKB); iomd_writeb(val | mask, IOMD_IRQMASKB); } static struct irq_chip iomd_b_chip = { - .ack = iomd_mask_irq_b, - .mask = iomd_mask_irq_b, - .unmask = iomd_unmask_irq_b, + .irq_ack = iomd_mask_irq_b, + .irq_mask = iomd_mask_irq_b, + .irq_unmask = iomd_unmask_irq_b, }; -static void iomd_mask_irq_dma(unsigned int irq) +static void iomd_mask_irq_dma(struct irq_data *d) { unsigned int val, mask; - mask = 1 << (irq & 7); + mask = 1 << (d->irq & 7); val = iomd_readb(IOMD_DMAMASK); iomd_writeb(val & ~mask, IOMD_DMAMASK); } -static void iomd_unmask_irq_dma(unsigned int irq) +static void iomd_unmask_irq_dma(struct irq_data *d) { unsigned int val, mask; - mask = 1 << (irq & 7); + mask = 1 << (d->irq & 7); val = iomd_readb(IOMD_DMAMASK); iomd_writeb(val | mask, IOMD_DMAMASK); } static struct irq_chip iomd_dma_chip = { - .ack = iomd_mask_irq_dma, - .mask = iomd_mask_irq_dma, - .unmask = iomd_unmask_irq_dma, + .irq_ack = iomd_mask_irq_dma, + .irq_mask = iomd_mask_irq_dma, + .irq_unmask = iomd_unmask_irq_dma, }; -static void iomd_mask_irq_fiq(unsigned int irq) +static void iomd_mask_irq_fiq(struct irq_data *d) { unsigned int val, mask; - mask = 1 << (irq & 7); + mask = 1 << (d->irq & 7); val = iomd_readb(IOMD_FIQMASK); iomd_writeb(val & ~mask, IOMD_FIQMASK); } -static void iomd_unmask_irq_fiq(unsigned int irq) +static void iomd_unmask_irq_fiq(struct irq_data *d) { unsigned int val, mask; - mask = 1 << (irq & 7); + mask = 1 << (d->irq & 7); val = iomd_readb(IOMD_FIQMASK); iomd_writeb(val | mask, IOMD_FIQMASK); } static struct irq_chip iomd_fiq_chip = { - .ack = iomd_mask_irq_fiq, - .mask = iomd_mask_irq_fiq, - .unmask = iomd_unmask_irq_fiq, + .irq_ack = iomd_mask_irq_fiq, + .irq_mask = iomd_mask_irq_fiq, + .irq_unmask = iomd_unmask_irq_fiq, }; void __init rpc_init_irq(void) diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c index 217b102866d..606cb6b1cc4 100644 --- a/arch/arm/mach-s3c2410/bast-irq.c +++ b/arch/arm/mach-s3c2410/bast-irq.c @@ -75,38 +75,38 @@ static unsigned char bast_pc104_irqmasks[] = { static unsigned char bast_pc104_irqs[] = { 3, 5, 7, 10 }; static void -bast_pc104_mask(unsigned int irqno) +bast_pc104_mask(struct irq_data *data) { unsigned long temp; temp = __raw_readb(BAST_VA_PC104_IRQMASK); - temp &= ~bast_pc104_irqmasks[irqno]; + temp &= ~bast_pc104_irqmasks[data->irq]; __raw_writeb(temp, BAST_VA_PC104_IRQMASK); } static void -bast_pc104_maskack(unsigned int irqno) +bast_pc104_maskack(struct irq_data *data) { struct irq_desc *desc = irq_desc + IRQ_ISA; - bast_pc104_mask(irqno); - desc->chip->ack(IRQ_ISA); + bast_pc104_mask(data); + desc->irq_data.chip->irq_ack(&desc->irq_data); } static void -bast_pc104_unmask(unsigned int irqno) +bast_pc104_unmask(struct irq_data *data) { unsigned long temp; temp = __raw_readb(BAST_VA_PC104_IRQMASK); - temp |= bast_pc104_irqmasks[irqno]; + temp |= bast_pc104_irqmasks[data->irq]; __raw_writeb(temp, BAST_VA_PC104_IRQMASK); } static struct irq_chip bast_pc104_chip = { - .mask = bast_pc104_mask, - .unmask = bast_pc104_unmask, - .ack = bast_pc104_maskack + .irq_mask = bast_pc104_mask, + .irq_unmask = bast_pc104_unmask, + .irq_ack = bast_pc104_maskack }; static void @@ -123,7 +123,7 @@ bast_irq_pc104_demux(unsigned int irq, /* ack if we get an irq with nothing (ie, startup) */ desc = irq_desc + IRQ_ISA; - desc->chip->ack(IRQ_ISA); + desc->irq_data.chip->irq_ack(&desc->irq_data); } else { /* handle the IRQ */ diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h index 11bb0f08fe6..e5a68ea1311 100644 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h @@ -152,8 +152,8 @@ #define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */ -#define IRQ_HSMMC0 IRQ_S3C2443_HSMMC -#define IRQ_HSMMC1 IRQ_S3C2416_HSMMC0 +#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0 +#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC #define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) #define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index cd3983ad416..25bbf5a942d 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h @@ -112,8 +112,8 @@ #define S3C_PA_IIC S3C2410_PA_IIC #define S3C_PA_UART S3C24XX_PA_UART #define S3C_PA_USBHOST S3C2410_PA_USBHOST -#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC -#define S3C_PA_HSMMC1 S3C2416_PA_HSMMC0 +#define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0 +#define S3C_PA_HSMMC1 S3C2443_PA_HSMMC #define S3C_PA_WDT S3C2410_PA_WATCHDOG #define S3C_PA_NAND S3C24XX_PA_NAND diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h index 101aeea2231..44494a56e68 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h @@ -86,6 +86,7 @@ #define S3C2443_HCLKCON_LCDC (1<<9) #define S3C2443_HCLKCON_USBH (1<<11) #define S3C2443_HCLKCON_USBD (1<<12) +#define S3C2416_HCLKCON_HSMMC0 (1<<15) #define S3C2443_HCLKCON_HSMMC (1<<16) #define S3C2443_HCLKCON_CFC (1<<17) #define S3C2443_HCLKCON_SSMC (1<<18) diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c index 6000ca9d181..eddb52ba5b6 100644 --- a/arch/arm/mach-s3c2412/irq.c +++ b/arch/arm/mach-s3c2412/irq.c @@ -49,9 +49,9 @@ */ static void -s3c2412_irq_mask(unsigned int irqno) +s3c2412_irq_mask(struct irq_data *data) { - unsigned long bitval = 1UL << (irqno - IRQ_EINT0); + unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); unsigned long mask; mask = __raw_readl(S3C2410_INTMSK); @@ -62,9 +62,9 @@ s3c2412_irq_mask(unsigned int irqno) } static inline void -s3c2412_irq_ack(unsigned int irqno) +s3c2412_irq_ack(struct irq_data *data) { - unsigned long bitval = 1UL << (irqno - IRQ_EINT0); + unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); __raw_writel(bitval, S3C2412_EINTPEND); __raw_writel(bitval, S3C2410_SRCPND); @@ -72,9 +72,9 @@ s3c2412_irq_ack(unsigned int irqno) } static inline void -s3c2412_irq_maskack(unsigned int irqno) +s3c2412_irq_maskack(struct irq_data *data) { - unsigned long bitval = 1UL << (irqno - IRQ_EINT0); + unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); unsigned long mask; mask = __raw_readl(S3C2410_INTMSK); @@ -89,9 +89,9 @@ s3c2412_irq_maskack(unsigned int irqno) } static void -s3c2412_irq_unmask(unsigned int irqno) +s3c2412_irq_unmask(struct irq_data *data) { - unsigned long bitval = 1UL << (irqno - IRQ_EINT0); + unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); unsigned long mask; mask = __raw_readl(S3C2412_EINTMASK); @@ -102,11 +102,11 @@ s3c2412_irq_unmask(unsigned int irqno) } static struct irq_chip s3c2412_irq_eint0t4 = { - .ack = s3c2412_irq_ack, - .mask = s3c2412_irq_mask, - .unmask = s3c2412_irq_unmask, - .set_wake = s3c_irq_wake, - .set_type = s3c_irqext_type, + .irq_ack = s3c2412_irq_ack, + .irq_mask = s3c2412_irq_mask, + .irq_unmask = s3c2412_irq_unmask, + .irq_set_wake = s3c_irq_wake, + .irq_set_type = s3c_irqext_type, }; #define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0))) @@ -132,29 +132,29 @@ static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc) #define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0)) #define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF) -static void s3c2412_irq_cfsdi_mask(unsigned int irqno) +static void s3c2412_irq_cfsdi_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_CFSDI, SUBMSK_CFSDI); + s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI); } -static void s3c2412_irq_cfsdi_unmask(unsigned int irqno) +static void s3c2412_irq_cfsdi_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_CFSDI); + s3c_irqsub_unmask(data->irq, INTMSK_CFSDI); } -static void s3c2412_irq_cfsdi_ack(unsigned int irqno) +static void s3c2412_irq_cfsdi_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_CFSDI, SUBMSK_CFSDI); + s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI); } static struct irq_chip s3c2412_irq_cfsdi = { .name = "s3c2412-cfsdi", - .ack = s3c2412_irq_cfsdi_ack, - .mask = s3c2412_irq_cfsdi_mask, - .unmask = s3c2412_irq_cfsdi_unmask, + .irq_ack = s3c2412_irq_cfsdi_ack, + .irq_mask = s3c2412_irq_cfsdi_mask, + .irq_unmask = s3c2412_irq_cfsdi_unmask, }; -static int s3c2412_irq_rtc_wake(unsigned int irqno, unsigned int state) +static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state) { unsigned long pwrcfg; @@ -165,7 +165,7 @@ static int s3c2412_irq_rtc_wake(unsigned int irqno, unsigned int state) pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ; __raw_writel(pwrcfg, S3C2412_PWRCFG); - return s3c_irq_chip.set_wake(irqno, state); + return s3c_irq_chip.irq_set_wake(data, state); } static struct irq_chip s3c2412_irq_rtc_chip; @@ -193,7 +193,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev) /* change RTC IRQ's set wake method */ s3c2412_irq_rtc_chip = s3c_irq_chip; - s3c2412_irq_rtc_chip.set_wake = s3c2412_irq_rtc_wake; + s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake; set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig index df8d14974c9..69b48a7d1db 100644 --- a/arch/arm/mach-s3c2416/Kconfig +++ b/arch/arm/mach-s3c2416/Kconfig @@ -31,6 +31,17 @@ config S3C2416_PM help Internal config node to apply S3C2416 power management +config S3C2416_SETUP_SDHCI + bool + select S3C2416_SETUP_SDHCI_GPIO + help + Internal helper functions for S3C2416 based SDHCI systems + +config S3C2416_SETUP_SDHCI_GPIO + bool + help + Common setup code for SDHCI gpio. + menu "S3C2416 Machines" config MACH_SMDK2416 @@ -42,6 +53,7 @@ config MACH_SMDK2416 select S3C_DEV_HSMMC1 select S3C_DEV_NAND select S3C_DEV_USB_HOST + select S3C2416_SETUP_SDHCI select S3C2416_PM if PM help Say Y here if you are using an SMDK2416 diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile index ef038d62ffd..7b805b279ca 100644 --- a/arch/arm/mach-s3c2416/Makefile +++ b/arch/arm/mach-s3c2416/Makefile @@ -14,6 +14,10 @@ obj-$(CONFIG_CPU_S3C2416) += irq.o obj-$(CONFIG_S3C2416_PM) += pm.o #obj-$(CONFIG_S3C2416_DMA) += dma.o +# Device setup +obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o +obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o + # Machine support obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c index 7ccf5a2a2bf..3b02d8506e2 100644 --- a/arch/arm/mach-s3c2416/clock.c +++ b/arch/arm/mach-s3c2416/clock.c @@ -38,12 +38,11 @@ static unsigned int armdiv[8] = { [7] = 8, }; -/* ID to hardware numbering, 0 is HSMMC1, 1 is HSMMC0 */ static struct clksrc_clk hsmmc_div[] = { [0] = { .clk = { .name = "hsmmc-div", - .id = 1, + .id = 0, .parent = &clk_esysclk.clk, }, .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 }, @@ -51,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = { [1] = { .clk = { .name = "hsmmc-div", - .id = 0, + .id = 1, .parent = &clk_esysclk.clk, }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, @@ -61,7 +60,7 @@ static struct clksrc_clk hsmmc_div[] = { static struct clksrc_clk hsmmc_mux[] = { [0] = { .clk = { - .id = 1, + .id = 0, .name = "hsmmc-if", .ctrlbit = (1 << 6), .enable = s3c2443_clkcon_enable_s, @@ -77,7 +76,7 @@ static struct clksrc_clk hsmmc_mux[] = { }, [1] = { .clk = { - .id = 0, + .id = 1, .name = "hsmmc-if", .ctrlbit = (1 << 12), .enable = s3c2443_clkcon_enable_s, @@ -93,6 +92,13 @@ static struct clksrc_clk hsmmc_mux[] = { }, }; +static struct clk hsmmc0_clk = { + .name = "hsmmc", + .id = 0, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2416_HCLKCON_HSMMC0, +}; static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0) { @@ -130,6 +136,8 @@ void __init s3c2416_init_clocks(int xtal) for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_register_clksrc(clksrcs[ptr], 1); + s3c24xx_register_clock(&hsmmc0_clk); + s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c index 00174daf152..680fe386aca 100644 --- a/arch/arm/mach-s3c2416/irq.c +++ b/arch/arm/mach-s3c2416/irq.c @@ -77,28 +77,27 @@ static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc) #define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0)) #define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97) -static void s3c2416_irq_wdtac97_mask(unsigned int irqno) +static void s3c2416_irq_wdtac97_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97); + s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97); } -static void s3c2416_irq_wdtac97_unmask(unsigned int irqno) +static void s3c2416_irq_wdtac97_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_WDTAC97); + s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97); } -static void s3c2416_irq_wdtac97_ack(unsigned int irqno) +static void s3c2416_irq_wdtac97_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97); + s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97); } static struct irq_chip s3c2416_irq_wdtac97 = { - .mask = s3c2416_irq_wdtac97_mask, - .unmask = s3c2416_irq_wdtac97_unmask, - .ack = s3c2416_irq_wdtac97_ack, + .irq_mask = s3c2416_irq_wdtac97_mask, + .irq_unmask = s3c2416_irq_wdtac97_unmask, + .irq_ack = s3c2416_irq_wdtac97_ack, }; - /* LCD sub interrupts */ static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc) @@ -109,28 +108,27 @@ static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc) #define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0)) #define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4) -static void s3c2416_irq_lcd_mask(unsigned int irqno) +static void s3c2416_irq_lcd_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD); + s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD); } -static void s3c2416_irq_lcd_unmask(unsigned int irqno) +static void s3c2416_irq_lcd_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_LCD); + s3c_irqsub_unmask(data->irq, INTMSK_LCD); } -static void s3c2416_irq_lcd_ack(unsigned int irqno) +static void s3c2416_irq_lcd_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD); + s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD); } static struct irq_chip s3c2416_irq_lcd = { - .mask = s3c2416_irq_lcd_mask, - .unmask = s3c2416_irq_lcd_unmask, - .ack = s3c2416_irq_lcd_ack, + .irq_mask = s3c2416_irq_lcd_mask, + .irq_unmask = s3c2416_irq_lcd_unmask, + .irq_ack = s3c2416_irq_lcd_ack, }; - /* DMA sub interrupts */ static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc) @@ -142,28 +140,27 @@ static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc) #define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5) -static void s3c2416_irq_dma_mask(unsigned int irqno) +static void s3c2416_irq_dma_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA); + s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA); } -static void s3c2416_irq_dma_unmask(unsigned int irqno) +static void s3c2416_irq_dma_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_DMA); + s3c_irqsub_unmask(data->irq, INTMSK_DMA); } -static void s3c2416_irq_dma_ack(unsigned int irqno) +static void s3c2416_irq_dma_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA); + s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA); } static struct irq_chip s3c2416_irq_dma = { - .mask = s3c2416_irq_dma_mask, - .unmask = s3c2416_irq_dma_unmask, - .ack = s3c2416_irq_dma_ack, + .irq_mask = s3c2416_irq_dma_mask, + .irq_unmask = s3c2416_irq_dma_unmask, + .irq_ack = s3c2416_irq_dma_ack, }; - /* UART3 sub interrupts */ static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc) @@ -174,28 +171,27 @@ static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc) #define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0)) #define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0))) -static void s3c2416_irq_uart3_mask(unsigned int irqno) +static void s3c2416_irq_uart3_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3); + s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3); } -static void s3c2416_irq_uart3_unmask(unsigned int irqno) +static void s3c2416_irq_uart3_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_UART3); + s3c_irqsub_unmask(data->irq, INTMSK_UART3); } -static void s3c2416_irq_uart3_ack(unsigned int irqno) +static void s3c2416_irq_uart3_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3); + s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3); } static struct irq_chip s3c2416_irq_uart3 = { - .mask = s3c2416_irq_uart3_mask, - .unmask = s3c2416_irq_uart3_unmask, - .ack = s3c2416_irq_uart3_ack, + .irq_mask = s3c2416_irq_uart3_mask, + .irq_unmask = s3c2416_irq_uart3_unmask, + .irq_ack = s3c2416_irq_uart3_ack, }; - /* IRQ initialisation code */ static int __init s3c2416_add_sub(unsigned int base, diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c index 7fc366476d7..3f83177246c 100644 --- a/arch/arm/mach-s3c2416/mach-smdk2416.c +++ b/arch/arm/mach-s3c2416/mach-smdk2416.c @@ -46,6 +46,7 @@ #include <plat/devs.h> #include <plat/cpu.h> #include <plat/nand.h> +#include <plat/sdhci.h> #include <plat/regs-fb-v4.h> #include <plat/fb.h> @@ -110,6 +111,13 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON | 0x50, .ufcon = UFCON, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, } }; @@ -159,6 +167,18 @@ static struct s3c_fb_platdata smdk2416_fb_platdata = { .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, }; +static struct s3c_sdhci_platdata smdk2416_hsmmc0_pdata __initdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S3C2410_GPF(1), + .ext_cd_gpio_invert = 1, +}; + +static struct s3c_sdhci_platdata smdk2416_hsmmc1_pdata __initdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_NONE, +}; + static struct platform_device *smdk2416_devices[] __initdata = { &s3c_device_fb, &s3c_device_wdt, @@ -180,6 +200,9 @@ static void __init smdk2416_machine_init(void) s3c_i2c0_set_platdata(NULL); s3c_fb_set_platdata(&smdk2416_fb_platdata); + s3c_sdhci0_set_platdata(&smdk2416_hsmmc0_pdata); + s3c_sdhci1_set_platdata(&smdk2416_hsmmc1_pdata); + gpio_request(S3C2410_GPB(4), "USBHost Power"); gpio_direction_output(S3C2410_GPB(4), 1); diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c index 63f39cdc097..ba7fd873743 100644 --- a/arch/arm/mach-s3c2416/s3c2416.c +++ b/arch/arm/mach-s3c2416/s3c2416.c @@ -53,6 +53,7 @@ #include <plat/s3c2416.h> #include <plat/devs.h> #include <plat/cpu.h> +#include <plat/sdhci.h> #include <plat/iic-core.h> #include <plat/fb-core.h> @@ -115,6 +116,10 @@ void __init s3c2416_map_io(void) s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown; s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown; + /* initialize device information early */ + s3c2416_default_sdhci0(); + s3c2416_default_sdhci1(); + iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc)); } diff --git a/arch/arm/mach-s3c2416/setup-sdhci-gpio.c b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c new file mode 100644 index 00000000000..f65cb3ef16c --- /dev/null +++ b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c @@ -0,0 +1,34 @@ +/* linux/arch/arm/plat-s3c2416/setup-sdhci-gpio.c + * + * Copyright 2010 Promwad Innovation Company + * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> + * + * S3C2416 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) + * + * Based on mach-s3c64xx/setup-sdhci-gpio.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/gpio.h> + +#include <mach/regs-gpio.h> +#include <plat/gpio-cfg.h> + +void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) +{ + s3c_gpio_cfgrange_nopull(S3C2410_GPE(5), 2 + width, S3C_GPIO_SFN(2)); +} + +void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) +{ + s3c_gpio_cfgrange_nopull(S3C2410_GPL(0), width, S3C_GPIO_SFN(2)); + s3c_gpio_cfgrange_nopull(S3C2410_GPL(8), 2, S3C_GPIO_SFN(2)); +} diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c new file mode 100644 index 00000000000..ed34fad8f2c --- /dev/null +++ b/arch/arm/mach-s3c2416/setup-sdhci.c @@ -0,0 +1,61 @@ +/* linux/arch/arm/mach-s3c2416/setup-sdhci.c + * + * Copyright 2010 Promwad Innovation Company + * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> + * + * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC) + * + * Based on mach-s3c64xx/setup-sdhci.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <linux/mmc/card.h> +#include <linux/mmc/host.h> + +#include <plat/regs-sdhci.h> +#include <plat/sdhci.h> + +/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ + +char *s3c2416_hsmmc_clksrcs[4] = { + [0] = "hsmmc", + [1] = "hsmmc", + [2] = "hsmmc-if", + /* [3] = "48m", - note not successfully used yet */ +}; + +void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card) +{ + u32 ctrl2, ctrl3; + + ctrl2 = __raw_readl(r + S3C_SDHCI_CONTROL2); + ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; + ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | + S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | + S3C_SDHCI_CTRL2_ENFBCLKRX | + S3C_SDHCI_CTRL2_DFCNT_NONE | + S3C_SDHCI_CTRL2_ENCLKOUTHOLD); + + if (ios->clock < 25 * 1000000) + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | + S3C_SDHCI_CTRL3_FCSEL2 | + S3C_SDHCI_CTRL3_FCSEL1 | + S3C_SDHCI_CTRL3_FCSEL0); + else + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); + + __raw_writel(ctrl2, r + S3C_SDHCI_CONTROL2); + __raw_writel(ctrl3, r + S3C_SDHCI_CONTROL3); +} diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c index 0c049b95c37..acad4428bef 100644 --- a/arch/arm/mach-s3c2440/irq.c +++ b/arch/arm/mach-s3c2440/irq.c @@ -69,27 +69,27 @@ static void s3c_irq_demux_wdtac97(unsigned int irq, #define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0)) static void -s3c_irq_wdtac97_mask(unsigned int irqno) +s3c_irq_wdtac97_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<13); + s3c_irqsub_mask(data->irq, INTMSK_WDT, 3 << 13); } static void -s3c_irq_wdtac97_unmask(unsigned int irqno) +s3c_irq_wdtac97_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_WDT); + s3c_irqsub_unmask(data->irq, INTMSK_WDT); } static void -s3c_irq_wdtac97_ack(unsigned int irqno) +s3c_irq_wdtac97_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13); + s3c_irqsub_maskack(data->irq, INTMSK_WDT, 3 << 13); } static struct irq_chip s3c_irq_wdtac97 = { - .mask = s3c_irq_wdtac97_mask, - .unmask = s3c_irq_wdtac97_unmask, - .ack = s3c_irq_wdtac97_ack, + .irq_mask = s3c_irq_wdtac97_mask, + .irq_unmask = s3c_irq_wdtac97_unmask, + .irq_ack = s3c_irq_wdtac97_ack, }; static int s3c2440_irq_add(struct sys_device *sysdev) diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c index a75c0c2431e..83daf4ece76 100644 --- a/arch/arm/mach-s3c2440/s3c244x-irq.c +++ b/arch/arm/mach-s3c2440/s3c244x-irq.c @@ -68,27 +68,27 @@ static void s3c_irq_demux_cam(unsigned int irq, #define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0)) static void -s3c_irq_cam_mask(unsigned int irqno) +s3c_irq_cam_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11); + s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11); } static void -s3c_irq_cam_unmask(unsigned int irqno) +s3c_irq_cam_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_CAM); + s3c_irqsub_unmask(data->irq, INTMSK_CAM); } static void -s3c_irq_cam_ack(unsigned int irqno) +s3c_irq_cam_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11); + s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11); } static struct irq_chip s3c_irq_cam = { - .mask = s3c_irq_cam_mask, - .unmask = s3c_irq_cam_unmask, - .ack = s3c_irq_cam_ack, + .irq_mask = s3c_irq_cam_mask, + .irq_unmask = s3c_irq_cam_unmask, + .irq_ack = s3c_irq_cam_ack, }; static int s3c244x_irq_add(struct sys_device *sysdev) diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig index 31babec90ce..d8eb86823df 100644 --- a/arch/arm/mach-s3c2443/Kconfig +++ b/arch/arm/mach-s3c2443/Kconfig @@ -10,6 +10,7 @@ config CPU_S3C2443 select CPU_LLSERIAL_S3C2440 select SAMSUNG_CLKSRC select S3C2443_CLOCK + select S3C_GPIO_PULL_S3C2443 help Support for the S3C2443 SoC from the S3C24XX line @@ -25,7 +26,7 @@ config MACH_SMDK2443 bool "SMDK2443" select CPU_S3C2443 select MACH_SMDK - select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 help Say Y here if you are using an SMDK2443 diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 0c3c0c884cd..f4ec6d5715c 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -196,7 +196,7 @@ static struct clksrc_clk clk_hsspi = { static struct clksrc_clk clk_hsmmc_div = { .clk = { .name = "hsmmc-div", - .id = -1, + .id = 1, .parent = &clk_esysclk.clk, }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, @@ -231,7 +231,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable) static struct clk clk_hsmmc = { .name = "hsmmc-if", - .id = -1, + .id = 1, .parent = &clk_hsmmc_div.clk, .enable = s3c2443_enable_hsmmc, .ops = &(struct clk_ops) { diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c index 893424767ce..c7820f9c135 100644 --- a/arch/arm/mach-s3c2443/irq.c +++ b/arch/arm/mach-s3c2443/irq.c @@ -75,28 +75,27 @@ static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc) #define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0)) #define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97) -static void s3c2443_irq_wdtac97_mask(unsigned int irqno) +static void s3c2443_irq_wdtac97_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97); + s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97); } -static void s3c2443_irq_wdtac97_unmask(unsigned int irqno) +static void s3c2443_irq_wdtac97_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_WDTAC97); + s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97); } -static void s3c2443_irq_wdtac97_ack(unsigned int irqno) +static void s3c2443_irq_wdtac97_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97); + s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97); } static struct irq_chip s3c2443_irq_wdtac97 = { - .mask = s3c2443_irq_wdtac97_mask, - .unmask = s3c2443_irq_wdtac97_unmask, - .ack = s3c2443_irq_wdtac97_ack, + .irq_mask = s3c2443_irq_wdtac97_mask, + .irq_unmask = s3c2443_irq_wdtac97_unmask, + .irq_ack = s3c2443_irq_wdtac97_ack, }; - /* LCD sub interrupts */ static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc) @@ -107,28 +106,27 @@ static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc) #define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0)) #define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4) -static void s3c2443_irq_lcd_mask(unsigned int irqno) +static void s3c2443_irq_lcd_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD); + s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD); } -static void s3c2443_irq_lcd_unmask(unsigned int irqno) +static void s3c2443_irq_lcd_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_LCD); + s3c_irqsub_unmask(data->irq, INTMSK_LCD); } -static void s3c2443_irq_lcd_ack(unsigned int irqno) +static void s3c2443_irq_lcd_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD); + s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD); } static struct irq_chip s3c2443_irq_lcd = { - .mask = s3c2443_irq_lcd_mask, - .unmask = s3c2443_irq_lcd_unmask, - .ack = s3c2443_irq_lcd_ack, + .irq_mask = s3c2443_irq_lcd_mask, + .irq_unmask = s3c2443_irq_lcd_unmask, + .irq_ack = s3c2443_irq_lcd_ack, }; - /* DMA sub interrupts */ static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc) @@ -139,29 +137,27 @@ static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc) #define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0)) #define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5) - -static void s3c2443_irq_dma_mask(unsigned int irqno) +static void s3c2443_irq_dma_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA); + s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA); } -static void s3c2443_irq_dma_unmask(unsigned int irqno) +static void s3c2443_irq_dma_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_DMA); + s3c_irqsub_unmask(data->irq, INTMSK_DMA); } -static void s3c2443_irq_dma_ack(unsigned int irqno) +static void s3c2443_irq_dma_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA); + s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA); } static struct irq_chip s3c2443_irq_dma = { - .mask = s3c2443_irq_dma_mask, - .unmask = s3c2443_irq_dma_unmask, - .ack = s3c2443_irq_dma_ack, + .irq_mask = s3c2443_irq_dma_mask, + .irq_unmask = s3c2443_irq_dma_unmask, + .irq_ack = s3c2443_irq_dma_ack, }; - /* UART3 sub interrupts */ static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc) @@ -172,28 +168,27 @@ static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc) #define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0)) #define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0))) -static void s3c2443_irq_uart3_mask(unsigned int irqno) +static void s3c2443_irq_uart3_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3); + s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3); } -static void s3c2443_irq_uart3_unmask(unsigned int irqno) +static void s3c2443_irq_uart3_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_UART3); + s3c_irqsub_unmask(data->irq, INTMSK_UART3); } -static void s3c2443_irq_uart3_ack(unsigned int irqno) +static void s3c2443_irq_uart3_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3); + s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3); } static struct irq_chip s3c2443_irq_uart3 = { - .mask = s3c2443_irq_uart3_mask, - .unmask = s3c2443_irq_uart3_unmask, - .ack = s3c2443_irq_uart3_ack, + .irq_mask = s3c2443_irq_uart3_mask, + .irq_unmask = s3c2443_irq_uart3_unmask, + .irq_ack = s3c2443_irq_uart3_ack, }; - /* CAM sub interrupts */ static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc) @@ -204,25 +199,25 @@ static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc) #define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0)) #define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P) -static void s3c2443_irq_cam_mask(unsigned int irqno) +static void s3c2443_irq_cam_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_CAM, SUBMSK_CAM); + s3c_irqsub_mask(data->irq, INTMSK_CAM, SUBMSK_CAM); } -static void s3c2443_irq_cam_unmask(unsigned int irqno) +static void s3c2443_irq_cam_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_CAM); + s3c_irqsub_unmask(data->irq, INTMSK_CAM); } -static void s3c2443_irq_cam_ack(unsigned int irqno) +static void s3c2443_irq_cam_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_CAM, SUBMSK_CAM); + s3c_irqsub_maskack(data->irq, INTMSK_CAM, SUBMSK_CAM); } static struct irq_chip s3c2443_irq_cam = { - .mask = s3c2443_irq_cam_mask, - .unmask = s3c2443_irq_cam_unmask, - .ack = s3c2443_irq_cam_ack, + .irq_mask = s3c2443_irq_cam_mask, + .irq_unmask = s3c2443_irq_cam_unmask, + .irq_ack = s3c2443_irq_cam_ack, }; /* IRQ initialisation code */ diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c index 4337f0a9960..514275e43ca 100644 --- a/arch/arm/mach-s3c2443/mach-smdk2443.c +++ b/arch/arm/mach-s3c2443/mach-smdk2443.c @@ -99,13 +99,20 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = { .ucon = 0x3c5, .ulcon = 0x43, .ufcon = 0x51, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, } }; static struct platform_device *smdk2443_devices[] __initdata = { &s3c_device_wdt, &s3c_device_i2c0, - &s3c_device_hsmmc0, + &s3c_device_hsmmc1, #ifdef CONFIG_SND_SOC_SMDK2443_WM9710 &s3c_device_ac97, #endif diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c index 33d18dd1ebd..e6a28ba52c7 100644 --- a/arch/arm/mach-s3c2443/s3c2443.c +++ b/arch/arm/mach-s3c2443/s3c2443.c @@ -16,6 +16,7 @@ #include <linux/list.h> #include <linux/timer.h> #include <linux/init.h> +#include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/serial_core.h> #include <linux/sysdev.h> @@ -32,6 +33,9 @@ #include <mach/regs-s3c2443-clock.h> #include <mach/reset.h> +#include <plat/gpio-core.h> +#include <plat/gpio-cfg.h> +#include <plat/gpio-cfg-helpers.h> #include <plat/s3c2443.h> #include <plat/devs.h> #include <plat/cpu.h> @@ -86,6 +90,9 @@ void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no) void __init s3c2443_map_io(void) { + s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_s3c2443; + s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_s3c2443; + iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc)); } diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 1c98d2ff2ed..dd378206450 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -127,7 +127,7 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable) return s3c64xx_gate(S3C_SCLK_GATE, clk, enable); } -static struct clk init_clocks_disable[] = { +static struct clk init_clocks_off[] = { { .name = "nand", .id = -1, @@ -834,10 +834,6 @@ static struct clk *clks[] __initdata = { void __init s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_divlimit) { - struct clk *clkp; - int ret; - int ptr; - armclk_mask = armclk_divlimit; s3c24xx_register_baseclocks(xtal); @@ -845,17 +841,8 @@ void __init s3c64xx_register_clocks(unsigned long xtal, s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - - (clkp->enable)(clkp, 0); - } + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index 372ea685545..135db1b4125 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c @@ -212,6 +212,7 @@ static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan) config = readl(chan->regs + PL080S_CH_CONFIG); config |= PL080_CONFIG_ENABLE; + config &= ~PL080_CONFIG_HALT; pr_debug("%s: writing config %08x\n", __func__, config); writel(config, chan->regs + PL080S_CH_CONFIG); diff --git a/arch/arm/mach-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c index 5682d6a7f4a..2ead8189da7 100644 --- a/arch/arm/mach-s3c64xx/irq-eint.c +++ b/arch/arm/mach-s3c64xx/irq-eint.c @@ -30,41 +30,41 @@ #include <plat/pm.h> #define eint_offset(irq) ((irq) - IRQ_EINT(0)) -#define eint_irq_to_bit(irq) (1 << eint_offset(irq)) +#define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq))) -static inline void s3c_irq_eint_mask(unsigned int irq) +static inline void s3c_irq_eint_mask(struct irq_data *data) { u32 mask; mask = __raw_readl(S3C64XX_EINT0MASK); - mask |= eint_irq_to_bit(irq); + mask |= (u32)data->chip_data; __raw_writel(mask, S3C64XX_EINT0MASK); } -static void s3c_irq_eint_unmask(unsigned int irq) +static void s3c_irq_eint_unmask(struct irq_data *data) { u32 mask; mask = __raw_readl(S3C64XX_EINT0MASK); - mask &= ~eint_irq_to_bit(irq); + mask &= ~((u32)data->chip_data); __raw_writel(mask, S3C64XX_EINT0MASK); } -static inline void s3c_irq_eint_ack(unsigned int irq) +static inline void s3c_irq_eint_ack(struct irq_data *data) { - __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND); + __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND); } -static void s3c_irq_eint_maskack(unsigned int irq) +static void s3c_irq_eint_maskack(struct irq_data *data) { /* compiler should in-line these */ - s3c_irq_eint_mask(irq); - s3c_irq_eint_ack(irq); + s3c_irq_eint_mask(data); + s3c_irq_eint_ack(data); } -static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) +static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type) { - int offs = eint_offset(irq); + int offs = eint_offset(data->irq); int pin, pin_val; int shift; u32 ctrl, mask; @@ -140,12 +140,12 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) static struct irq_chip s3c_irq_eint = { .name = "s3c-eint", - .mask = s3c_irq_eint_mask, - .unmask = s3c_irq_eint_unmask, - .mask_ack = s3c_irq_eint_maskack, - .ack = s3c_irq_eint_ack, - .set_type = s3c_irq_eint_set_type, - .set_wake = s3c_irqext_wake, + .irq_mask = s3c_irq_eint_mask, + .irq_unmask = s3c_irq_eint_unmask, + .irq_mask_ack = s3c_irq_eint_maskack, + .irq_ack = s3c_irq_eint_ack, + .irq_set_type = s3c_irq_eint_set_type, + .irq_set_wake = s3c_irqext_wake, }; /* s3c_irq_demux_eint @@ -198,6 +198,7 @@ static int __init s3c64xx_init_irq_eint(void) for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { set_irq_chip(irq, &s3c_irq_eint); + set_irq_chip_data(irq, (void *)eint_irq_to_bit(irq)); set_irq_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c index 16d6e7e61b5..fbbc7bede68 100644 --- a/arch/arm/mach-s5p6442/clock.c +++ b/arch/arm/mach-s5p6442/clock.c @@ -340,7 +340,7 @@ void __init_or_cpufreq s5p6442_setup_clocks(void) clk_pclkd1.rate = pclkd1; } -static struct clk init_clocks_disable[] = { +static struct clk init_clocks_off[] = { { .name = "pdma", .id = -1, @@ -408,23 +408,13 @@ static struct clk *clks[] __initdata = { void __init s5p6442_register_clocks(void) { - struct clk *clkptr; - int i, ret; - s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - clkptr = init_clocks_disable; - for (i = 0; i < ARRAY_SIZE(init_clocks_disable); i++, clkptr++) { - ret = s3c24xx_register_clock(clkptr); - if (ret < 0) { - printk(KERN_ERR "Fail to register clock %s (%d)\n", - clkptr->name, ret); - } else - (clkptr->enable)(clkptr, 0); - } + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h index 31fb2e68d52..203dd5a18bd 100644 --- a/arch/arm/mach-s5p6442/include/mach/map.h +++ b/arch/arm/mach-s5p6442/include/mach/map.h @@ -28,6 +28,9 @@ #define S5P6442_PA_VIC1 (0xE4100000) #define S5P6442_PA_VIC2 (0xE4200000) +#define S5P6442_PA_SROMC (0xE7000000) +#define S5P_PA_SROMC S5P6442_PA_SROMC + #define S5P6442_PA_MDMA 0xE8000000 #define S5P6442_PA_PDMA 0xE9000000 diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c index 819fd80d00a..eaf6b9c489f 100644 --- a/arch/arm/mach-s5p6442/mach-smdk6442.c +++ b/arch/arm/mach-s5p6442/mach-smdk6442.c @@ -12,6 +12,7 @@ #include <linux/types.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/i2c.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -25,6 +26,7 @@ #include <plat/s5p6442.h> #include <plat/devs.h> #include <plat/cpu.h> +#include <plat/iic.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDK6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -65,10 +67,16 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = { }; static struct platform_device *smdk6442_devices[] __initdata = { + &s3c_device_i2c0, + &samsung_asoc_dma, &s5p6442_device_iis0, &s3c_device_wdt, }; +static struct i2c_board_info smdk6442_i2c_devs0[] __initdata = { + { I2C_BOARD_INFO("wm8580", 0x1b), }, +}; + static void __init smdk6442_map_io(void) { s5p_init_io(NULL, 0, S5P_VA_CHIPID); @@ -78,6 +86,9 @@ static void __init smdk6442_map_io(void) static void __init smdk6442_machine_init(void) { + s3c_i2c0_set_platdata(NULL); + i2c_register_board_info(0, smdk6442_i2c_devs0, + ARRAY_SIZE(smdk6442_i2c_devs0)); platform_add_devices(smdk6442_devices, ARRAY_SIZE(smdk6442_devices)); } diff --git a/arch/arm/mach-s5p6442/setup-i2c0.c b/arch/arm/mach-s5p6442/setup-i2c0.c index 662695dd776..aad85656b0c 100644 --- a/arch/arm/mach-s5p6442/setup-i2c0.c +++ b/arch/arm/mach-s5p6442/setup-i2c0.c @@ -14,12 +14,15 @@ #include <linux/kernel.h> #include <linux/types.h> +#include <linux/gpio.h> struct platform_device; /* don't need the contents */ +#include <plat/gpio-cfg.h> #include <plat/iic.h> void s3c_i2c0_cfg_gpio(struct platform_device *dev) { - /* Will be populated later */ + s3c_gpio_cfgall_range(S5P6442_GPD1(0), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); } diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile index 2655829e6bf..ae6bf6feba8 100644 --- a/arch/arm/mach-s5p64x0/Makefile +++ b/arch/arm/mach-s5p64x0/Makefile @@ -12,9 +12,9 @@ obj- := # Core support for S5P64X0 system -obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o +obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o -obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o gpio.o +obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o # machine support diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index 409c5fc3670..9f12c2ebf41 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c @@ -133,7 +133,7 @@ static struct clksrc_clk clk_pclk_low = { * recommended to keep the following clocks disabled until the driver requests * for enabling the clock. */ -static struct clk init_clocks_disable[] = { +static struct clk init_clocks_off[] = { { .name = "nand", .id = -1, @@ -419,7 +419,7 @@ static struct clksrc_sources clkset_audio = { static struct clksrc_clk clksrcs[] = { { .clk = { - .name = "mmc_bus", + .name = "sclk_mmc", .id = 0, .ctrlbit = (1 << 24), .enable = s5p64x0_sclk_ctrl, @@ -429,7 +429,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 }, }, { .clk = { - .name = "mmc_bus", + .name = "sclk_mmc", .id = 1, .ctrlbit = (1 << 25), .enable = s5p64x0_sclk_ctrl, @@ -439,7 +439,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 }, }, { .clk = { - .name = "mmc_bus", + .name = "sclk_mmc", .id = 2, .ctrlbit = (1 << 26), .enable = s5p64x0_sclk_ctrl, @@ -602,8 +602,6 @@ static struct clk *clks[] __initdata = { void __init s5p6440_register_clocks(void) { - struct clk *clkp; - int ret; int ptr; s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); @@ -614,16 +612,8 @@ void __init s5p6440_register_clocks(void) s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - (clkp->enable)(clkp, 0); - } + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c index 7fc6abd3591..4eec457ddcc 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c @@ -181,7 +181,7 @@ static struct clksrc_clk clk_pclk_low = { * recommended to keep the following clocks disabled until the driver requests * for enabling the clock. */ -static struct clk init_clocks_disable[] = { +static struct clk init_clocks_off[] = { { .name = "usbhost", .id = -1, @@ -231,6 +231,12 @@ static struct clk init_clocks_disable[] = { .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 5), }, { + .name = "rtc", + .id = -1, + .parent = &clk_pclk_low.clk, + .enable = s5p64x0_pclk_ctrl, + .ctrlbit = (1 << 6), + }, { .name = "adc", .id = -1, .parent = &clk_pclk_low.clk, @@ -261,6 +267,18 @@ static struct clk init_clocks_disable[] = { .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 26), }, { + .name = "iis", + .id = 1, + .parent = &clk_pclk_low.clk, + .enable = s5p64x0_pclk_ctrl, + .ctrlbit = (1 << 15), + }, { + .name = "iis", + .id = 2, + .parent = &clk_pclk_low.clk, + .enable = s5p64x0_pclk_ctrl, + .ctrlbit = (1 << 16), + }, { .name = "i2c", .id = 1, .parent = &clk_pclk_low.clk, @@ -633,8 +651,6 @@ void __init_or_cpufreq s5p6450_setup_clocks(void) void __init s5p6450_register_clocks(void) { - struct clk *clkp; - int ret; int ptr; for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) @@ -643,16 +659,8 @@ void __init s5p6450_register_clocks(void) s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - (clkp->enable)(clkp, 0); - } + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c index 14f89e73b8d..35f1f226dab 100644 --- a/arch/arm/mach-s5p64x0/dev-audio.c +++ b/arch/arm/mach-s5p64x0/dev-audio.c @@ -24,13 +24,13 @@ static const char *rclksrc[] = { [1] = "sclk_audio2", }; -static int s5p64x0_cfg_i2s(struct platform_device *pdev) +static int s5p6440_cfg_i2s(struct platform_device *pdev) { - /* configure GPIO for i2s port */ switch (pdev->id) { case 0: - s3c_gpio_cfgpin_range(S5P6440_GPR(4), 5, S3C_GPIO_SFN(5)); - s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin_range(S5P6440_GPC(4), 2, S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin(S5P6440_GPC(7), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin_range(S5P6440_GPH(6), 4, S3C_GPIO_SFN(5)); break; default: printk(KERN_ERR "Invalid Device %d\n", pdev->id); @@ -40,8 +40,8 @@ static int s5p64x0_cfg_i2s(struct platform_device *pdev) return 0; } -static struct s3c_audio_pdata s5p64x0_i2s_pdata = { - .cfg_gpio = s5p64x0_cfg_i2s, +static struct s3c_audio_pdata s5p6440_i2s_pdata = { + .cfg_gpio = s5p6440_cfg_i2s, .type = { .i2s = { .quirks = QUIRK_PRI_6CHAN, @@ -50,7 +50,7 @@ static struct s3c_audio_pdata s5p64x0_i2s_pdata = { }, }; -static struct resource s5p64x0_iis0_resource[] = { +static struct resource s5p64x0_i2s0_resource[] = { [0] = { .start = S5P64X0_PA_I2S, .end = S5P64X0_PA_I2S + 0x100 - 1, @@ -71,20 +71,117 @@ static struct resource s5p64x0_iis0_resource[] = { struct platform_device s5p6440_device_iis = { .name = "samsung-i2s", .id = 0, - .num_resources = ARRAY_SIZE(s5p64x0_iis0_resource), - .resource = s5p64x0_iis0_resource, + .num_resources = ARRAY_SIZE(s5p64x0_i2s0_resource), + .resource = s5p64x0_i2s0_resource, .dev = { - .platform_data = &s5p64x0_i2s_pdata, + .platform_data = &s5p6440_i2s_pdata, + }, +}; + +static int s5p6450_cfg_i2s(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin_range(S5P6450_GPR(4), 5, S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin_range(S5P6450_GPR(13), 2, S3C_GPIO_SFN(5)); + break; + case 1: + s3c_gpio_cfgpin(S5P6440_GPB(4), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin_range(S5P6450_GPC(0), 4, S3C_GPIO_SFN(5)); + break; + case 2: + s3c_gpio_cfgpin_range(S5P6450_GPK(0), 5, S3C_GPIO_SFN(5)); + break; + default: + printk(KERN_ERR "Invalid Device %d\n", pdev->id); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata s5p6450_i2s0_pdata = { + .cfg_gpio = s5p6450_cfg_i2s, + .type = { + .i2s = { + .quirks = QUIRK_PRI_6CHAN, + .src_clk = rclksrc, + }, }, }; struct platform_device s5p6450_device_iis0 = { .name = "samsung-i2s", .id = 0, - .num_resources = ARRAY_SIZE(s5p64x0_iis0_resource), - .resource = s5p64x0_iis0_resource, + .num_resources = ARRAY_SIZE(s5p64x0_i2s0_resource), + .resource = s5p64x0_i2s0_resource, + .dev = { + .platform_data = &s5p6450_i2s0_pdata, + }, +}; + +static struct s3c_audio_pdata s5p6450_i2s_pdata = { + .cfg_gpio = s5p6450_cfg_i2s, + .type = { + .i2s = { + .src_clk = rclksrc, + }, + }, +}; + +static struct resource s5p6450_i2s1_resource[] = { + [0] = { + .start = S5P6450_PA_I2S1, + .end = S5P6450_PA_I2S1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S1_TX, + .end = DMACH_I2S1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S1_RX, + .end = DMACH_I2S1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5p6450_device_iis1 = { + .name = "samsung-i2s", + .id = 1, + .num_resources = ARRAY_SIZE(s5p6450_i2s1_resource), + .resource = s5p6450_i2s1_resource, + .dev = { + .platform_data = &s5p6450_i2s_pdata, + }, +}; + +static struct resource s5p6450_i2s2_resource[] = { + [0] = { + .start = S5P6450_PA_I2S2, + .end = S5P6450_PA_I2S2 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S2_TX, + .end = DMACH_I2S2_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S2_RX, + .end = DMACH_I2S2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5p6450_device_iis2 = { + .name = "samsung-i2s", + .id = 2, + .num_resources = ARRAY_SIZE(s5p6450_i2s2_resource), + .resource = s5p6450_i2s2_resource, .dev = { - .platform_data = &s5p64x0_i2s_pdata, + .platform_data = &s5p6450_i2s_pdata, }, }; diff --git a/arch/arm/mach-s5p64x0/gpio.c b/arch/arm/mach-s5p64x0/gpiolib.c index 39159dd5a29..e7fb3b004e7 100644 --- a/arch/arm/mach-s5p64x0/gpio.c +++ b/arch/arm/mach-s5p64x0/gpiolib.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s5p64x0/gpio.c +/* linux/arch/arm/mach-s5p64x0/gpiolib.c * * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. * http://www.samsung.com @@ -17,13 +17,12 @@ #include <mach/map.h> #include <mach/regs-gpio.h> +#include <mach/regs-clock.h> #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> #include <plat/gpio-cfg-helpers.h> -/* To be implemented S5P6450 GPIO */ - /* * S5P6440 GPIO bank summary: * @@ -40,6 +39,25 @@ * P 8 2Bit Yes 8 * R 15 4Bit[2] Yes 8 * + * S5P6450 GPIO bank summary: + * + * Bank GPIOs Style SlpCon ExtInt Group + * A 6 4Bit Yes 1 + * B 7 4Bit Yes 1 + * C 8 4Bit Yes 2 + * D 8 4Bit Yes None + * F 2 2Bit Yes None + * G 14 4Bit[2] Yes 5 + * H 10 4Bit[2] Yes 6 + * I 16 2Bit Yes None + * J 12 2Bit Yes None + * K 5 4Bit Yes None + * N 16 2Bit No IRQ_EINT + * P 11 2Bit Yes 8 + * Q 14 2Bit Yes None + * R 15 4Bit[2] Yes None + * S 8 2Bit Yes None + * * [1] BANKF pins 14,15 do not form part of the external interrupt sources * [2] BANK has two control registers, GPxCON0 and GPxCON1 */ @@ -190,7 +208,7 @@ static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = { static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { { - .base = S5P6440_GPA_BASE, + .base = S5P64X0_GPA_BASE, .config = &s5p64x0_gpio_cfgs[1], .chip = { .base = S5P6440_GPA(0), @@ -198,7 +216,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { .label = "GPA", }, }, { - .base = S5P6440_GPB_BASE, + .base = S5P64X0_GPB_BASE, .config = &s5p64x0_gpio_cfgs[1], .chip = { .base = S5P6440_GPB(0), @@ -206,7 +224,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { .label = "GPB", }, }, { - .base = S5P6440_GPC_BASE, + .base = S5P64X0_GPC_BASE, .config = &s5p64x0_gpio_cfgs[1], .chip = { .base = S5P6440_GPC(0), @@ -214,7 +232,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { .label = "GPC", }, }, { - .base = S5P6440_GPG_BASE, + .base = S5P64X0_GPG_BASE, .config = &s5p64x0_gpio_cfgs[1], .chip = { .base = S5P6440_GPG(0), @@ -226,7 +244,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = { { - .base = S5P6440_GPH_BASE + 0x4, + .base = S5P64X0_GPH_BASE + 0x4, .config = &s5p64x0_gpio_cfgs[1], .chip = { .base = S5P6440_GPH(0), @@ -238,7 +256,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = { static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = { { - .base = S5P6440_GPR_BASE + 0x4, + .base = S5P64X0_GPR_BASE + 0x4, .config = &s5p64x0_gpio_cfgs[2], .chip = { .base = S5P6440_GPR(0), @@ -250,7 +268,7 @@ static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = { static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { { - .base = S5P6440_GPF_BASE, + .base = S5P64X0_GPF_BASE, .config = &s5p64x0_gpio_cfgs[5], .chip = { .base = S5P6440_GPF(0), @@ -258,7 +276,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { .label = "GPF", }, }, { - .base = S5P6440_GPI_BASE, + .base = S5P64X0_GPI_BASE, .config = &s5p64x0_gpio_cfgs[3], .chip = { .base = S5P6440_GPI(0), @@ -266,7 +284,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { .label = "GPI", }, }, { - .base = S5P6440_GPJ_BASE, + .base = S5P64X0_GPJ_BASE, .config = &s5p64x0_gpio_cfgs[3], .chip = { .base = S5P6440_GPJ(0), @@ -274,7 +292,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { .label = "GPJ", }, }, { - .base = S5P6440_GPN_BASE, + .base = S5P64X0_GPN_BASE, .config = &s5p64x0_gpio_cfgs[4], .chip = { .base = S5P6440_GPN(0), @@ -282,7 +300,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { .label = "GPN", }, }, { - .base = S5P6440_GPP_BASE, + .base = S5P64X0_GPP_BASE, .config = &s5p64x0_gpio_cfgs[5], .chip = { .base = S5P6440_GPP(0), @@ -292,6 +310,142 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { }, }; +static struct s3c_gpio_chip s5p6450_gpio_4bit[] = { + { + .base = S5P64X0_GPA_BASE, + .config = &s5p64x0_gpio_cfgs[1], + .chip = { + .base = S5P6450_GPA(0), + .ngpio = S5P6450_GPIO_A_NR, + .label = "GPA", + }, + }, { + .base = S5P64X0_GPB_BASE, + .config = &s5p64x0_gpio_cfgs[1], + .chip = { + .base = S5P6450_GPB(0), + .ngpio = S5P6450_GPIO_B_NR, + .label = "GPB", + }, + }, { + .base = S5P64X0_GPC_BASE, + .config = &s5p64x0_gpio_cfgs[1], + .chip = { + .base = S5P6450_GPC(0), + .ngpio = S5P6450_GPIO_C_NR, + .label = "GPC", + }, + }, { + .base = S5P6450_GPD_BASE, + .config = &s5p64x0_gpio_cfgs[1], + .chip = { + .base = S5P6450_GPD(0), + .ngpio = S5P6450_GPIO_D_NR, + .label = "GPD", + }, + }, { + .base = S5P6450_GPK_BASE, + .config = &s5p64x0_gpio_cfgs[1], + .chip = { + .base = S5P6450_GPK(0), + .ngpio = S5P6450_GPIO_K_NR, + .label = "GPK", + }, + }, +}; + +static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = { + { + .base = S5P64X0_GPG_BASE + 0x4, + .config = &s5p64x0_gpio_cfgs[1], + .chip = { + .base = S5P6450_GPG(0), + .ngpio = S5P6450_GPIO_G_NR, + .label = "GPG", + }, + }, { + .base = S5P64X0_GPH_BASE + 0x4, + .config = &s5p64x0_gpio_cfgs[1], + .chip = { + .base = S5P6450_GPH(0), + .ngpio = S5P6450_GPIO_H_NR, + .label = "GPH", + }, + }, +}; + +static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = { + { + .base = S5P64X0_GPR_BASE + 0x4, + .config = &s5p64x0_gpio_cfgs[2], + .chip = { + .base = S5P6450_GPR(0), + .ngpio = S5P6450_GPIO_R_NR, + .label = "GPR", + }, + }, +}; + +static struct s3c_gpio_chip s5p6450_gpio_2bit[] = { + { + .base = S5P64X0_GPF_BASE, + .config = &s5p64x0_gpio_cfgs[5], + .chip = { + .base = S5P6450_GPF(0), + .ngpio = S5P6450_GPIO_F_NR, + .label = "GPF", + }, + }, { + .base = S5P64X0_GPI_BASE, + .config = &s5p64x0_gpio_cfgs[3], + .chip = { + .base = S5P6450_GPI(0), + .ngpio = S5P6450_GPIO_I_NR, + .label = "GPI", + }, + }, { + .base = S5P64X0_GPJ_BASE, + .config = &s5p64x0_gpio_cfgs[3], + .chip = { + .base = S5P6450_GPJ(0), + .ngpio = S5P6450_GPIO_J_NR, + .label = "GPJ", + }, + }, { + .base = S5P64X0_GPN_BASE, + .config = &s5p64x0_gpio_cfgs[4], + .chip = { + .base = S5P6450_GPN(0), + .ngpio = S5P6450_GPIO_N_NR, + .label = "GPN", + }, + }, { + .base = S5P64X0_GPP_BASE, + .config = &s5p64x0_gpio_cfgs[5], + .chip = { + .base = S5P6450_GPP(0), + .ngpio = S5P6450_GPIO_P_NR, + .label = "GPP", + }, + }, { + .base = S5P6450_GPQ_BASE, + .config = &s5p64x0_gpio_cfgs[4], + .chip = { + .base = S5P6450_GPQ(0), + .ngpio = S5P6450_GPIO_Q_NR, + .label = "GPQ", + }, + }, { + .base = S5P6450_GPS_BASE, + .config = &s5p64x0_gpio_cfgs[5], + .chip = { + .base = S5P6450_GPS(0), + .ngpio = S5P6450_GPIO_S_NR, + .label = "GPS", + }, + }, +}; + void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips) { for (; nr_chips > 0; nr_chips--, chipcfg++) { @@ -317,26 +471,41 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip, } } -static int __init s5p6440_gpiolib_init(void) +static int __init s5p64x0_gpiolib_init(void) { - struct s3c_gpio_chip *chips = s5p6440_gpio_2bit; - int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit); + unsigned int chipid; + + chipid = __raw_readl(S5P64X0_SYS_ID); s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs, ARRAY_SIZE(s5p64x0_gpio_cfgs)); - for (; nr_chips > 0; nr_chips--, chips++) - s3c_gpiolib_add(chips); + if ((chipid & 0xff000) == 0x50000) { + samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit, + ARRAY_SIZE(s5p6450_gpio_2bit)); + + samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit, + ARRAY_SIZE(s5p6450_gpio_4bit)); - samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit, - ARRAY_SIZE(s5p6440_gpio_4bit)); + samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2, + ARRAY_SIZE(s5p6450_gpio_4bit2)); - samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2, - ARRAY_SIZE(s5p6440_gpio_4bit2)); + s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2, + ARRAY_SIZE(s5p6450_gpio_rbank_4bit2)); + } else { + samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit, + ARRAY_SIZE(s5p6440_gpio_2bit)); - s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2, - ARRAY_SIZE(s5p6440_gpio_rbank_4bit2)); + samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit, + ARRAY_SIZE(s5p6440_gpio_4bit)); + + samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2, + ARRAY_SIZE(s5p6440_gpio_4bit2)); + + s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2, + ARRAY_SIZE(s5p6440_gpio_rbank_4bit2)); + } return 0; } -arch_initcall(s5p6440_gpiolib_init); +core_initcall(s5p64x0_gpiolib_init); diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h index 31e534156e0..a9365e5ba61 100644 --- a/arch/arm/mach-s5p64x0/include/mach/map.h +++ b/arch/arm/mach-s5p64x0/include/mach/map.h @@ -29,6 +29,9 @@ #define S5P64X0_PA_VIC0 (0xE4000000) #define S5P64X0_PA_VIC1 (0xE4100000) +#define S5P64X0_PA_SROMC (0xE7000000) +#define S5P_PA_SROMC S5P64X0_PA_SROMC + #define S5P64X0_PA_PDMA (0xE9000000) #define S5P64X0_PA_TIMER (0xEA000000) @@ -63,6 +66,8 @@ #define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) #define S5P64X0_PA_I2S (0xF2000000) +#define S5P6450_PA_I2S1 0xF2800000 +#define S5P6450_PA_I2S2 0xF2900000 #define S5P64X0_PA_PCM (0xF2100000) diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h index 85f448e20a8..0953ef6b1c7 100644 --- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h +++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h @@ -15,48 +15,23 @@ #include <mach/map.h> -/* Will be implemented S5P6442 GPIOlib */ - /* Base addresses for each of the banks */ -#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000) -#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020) -#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040) -#define S5P6440_GPF_BASE (S5P_VA_GPIO + 0x00A0) -#define S5P6440_GPG_BASE (S5P_VA_GPIO + 0x00C0) -#define S5P6440_GPH_BASE (S5P_VA_GPIO + 0x00E0) -#define S5P6440_GPI_BASE (S5P_VA_GPIO + 0x0100) -#define S5P6440_GPJ_BASE (S5P_VA_GPIO + 0x0120) -#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830) -#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160) -#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290) - -#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900) -#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910) -#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914) -#define S5P6440_EINT0MASK (S5P_VA_GPIO + 0x920) -#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924) - -/* for LCD */ - -#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0) -#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0) - -/* - * These set of macros are not really useful for the - * GPF/GPI/GPJ/GPN/GPP, useful for others set of GPIO's (4 bit) - */ - -#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4)) -#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4)) -#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) - -/* - * Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit) - */ - -#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) -#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2)) -#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) +#define S5P64X0_GPA_BASE (S5P_VA_GPIO + 0x0000) +#define S5P64X0_GPB_BASE (S5P_VA_GPIO + 0x0020) +#define S5P64X0_GPC_BASE (S5P_VA_GPIO + 0x0040) +#define S5P64X0_GPF_BASE (S5P_VA_GPIO + 0x00A0) +#define S5P64X0_GPG_BASE (S5P_VA_GPIO + 0x00C0) +#define S5P64X0_GPH_BASE (S5P_VA_GPIO + 0x00E0) +#define S5P64X0_GPI_BASE (S5P_VA_GPIO + 0x0100) +#define S5P64X0_GPJ_BASE (S5P_VA_GPIO + 0x0120) +#define S5P64X0_GPN_BASE (S5P_VA_GPIO + 0x0830) +#define S5P64X0_GPP_BASE (S5P_VA_GPIO + 0x0160) +#define S5P64X0_GPR_BASE (S5P_VA_GPIO + 0x0290) + +#define S5P6450_GPD_BASE (S5P_VA_GPIO + 0x0060) +#define S5P6450_GPK_BASE (S5P_VA_GPIO + 0x0140) +#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180) +#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300) #endif /* __ASM_ARCH_REGS_GPIO_H */ diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c index 87c3f03c618..e5beb84e239 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6440.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c @@ -95,6 +95,7 @@ static struct platform_device *smdk6440_devices[] __initdata = { &s3c_device_i2c1, &s3c_device_ts, &s3c_device_wdt, + &samsung_asoc_dma, &s5p6440_device_iis, }; @@ -117,6 +118,7 @@ static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = { static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = { { I2C_BOARD_INFO("24c08", 0x50), }, + { I2C_BOARD_INFO("wm8580", 0x1b), }, }; static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = { diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c index d609f5af2b9..3a20de0a926 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6450.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c @@ -113,6 +113,7 @@ static struct platform_device *smdk6450_devices[] __initdata = { &s3c_device_i2c1, &s3c_device_ts, &s3c_device_wdt, + &samsung_asoc_dma, &s5p6450_device_iis0, /* s5p6450_device_spi0 will be added */ }; @@ -135,6 +136,7 @@ static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = { }; static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = { + { I2C_BOARD_INFO("wm8580", 0x1b), }, { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung KS24C080C EEPROM */ }; diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index 2d4a761a516..0305e9b8282 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c @@ -396,7 +396,7 @@ static int s5pc100_sclk1_ctrl(struct clk *clk, int enable) * recommended to keep the following clocks disabled until the driver requests * for enabling the clock. */ -static struct clk init_clocks_disable[] = { +static struct clk init_clocks_off[] = { { .name = "cssys", .id = -1, @@ -1381,8 +1381,6 @@ static struct clk *clks[] __initdata = { void __init s5pc100_register_clocks(void) { - struct clk *clkp; - int ret; int ptr; s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); @@ -1393,16 +1391,8 @@ void __init s5pc100_register_clocks(void) s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - (clkp->enable)(clkp, 0); - } + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h index 32e9cab5c86..328467b346a 100644 --- a/arch/arm/mach-s5pc100/include/mach/map.h +++ b/arch/arm/mach-s5pc100/include/mach/map.h @@ -55,6 +55,8 @@ #define S5PC100_VA_VIC_OFFSET 0x10000 #define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) +#define S5PC100_PA_SROMC (0xE7000000) +#define S5P_PA_SROMC S5PC100_PA_SROMC #define S5PC100_PA_ONENAND (0xE7100000) diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 862f239a0fd..53aabef1e9c 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -118,6 +118,7 @@ menu "S5PV210 Machines" config MACH_SMDKV210 bool "SMDKV210" select CPU_S5PV210 + select S3C_DEV_FB select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 @@ -130,6 +131,7 @@ config MACH_SMDKV210 select SAMSUNG_DEV_IDE select SAMSUNG_DEV_KEYPAD select SAMSUNG_DEV_TS + select S5PV210_SETUP_FB_24BPP select S5PV210_SETUP_I2C1 select S5PV210_SETUP_I2C2 select S5PV210_SETUP_IDE diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index b774ff1805d..2d599499cef 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -309,7 +309,7 @@ static struct clk_ops clk_fout_apll_ops = { .get_rate = s5pv210_clk_fout_apll_get_rate, }; -static struct clk init_clocks_disable[] = { +static struct clk init_clocks_off[] = { { .name = "pdma", .id = 0, @@ -525,6 +525,12 @@ static struct clk init_clocks[] = { .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 20), + }, { + .name = "sromc", + .id = -1, + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 26), }, }; @@ -1220,13 +1226,9 @@ static struct clk *clks[] __initdata = { void __init s5pv210_register_clocks(void) { - struct clk *clkp; - int ret; int ptr; - ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - if (ret > 0) - printk(KERN_ERR "Failed to register %u clocks\n", ret); + s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) s3c_register_clksrc(sysclks[ptr], 1); @@ -1234,15 +1236,8 @@ void __init s5pv210_register_clocks(void) s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - (clkp->enable)(clkp, 0); - } + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 8eb480e201b..61e6c24b90a 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c @@ -81,11 +81,6 @@ static struct map_desc s5pv210_iodesc[] __initdata = { .length = SZ_512K, .type = MT_DEVICE, }, { - .virtual = (unsigned long)S5P_VA_SROMC, - .pfn = __phys_to_pfn(S5PV210_PA_SROMC), - .length = SZ_4K, - .type = MT_DEVICE, - }, { .virtual = (unsigned long)S5P_VA_DMC0, .pfn = __phys_to_pfn(S5PV210_PA_DMC0), .length = SZ_4K, diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index 119b95fdc3c..26710b35ef8 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -65,7 +65,7 @@ #define IRQ_HSMMC0 S5P_IRQ_VIC1(26) #define IRQ_HSMMC1 S5P_IRQ_VIC1(27) #define IRQ_HSMMC2 S5P_IRQ_VIC1(28) -#define IRQ_MIPICSI S5P_IRQ_VIC1(29) +#define IRQ_MIPI_CSIS S5P_IRQ_VIC1(29) #define IRQ_MIPIDSI S5P_IRQ_VIC1(30) #define IRQ_ONENAND_AUDI S5P_IRQ_VIC1(31) @@ -132,5 +132,6 @@ #define IRQ_LCD_FIFO IRQ_LCD0 #define IRQ_LCD_VSYNC IRQ_LCD1 #define IRQ_LCD_SYSTEM IRQ_LCD2 +#define IRQ_MIPI_CSIS0 IRQ_MIPI_CSIS #endif /* ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index 861d7fe11fc..3611492ad68 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -16,6 +16,8 @@ #include <plat/map-base.h> #include <plat/map-s5p.h> +#define S5PV210_PA_SROM_BANK5 (0xA8000000) + #define S5PC110_PA_ONENAND (0xB0000000) #define S5P_PA_ONENAND S5PC110_PA_ONENAND @@ -60,6 +62,7 @@ #define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) #define S5PV210_PA_SROMC (0xE8000000) +#define S5P_PA_SROMC S5PV210_PA_SROMC #define S5PV210_PA_CFCON (0xE8200000) @@ -107,6 +110,8 @@ #define S5PV210_PA_DMC0 (0xF0000000) #define S5PV210_PA_DMC1 (0xF1400000) +#define S5PV210_PA_MIPI_CSIS 0xFA600000 + /* compatibiltiy defines. */ #define S3C_PA_UART S5PV210_PA_UART #define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0) @@ -123,6 +128,7 @@ #define S5P_PA_FIMC0 S5PV210_PA_FIMC0 #define S5P_PA_FIMC1 S5PV210_PA_FIMC1 #define S5P_PA_FIMC2 S5PV210_PA_FIMC2 +#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS #define SAMSUNG_PA_ADC S5PV210_PA_ADC #define SAMSUNG_PA_CFCON S5PV210_PA_CFCON diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h index ebaabe021af..4c45b74def5 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h @@ -161,7 +161,7 @@ #define S5P_MDNIE_SEL S5P_CLKREG(0x7008) #define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) #define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) -#define S5P_MIPI_CONTROL S5P_CLKREG(0xE814) +#define S5P_MIPI_DPHY_CONTROL S5P_CLKREG(0xE814) #define S5P_IDLE_CFG_TL_MASK (3 << 30) #define S5P_IDLE_CFG_TM_MASK (3 << 28) @@ -195,9 +195,6 @@ #define S5P_OTHERS_RET_UART (1 << 28) #define S5P_OTHERS_USB_SIG_MASK (1 << 16) -/* MIPI */ -#define S5P_MIPI_DPHY_EN (3) - /* S5P_DAC_CONTROL */ #define S5P_DAC_ENABLE (1) #define S5P_DAC_DISABLE (0) diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c index 5dd1681c069..ce11a02eabf 100644 --- a/arch/arm/mach-s5pv210/mach-smdkc110.c +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c @@ -81,6 +81,7 @@ static struct s3c_ide_platdata smdkc110_ide_pdata __initdata = { }; static struct platform_device *smdkc110_devices[] __initdata = { + &samsung_asoc_dma, &s5pv210_device_iis0, &s5pv210_device_ac97, &s5pv210_device_spdif, @@ -94,6 +95,7 @@ static struct platform_device *smdkc110_devices[] __initdata = { static struct i2c_board_info smdkc110_i2c_devs0[] __initdata = { { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */ + { I2C_BOARD_INFO("wm8580", 0x1b), }, }; static struct i2c_board_info smdkc110_i2c_devs1[] __initdata = { diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index 1fbc45b2a43..bc9fdb52a02 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -14,16 +14,25 @@ #include <linux/init.h> #include <linux/serial_core.h> #include <linux/sysdev.h> +#include <linux/dm9000.h> +#include <linux/fb.h> +#include <linux/gpio.h> +#include <linux/delay.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/setup.h> #include <asm/mach-types.h> +#include <video/platform_lcd.h> + #include <mach/map.h> #include <mach/regs-clock.h> +#include <mach/regs-fb.h> #include <plat/regs-serial.h> +#include <plat/regs-srom.h> +#include <plat/gpio-cfg.h> #include <plat/s5pv210.h> #include <plat/devs.h> #include <plat/cpu.h> @@ -33,6 +42,7 @@ #include <plat/iic.h> #include <plat/keypad.h> #include <plat/pm.h> +#include <plat/fb.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -102,12 +112,106 @@ static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = { .cols = 8, }; +static struct resource smdkv210_dm9000_resources[] = { + [0] = { + .start = S5PV210_PA_SROM_BANK5, + .end = S5PV210_PA_SROM_BANK5, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = S5PV210_PA_SROM_BANK5 + 2, + .end = S5PV210_PA_SROM_BANK5 + 2, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = IRQ_EINT(9), + .end = IRQ_EINT(9), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct dm9000_plat_data smdkv210_dm9000_platdata = { + .flags = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM, + .dev_addr = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 }, +}; + +struct platform_device smdkv210_dm9000 = { + .name = "dm9000", + .id = -1, + .num_resources = ARRAY_SIZE(smdkv210_dm9000_resources), + .resource = smdkv210_dm9000_resources, + .dev = { + .platform_data = &smdkv210_dm9000_platdata, + }, +}; + +static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd, + unsigned int power) +{ + if (power) { +#if !defined(CONFIG_BACKLIGHT_PWM) + gpio_request(S5PV210_GPD0(3), "GPD0"); + gpio_direction_output(S5PV210_GPD0(3), 1); + gpio_free(S5PV210_GPD0(3)); +#endif + + /* fire nRESET on power up */ + gpio_request(S5PV210_GPH0(6), "GPH0"); + + gpio_direction_output(S5PV210_GPH0(6), 1); + + gpio_set_value(S5PV210_GPH0(6), 0); + mdelay(10); + + gpio_set_value(S5PV210_GPH0(6), 1); + mdelay(10); + + gpio_free(S5PV210_GPH0(6)); + } else { +#if !defined(CONFIG_BACKLIGHT_PWM) + gpio_request(S5PV210_GPD0(3), "GPD0"); + gpio_direction_output(S5PV210_GPD0(3), 0); + gpio_free(S5PV210_GPD0(3)); +#endif + } +} + +static struct plat_lcd_data smdkv210_lcd_lte480wv_data = { + .set_power = smdkv210_lte480wv_set_power, +}; + +static struct platform_device smdkv210_lcd_lte480wv = { + .name = "platform-lcd", + .dev.parent = &s3c_device_fb.dev, + .dev.platform_data = &smdkv210_lcd_lte480wv_data, +}; + +static struct s3c_fb_pd_win smdkv210_fb_win0 = { + .win_mode = { + .left_margin = 13, + .right_margin = 8, + .upper_margin = 7, + .lower_margin = 5, + .hsync_len = 3, + .vsync_len = 1, + .xres = 800, + .yres = 480, + }, + .max_bpp = 32, + .default_bpp = 24, +}; + +static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = { + .win[0] = &smdkv210_fb_win0, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, + .setup_gpio = s5pv210_fb_gpio_setup_24bpp, +}; + static struct platform_device *smdkv210_devices[] __initdata = { - &s5pv210_device_iis0, - &s5pv210_device_ac97, - &s5pv210_device_spdif, &s3c_device_adc, &s3c_device_cfcon, + &s3c_device_fb, &s3c_device_hsmmc0, &s3c_device_hsmmc1, &s3c_device_hsmmc2, @@ -115,14 +219,38 @@ static struct platform_device *smdkv210_devices[] __initdata = { &s3c_device_i2c0, &s3c_device_i2c1, &s3c_device_i2c2, - &samsung_device_keypad, &s3c_device_rtc, &s3c_device_ts, &s3c_device_wdt, + &s5pv210_device_ac97, + &s5pv210_device_iis0, + &s5pv210_device_spdif, + &samsung_asoc_dma, + &samsung_device_keypad, + &smdkv210_dm9000, + &smdkv210_lcd_lte480wv, }; +static void __init smdkv210_dm9000_init(void) +{ + unsigned int tmp; + + gpio_request(S5PV210_MP01(5), "nCS5"); + s3c_gpio_cfgpin(S5PV210_MP01(5), S3C_GPIO_SFN(2)); + gpio_free(S5PV210_MP01(5)); + + tmp = (5 << S5P_SROM_BCX__TACC__SHIFT); + __raw_writel(tmp, S5P_SROM_BC5); + + tmp = __raw_readl(S5P_SROM_BW); + tmp &= (S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS5__SHIFT); + tmp |= (1 << S5P_SROM_BW__NCS5__SHIFT); + __raw_writel(tmp, S5P_SROM_BW); +} + static struct i2c_board_info smdkv210_i2c_devs0[] __initdata = { { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */ + { I2C_BOARD_INFO("wm8580", 0x1b), }, }; static struct i2c_board_info smdkv210_i2c_devs1[] __initdata = { @@ -150,6 +278,8 @@ static void __init smdkv210_machine_init(void) { s3c_pm_init(); + smdkv210_dm9000_init(); + samsung_keypad_set_platdata(&smdkv210_keypad_data); s3c24xx_ts_set_platdata(&s3c_ts_platform); @@ -165,6 +295,8 @@ static void __init smdkv210_machine_init(void) s3c_ide_set_platdata(&smdkv210_ide_pdata); + s3c_fb_set_platdata(&smdkv210_lcd0_pdata); + platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); } diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig index d64efe0d4c9..09c4c21b70c 100644 --- a/arch/arm/mach-s5pv310/Kconfig +++ b/arch/arm/mach-s5pv310/Kconfig @@ -15,6 +15,11 @@ config CPU_S5PV310 help Enable S5PV310 CPU support +config S5PV310_DEV_PD + bool + help + Compile in platform device definitions for Power Domain + config S5PV310_SETUP_I2C1 bool help @@ -61,6 +66,11 @@ config S5PV310_SETUP_SDHCI_GPIO help Common setup code for SDHCI gpio. +config S5PV310_DEV_SYSMMU + bool + help + Common setup code for SYSTEM MMU in S5PV310 + # machine support menu "S5PC210 Machines" @@ -70,11 +80,15 @@ config MACH_SMDKC210 select CPU_S5PV310 select S3C_DEV_RTC select S3C_DEV_WDT + select S3C_DEV_I2C1 select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 + select S5PV310_DEV_PD + select S5PV310_SETUP_I2C1 select S5PV310_SETUP_SDHCI + select S5PV310_DEV_SYSMMU help Machine support for Samsung SMDKC210 S5PC210(MCP) is one of package option of S5PV310 @@ -83,6 +97,10 @@ config MACH_UNIVERSAL_C210 bool "Mobile UNIVERSAL_C210 Board" select CPU_S5PV310 select S5P_DEV_ONENAND + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC2 + select S3C_DEV_HSMMC3 + select S5PV310_SETUP_SDHCI select S3C_DEV_I2C1 select S5PV310_SETUP_I2C1 help @@ -98,10 +116,13 @@ config MACH_SMDKV310 select CPU_S5PV310 select S3C_DEV_RTC select S3C_DEV_WDT + select S3C_DEV_I2C1 select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 + select S5PV310_DEV_PD + select S5PV310_SETUP_I2C1 select S5PV310_SETUP_SDHCI help Machine support for Samsung SMDKV310 diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile index 61e3cb65426..036fb383b83 100644 --- a/arch/arm/mach-s5pv310/Makefile +++ b/arch/arm/mach-s5pv310/Makefile @@ -14,6 +14,7 @@ obj- := obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o dma.o +obj-$(CONFIG_CPU_FREQ) += cpufreq.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o @@ -27,7 +28,10 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o # device support -obj-y += dev-audio.o +obj-y += dev-audio.o +obj-$(CONFIG_S5PV310_DEV_PD) += dev-pd.o +obj-$(CONFIG_S5PV310_DEV_SYSMMU) += dev-sysmmu.o + obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o obj-$(CONFIG_S5PV310_SETUP_I2C3) += setup-i2c3.o diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 58c9d33f36f..fc7c2f8d165 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -244,7 +244,7 @@ static struct clksrc_clk clk_mout_corebus = { .id = -1, }, .sources = &clkset_mout_corebus, - .reg_src = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 }, + .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, }; static struct clksrc_clk clk_sclk_dmc = { @@ -253,7 +253,7 @@ static struct clksrc_clk clk_sclk_dmc = { .id = -1, .parent = &clk_mout_corebus.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, }; static struct clksrc_clk clk_aclk_cored = { @@ -262,7 +262,7 @@ static struct clksrc_clk clk_aclk_cored = { .id = -1, .parent = &clk_sclk_dmc.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, }; static struct clksrc_clk clk_aclk_corep = { @@ -271,7 +271,7 @@ static struct clksrc_clk clk_aclk_corep = { .id = -1, .parent = &clk_aclk_cored.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, }; static struct clksrc_clk clk_aclk_acp = { @@ -280,7 +280,7 @@ static struct clksrc_clk clk_aclk_acp = { .id = -1, .parent = &clk_mout_corebus.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, }; static struct clksrc_clk clk_pclk_acp = { @@ -289,7 +289,7 @@ static struct clksrc_clk clk_pclk_acp = { .id = -1, .parent = &clk_aclk_acp.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, }; /* Core list of CMU_TOP side */ @@ -384,7 +384,7 @@ static struct clksrc_clk clk_sclk_vpll = { .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, }; -static struct clk init_clocks_disable[] = { +static struct clk init_clocks_off[] = { { .name = "timers", .id = -1, @@ -467,6 +467,16 @@ static struct clk init_clocks_disable[] = { .enable = s5pv310_clk_ip_fsys_ctrl, .ctrlbit = (1 << 10), }, { + .name = "pdma", + .id = 0, + .enable = s5pv310_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "pdma", + .id = 1, + .enable = s5pv310_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 1), + }, { .name = "adc", .id = -1, .enable = s5pv310_clk_ip_peril_ctrl, @@ -507,6 +517,26 @@ static struct clk init_clocks_disable[] = { .enable = s5pv310_clk_ip_peril_ctrl, .ctrlbit = (1 << 18), }, { + .name = "iis", + .id = 0, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 19), + }, { + .name = "iis", + .id = 1, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 20), + }, { + .name = "iis", + .id = 2, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 21), + }, { + .name = "ac97", + .id = -1, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 27), + }, { .name = "fimg2d", .id = -1, .enable = s5pv310_clk_ip_image_ctrl, @@ -990,6 +1020,17 @@ static struct clksrc_clk *sysclks[] = { &clk_dout_mmc4, }; +static int xtal_rate; + +static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk) +{ + return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508); +} + +static struct clk_ops s5pv310_fout_apll_ops = { + .get_rate = s5pv310_fout_apll_get_rate, +}; + void __init_or_cpufreq s5pv310_setup_clocks(void) { struct clk *xtal_clk; @@ -1013,6 +1054,9 @@ void __init_or_cpufreq s5pv310_setup_clocks(void) BUG_ON(IS_ERR(xtal_clk)); xtal = clk_get_rate(xtal_clk); + + xtal_rate = xtal; + clk_put(xtal_clk); printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); @@ -1026,7 +1070,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void) vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), __raw_readl(S5P_VPLL_CON1), pll_4650); - clk_fout_apll.rate = apll; + clk_fout_apll.ops = &s5pv310_fout_apll_ops; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; clk_fout_vpll.rate = vpll; @@ -1061,13 +1105,9 @@ static struct clk *clks[] __initdata = { void __init s5pv310_register_clocks(void) { - struct clk *clkp; - int ret; int ptr; - ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - if (ret > 0) - printk(KERN_ERR "Failed to register %u clocks\n", ret); + s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) s3c_register_clksrc(sysclks[ptr], 1); @@ -1075,15 +1115,8 @@ void __init s5pv310_register_clocks(void) s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - (clkp->enable)(clkp, 0); - } + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index 72ab289e781..0db0fb65bd7 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -41,6 +41,11 @@ static struct map_desc s5pv310_iodesc[] __initdata = { .length = SZ_128K, .type = MT_DEVICE, }, { + .virtual = (unsigned long)S5P_VA_PMU, + .pfn = __phys_to_pfn(S5PV310_PA_PMU), + .length = SZ_64K, + .type = MT_DEVICE, + }, { .virtual = (unsigned long)S5P_VA_COMBINER_BASE, .pfn = __phys_to_pfn(S5PV310_PA_COMBINER), .length = SZ_4K, @@ -71,6 +76,11 @@ static struct map_desc s5pv310_iodesc[] __initdata = { .length = SZ_256, .type = MT_DEVICE, }, { + .virtual = (unsigned long)S5P_VA_DMC0, + .pfn = __phys_to_pfn(S5PV310_PA_DMC0), + .length = SZ_4K, + .type = MT_DEVICE, + }, { .virtual = (unsigned long)S3C_VA_UART, .pfn = __phys_to_pfn(S3C_PA_UART), .length = SZ_512K, @@ -123,6 +133,15 @@ void __init s5pv310_init_irq(void) gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); for (irq = 0; irq < MAX_COMBINER_NR; irq++) { + + /* + * From SPI(0) to SPI(39) and SPI(51), SPI(53) are + * connected to the interrupt combiner. These irqs + * should be initialized to support cascade interrupt. + */ + if ((irq >= 40) && !(irq == 51) && !(irq == 53)) + continue; + combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), COMBINER_IRQ(irq, 0)); combiner_cascade_irq(irq, IRQ_SPI(irq)); @@ -164,7 +183,7 @@ static int __init s5pv310_l2x0_cache_init(void) __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, S5P_VA_L2CC + L2X0_POWER_CTRL); - l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff); + l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff); return 0; } diff --git a/arch/arm/mach-s5pv310/cpufreq.c b/arch/arm/mach-s5pv310/cpufreq.c new file mode 100644 index 00000000000..b04cbc73112 --- /dev/null +++ b/arch/arm/mach-s5pv310/cpufreq.c @@ -0,0 +1,580 @@ +/* linux/arch/arm/mach-s5pv310/cpufreq.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV310 - CPU frequency scaling support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/regulator/consumer.h> +#include <linux/cpufreq.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> +#include <mach/regs-mem.h> + +#include <plat/clock.h> +#include <plat/pm.h> + +static struct clk *cpu_clk; +static struct clk *moutcore; +static struct clk *mout_mpll; +static struct clk *mout_apll; + +#ifdef CONFIG_REGULATOR +static struct regulator *arm_regulator; +static struct regulator *int_regulator; +#endif + +static struct cpufreq_freqs freqs; +static unsigned int memtype; + +enum s5pv310_memory_type { + DDR2 = 4, + LPDDR2, + DDR3, +}; + +enum cpufreq_level_index { + L0, L1, L2, L3, CPUFREQ_LEVEL_END, +}; + +static struct cpufreq_frequency_table s5pv310_freq_table[] = { + {L0, 1000*1000}, + {L1, 800*1000}, + {L2, 400*1000}, + {L3, 100*1000}, + {0, CPUFREQ_TABLE_END}, +}; + +static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = { + /* + * Clock divider value for following + * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, + * DIVATB, DIVPCLK_DBG, DIVAPLL } + */ + + /* ARM L0: 1000MHz */ + { 0, 3, 7, 3, 3, 0, 1 }, + + /* ARM L1: 800MHz */ + { 0, 3, 7, 3, 3, 0, 1 }, + + /* ARM L2: 400MHz */ + { 0, 1, 3, 1, 3, 0, 1 }, + + /* ARM L3: 100MHz */ + { 0, 0, 1, 0, 3, 1, 1 }, +}; + +static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = { + /* + * Clock divider value for following + * { DIVCOPY, DIVHPM } + */ + + /* ARM L0: 1000MHz */ + { 3, 0 }, + + /* ARM L1: 800MHz */ + { 3, 0 }, + + /* ARM L2: 400MHz */ + { 3, 0 }, + + /* ARM L3: 100MHz */ + { 3, 0 }, +}; + +static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = { + /* + * Clock divider value for following + * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD + * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS } + */ + + /* DMC L0: 400MHz */ + { 3, 1, 1, 1, 1, 1, 3, 1 }, + + /* DMC L1: 400MHz */ + { 3, 1, 1, 1, 1, 1, 3, 1 }, + + /* DMC L2: 266.7MHz */ + { 7, 1, 1, 2, 1, 1, 3, 1 }, + + /* DMC L3: 200MHz */ + { 7, 1, 1, 3, 1, 1, 3, 1 }, +}; + +static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = { + /* + * Clock divider value for following + * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND } + */ + + /* ACLK200 L0: 200MHz */ + { 3, 7, 4, 5, 1 }, + + /* ACLK200 L1: 200MHz */ + { 3, 7, 4, 5, 1 }, + + /* ACLK200 L2: 160MHz */ + { 4, 7, 5, 7, 1 }, + + /* ACLK200 L3: 133.3MHz */ + { 5, 7, 7, 7, 1 }, +}; + +static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = { + /* + * Clock divider value for following + * { DIVGDL/R, DIVGPL/R } + */ + + /* ACLK_GDL/R L0: 200MHz */ + { 3, 1 }, + + /* ACLK_GDL/R L1: 200MHz */ + { 3, 1 }, + + /* ACLK_GDL/R L2: 160MHz */ + { 4, 1 }, + + /* ACLK_GDL/R L3: 133.3MHz */ + { 5, 1 }, +}; + +struct cpufreq_voltage_table { + unsigned int index; /* any */ + unsigned int arm_volt; /* uV */ + unsigned int int_volt; +}; + +static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = { + { + .index = L0, + .arm_volt = 1200000, + .int_volt = 1100000, + }, { + .index = L1, + .arm_volt = 1100000, + .int_volt = 1100000, + }, { + .index = L2, + .arm_volt = 1000000, + .int_volt = 1000000, + }, { + .index = L3, + .arm_volt = 900000, + .int_volt = 1000000, + }, +}; + +static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = { + /* APLL FOUT L0: 1000MHz */ + ((250 << 16) | (6 << 8) | 1), + + /* APLL FOUT L1: 800MHz */ + ((200 << 16) | (6 << 8) | 1), + + /* APLL FOUT L2 : 400MHz */ + ((200 << 16) | (6 << 8) | 2), + + /* APLL FOUT L3: 100MHz */ + ((200 << 16) | (6 << 8) | 4), +}; + +int s5pv310_verify_speed(struct cpufreq_policy *policy) +{ + return cpufreq_frequency_table_verify(policy, s5pv310_freq_table); +} + +unsigned int s5pv310_getspeed(unsigned int cpu) +{ + return clk_get_rate(cpu_clk) / 1000; +} + +void s5pv310_set_clkdiv(unsigned int div_index) +{ + unsigned int tmp; + + /* Change Divider - CPU0 */ + + tmp = __raw_readl(S5P_CLKDIV_CPU); + + tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK | + S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK | + S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK | + S5P_CLKDIV_CPU0_APLL_MASK); + + tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) | + (clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) | + (clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) | + (clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) | + (clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) | + (clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) | + (clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT)); + + __raw_writel(tmp, S5P_CLKDIV_CPU); + + do { + tmp = __raw_readl(S5P_CLKDIV_STATCPU); + } while (tmp & 0x1111111); + + /* Change Divider - CPU1 */ + + tmp = __raw_readl(S5P_CLKDIV_CPU1); + + tmp &= ~((0x7 << 4) | 0x7); + + tmp |= ((clkdiv_cpu1[div_index][0] << 4) | + (clkdiv_cpu1[div_index][1] << 0)); + + __raw_writel(tmp, S5P_CLKDIV_CPU1); + + do { + tmp = __raw_readl(S5P_CLKDIV_STATCPU1); + } while (tmp & 0x11); + + /* Change Divider - DMC0 */ + + tmp = __raw_readl(S5P_CLKDIV_DMC0); + + tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK | + S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK | + S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK | + S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK); + + tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) | + (clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) | + (clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) | + (clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) | + (clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) | + (clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) | + (clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) | + (clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT)); + + __raw_writel(tmp, S5P_CLKDIV_DMC0); + + do { + tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0); + } while (tmp & 0x11111111); + + /* Change Divider - TOP */ + + tmp = __raw_readl(S5P_CLKDIV_TOP); + + tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK | + S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK | + S5P_CLKDIV_TOP_ONENAND_MASK); + + tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) | + (clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) | + (clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) | + (clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) | + (clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT)); + + __raw_writel(tmp, S5P_CLKDIV_TOP); + + do { + tmp = __raw_readl(S5P_CLKDIV_STAT_TOP); + } while (tmp & 0x11111); + + /* Change Divider - LEFTBUS */ + + tmp = __raw_readl(S5P_CLKDIV_LEFTBUS); + + tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK); + + tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) | + (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT)); + + __raw_writel(tmp, S5P_CLKDIV_LEFTBUS); + + do { + tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS); + } while (tmp & 0x11); + + /* Change Divider - RIGHTBUS */ + + tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS); + + tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK); + + tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) | + (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT)); + + __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS); + + do { + tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS); + } while (tmp & 0x11); +} + +static void s5pv310_set_apll(unsigned int index) +{ + unsigned int tmp; + + /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ + clk_set_parent(moutcore, mout_mpll); + + do { + tmp = (__raw_readl(S5P_CLKMUX_STATCPU) + >> S5P_CLKSRC_CPU_MUXCORE_SHIFT); + tmp &= 0x7; + } while (tmp != 0x2); + + /* 2. Set APLL Lock time */ + __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK); + + /* 3. Change PLL PMS values */ + tmp = __raw_readl(S5P_APLL_CON0); + tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); + tmp |= s5pv310_apll_pms_table[index]; + __raw_writel(tmp, S5P_APLL_CON0); + + /* 4. wait_lock_time */ + do { + tmp = __raw_readl(S5P_APLL_CON0); + } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT))); + + /* 5. MUX_CORE_SEL = APLL */ + clk_set_parent(moutcore, mout_apll); + + do { + tmp = __raw_readl(S5P_CLKMUX_STATCPU); + tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK; + } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)); +} + +static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index) +{ + unsigned int tmp; + + if (old_index > new_index) { + /* The frequency changing to L0 needs to change apll */ + if (freqs.new == s5pv310_freq_table[L0].frequency) { + /* 1. Change the system clock divider values */ + s5pv310_set_clkdiv(new_index); + + /* 2. Change the apll m,p,s value */ + s5pv310_set_apll(new_index); + } else { + /* 1. Change the system clock divider values */ + s5pv310_set_clkdiv(new_index); + + /* 2. Change just s value in apll m,p,s value */ + tmp = __raw_readl(S5P_APLL_CON0); + tmp &= ~(0x7 << 0); + tmp |= (s5pv310_apll_pms_table[new_index] & 0x7); + __raw_writel(tmp, S5P_APLL_CON0); + } + } + + else if (old_index < new_index) { + /* The frequency changing from L0 needs to change apll */ + if (freqs.old == s5pv310_freq_table[L0].frequency) { + /* 1. Change the apll m,p,s value */ + s5pv310_set_apll(new_index); + + /* 2. Change the system clock divider values */ + s5pv310_set_clkdiv(new_index); + } else { + /* 1. Change just s value in apll m,p,s value */ + tmp = __raw_readl(S5P_APLL_CON0); + tmp &= ~(0x7 << 0); + tmp |= (s5pv310_apll_pms_table[new_index] & 0x7); + __raw_writel(tmp, S5P_APLL_CON0); + + /* 2. Change the system clock divider values */ + s5pv310_set_clkdiv(new_index); + } + } +} + +static int s5pv310_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + unsigned int index, old_index; + unsigned int arm_volt, int_volt; + + freqs.old = s5pv310_getspeed(policy->cpu); + + if (cpufreq_frequency_table_target(policy, s5pv310_freq_table, + freqs.old, relation, &old_index)) + return -EINVAL; + + if (cpufreq_frequency_table_target(policy, s5pv310_freq_table, + target_freq, relation, &index)) + return -EINVAL; + + freqs.new = s5pv310_freq_table[index].frequency; + freqs.cpu = policy->cpu; + + if (freqs.new == freqs.old) + return 0; + + /* get the voltage value */ + arm_volt = s5pv310_volt_table[index].arm_volt; + int_volt = s5pv310_volt_table[index].int_volt; + + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + + /* control regulator */ + if (freqs.new > freqs.old) { + /* Voltage up */ +#ifdef CONFIG_REGULATOR + regulator_set_voltage(arm_regulator, arm_volt, arm_volt); + regulator_set_voltage(int_regulator, int_volt, int_volt); +#endif + } + + /* Clock Configuration Procedure */ + s5pv310_set_frequency(old_index, index); + + /* control regulator */ + if (freqs.new < freqs.old) { + /* Voltage down */ +#ifdef CONFIG_REGULATOR + regulator_set_voltage(arm_regulator, arm_volt, arm_volt); + regulator_set_voltage(int_regulator, int_volt, int_volt); +#endif + } + + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return 0; +} + +#ifdef CONFIG_PM +static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy, + pm_message_t pmsg) +{ + return 0; +} + +static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy) +{ + return 0; +} +#endif + +static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy) +{ + policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu); + + cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu); + + /* set the transition latency value */ + policy->cpuinfo.transition_latency = 100000; + + /* + * S5PV310 multi-core processors has 2 cores + * that the frequency cannot be set independently. + * Each cpu is bound to the same speed. + * So the affected cpu is all of the cpus. + */ + cpumask_setall(policy->cpus); + + return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table); +} + +static struct cpufreq_driver s5pv310_driver = { + .flags = CPUFREQ_STICKY, + .verify = s5pv310_verify_speed, + .target = s5pv310_target, + .get = s5pv310_getspeed, + .init = s5pv310_cpufreq_cpu_init, + .name = "s5pv310_cpufreq", +#ifdef CONFIG_PM + .suspend = s5pv310_cpufreq_suspend, + .resume = s5pv310_cpufreq_resume, +#endif +}; + +static int __init s5pv310_cpufreq_init(void) +{ + cpu_clk = clk_get(NULL, "armclk"); + if (IS_ERR(cpu_clk)) + return PTR_ERR(cpu_clk); + + moutcore = clk_get(NULL, "moutcore"); + if (IS_ERR(moutcore)) + goto out; + + mout_mpll = clk_get(NULL, "mout_mpll"); + if (IS_ERR(mout_mpll)) + goto out; + + mout_apll = clk_get(NULL, "mout_apll"); + if (IS_ERR(mout_apll)) + goto out; + +#ifdef CONFIG_REGULATOR + arm_regulator = regulator_get(NULL, "vdd_arm"); + if (IS_ERR(arm_regulator)) { + printk(KERN_ERR "failed to get resource %s\n", "vdd_arm"); + goto out; + } + + int_regulator = regulator_get(NULL, "vdd_int"); + if (IS_ERR(int_regulator)) { + printk(KERN_ERR "failed to get resource %s\n", "vdd_int"); + goto out; + } +#endif + + /* + * Check DRAM type. + * Because DVFS level is different according to DRAM type. + */ + memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET); + memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT); + memtype &= S5P_DMC0_MEMTYPE_MASK; + + if ((memtype < DDR2) && (memtype > DDR3)) { + printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype); + goto out; + } else { + printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype); + } + + return cpufreq_register_driver(&s5pv310_driver); + +out: + if (!IS_ERR(cpu_clk)) + clk_put(cpu_clk); + + if (!IS_ERR(moutcore)) + clk_put(moutcore); + + if (!IS_ERR(mout_mpll)) + clk_put(mout_mpll); + + if (!IS_ERR(mout_apll)) + clk_put(mout_apll); + +#ifdef CONFIG_REGULATOR + if (!IS_ERR(arm_regulator)) + regulator_put(arm_regulator); + + if (!IS_ERR(int_regulator)) + regulator_put(int_regulator); +#endif + + printk(KERN_ERR "%s: failed initialization\n", __func__); + + return -EINVAL; +} +late_initcall(s5pv310_cpufreq_init); diff --git a/arch/arm/mach-s5pv310/dev-pd.c b/arch/arm/mach-s5pv310/dev-pd.c new file mode 100644 index 00000000000..58a50c2d0b6 --- /dev/null +++ b/arch/arm/mach-s5pv310/dev-pd.c @@ -0,0 +1,139 @@ +/* linux/arch/arm/mach-s5pv310/dev-pd.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV310 - Power Domain support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/delay.h> + +#include <mach/regs-pmu.h> + +#include <plat/pd.h> + +static int s5pv310_pd_enable(struct device *dev) +{ + struct samsung_pd_info *pdata = dev->platform_data; + u32 timeout; + + __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base); + + /* Wait max 1ms */ + timeout = 10; + while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) + != S5P_INT_LOCAL_PWR_EN) { + if (timeout == 0) { + printk(KERN_ERR "Power domain %s enable failed.\n", + dev_name(dev)); + return -ETIMEDOUT; + } + timeout--; + udelay(100); + } + + return 0; +} + +static int s5pv310_pd_disable(struct device *dev) +{ + struct samsung_pd_info *pdata = dev->platform_data; + u32 timeout; + + __raw_writel(0, pdata->base); + + /* Wait max 1ms */ + timeout = 10; + while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) { + if (timeout == 0) { + printk(KERN_ERR "Power domain %s disable failed.\n", + dev_name(dev)); + return -ETIMEDOUT; + } + timeout--; + udelay(100); + } + + return 0; +} + +struct platform_device s5pv310_device_pd[] = { + { + .name = "samsung-pd", + .id = 0, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = s5pv310_pd_enable, + .disable = s5pv310_pd_disable, + .base = S5P_PMU_MFC_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 1, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = s5pv310_pd_enable, + .disable = s5pv310_pd_disable, + .base = S5P_PMU_G3D_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 2, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = s5pv310_pd_enable, + .disable = s5pv310_pd_disable, + .base = S5P_PMU_LCD0_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 3, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = s5pv310_pd_enable, + .disable = s5pv310_pd_disable, + .base = S5P_PMU_LCD1_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 4, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = s5pv310_pd_enable, + .disable = s5pv310_pd_disable, + .base = S5P_PMU_TV_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 5, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = s5pv310_pd_enable, + .disable = s5pv310_pd_disable, + .base = S5P_PMU_CAM_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 6, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = s5pv310_pd_enable, + .disable = s5pv310_pd_disable, + .base = S5P_PMU_GPS_CONF, + }, + }, + }, +}; diff --git a/arch/arm/mach-s5pv310/dev-sysmmu.c b/arch/arm/mach-s5pv310/dev-sysmmu.c new file mode 100644 index 00000000000..e1bb200ac0f --- /dev/null +++ b/arch/arm/mach-s5pv310/dev-sysmmu.c @@ -0,0 +1,187 @@ +/* linux/arch/arm/mach-s5pv310/dev-sysmmu.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <mach/map.h> +#include <mach/irqs.h> + +static struct resource s5pv310_sysmmu_resource[] = { + [0] = { + .start = S5PV310_PA_SYSMMU_MDMA, + .end = S5PV310_PA_SYSMMU_MDMA + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SYSMMU_MDMA0_0, + .end = IRQ_SYSMMU_MDMA0_0, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = S5PV310_PA_SYSMMU_SSS, + .end = S5PV310_PA_SYSMMU_SSS + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = IRQ_SYSMMU_SSS_0, + .end = IRQ_SYSMMU_SSS_0, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = S5PV310_PA_SYSMMU_FIMC0, + .end = S5PV310_PA_SYSMMU_FIMC0 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [5] = { + .start = IRQ_SYSMMU_FIMC0_0, + .end = IRQ_SYSMMU_FIMC0_0, + .flags = IORESOURCE_IRQ, + }, + [6] = { + .start = S5PV310_PA_SYSMMU_FIMC1, + .end = S5PV310_PA_SYSMMU_FIMC1 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [7] = { + .start = IRQ_SYSMMU_FIMC1_0, + .end = IRQ_SYSMMU_FIMC1_0, + .flags = IORESOURCE_IRQ, + }, + [8] = { + .start = S5PV310_PA_SYSMMU_FIMC2, + .end = S5PV310_PA_SYSMMU_FIMC2 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [9] = { + .start = IRQ_SYSMMU_FIMC2_0, + .end = IRQ_SYSMMU_FIMC2_0, + .flags = IORESOURCE_IRQ, + }, + [10] = { + .start = S5PV310_PA_SYSMMU_FIMC3, + .end = S5PV310_PA_SYSMMU_FIMC3 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [11] = { + .start = IRQ_SYSMMU_FIMC3_0, + .end = IRQ_SYSMMU_FIMC3_0, + .flags = IORESOURCE_IRQ, + }, + [12] = { + .start = S5PV310_PA_SYSMMU_JPEG, + .end = S5PV310_PA_SYSMMU_JPEG + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [13] = { + .start = IRQ_SYSMMU_JPEG_0, + .end = IRQ_SYSMMU_JPEG_0, + .flags = IORESOURCE_IRQ, + }, + [14] = { + .start = S5PV310_PA_SYSMMU_FIMD0, + .end = S5PV310_PA_SYSMMU_FIMD0 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [15] = { + .start = IRQ_SYSMMU_LCD0_M0_0, + .end = IRQ_SYSMMU_LCD0_M0_0, + .flags = IORESOURCE_IRQ, + }, + [16] = { + .start = S5PV310_PA_SYSMMU_FIMD1, + .end = S5PV310_PA_SYSMMU_FIMD1 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [17] = { + .start = IRQ_SYSMMU_LCD1_M1_0, + .end = IRQ_SYSMMU_LCD1_M1_0, + .flags = IORESOURCE_IRQ, + }, + [18] = { + .start = S5PV310_PA_SYSMMU_PCIe, + .end = S5PV310_PA_SYSMMU_PCIe + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [19] = { + .start = IRQ_SYSMMU_PCIE_0, + .end = IRQ_SYSMMU_PCIE_0, + .flags = IORESOURCE_IRQ, + }, + [20] = { + .start = S5PV310_PA_SYSMMU_G2D, + .end = S5PV310_PA_SYSMMU_G2D + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [21] = { + .start = IRQ_SYSMMU_2D_0, + .end = IRQ_SYSMMU_2D_0, + .flags = IORESOURCE_IRQ, + }, + [22] = { + .start = S5PV310_PA_SYSMMU_ROTATOR, + .end = S5PV310_PA_SYSMMU_ROTATOR + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [23] = { + .start = IRQ_SYSMMU_ROTATOR_0, + .end = IRQ_SYSMMU_ROTATOR_0, + .flags = IORESOURCE_IRQ, + }, + [24] = { + .start = S5PV310_PA_SYSMMU_MDMA2, + .end = S5PV310_PA_SYSMMU_MDMA2 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [25] = { + .start = IRQ_SYSMMU_MDMA1_0, + .end = IRQ_SYSMMU_MDMA1_0, + .flags = IORESOURCE_IRQ, + }, + [26] = { + .start = S5PV310_PA_SYSMMU_TV, + .end = S5PV310_PA_SYSMMU_TV + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [27] = { + .start = IRQ_SYSMMU_TV_M0_0, + .end = IRQ_SYSMMU_TV_M0_0, + .flags = IORESOURCE_IRQ, + }, + [28] = { + .start = S5PV310_PA_SYSMMU_MFC_L, + .end = S5PV310_PA_SYSMMU_MFC_L + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [29] = { + .start = IRQ_SYSMMU_MFC_M0_0, + .end = IRQ_SYSMMU_MFC_M0_0, + .flags = IORESOURCE_IRQ, + }, + [30] = { + .start = S5PV310_PA_SYSMMU_MFC_R, + .end = S5PV310_PA_SYSMMU_MFC_R + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [31] = { + .start = IRQ_SYSMMU_MFC_M1_0, + .end = IRQ_SYSMMU_MFC_M1_0, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s5pv310_device_sysmmu = { + .name = "s5p-sysmmu", + .id = 32, + .num_resources = ARRAY_SIZE(s5pv310_sysmmu_resource), + .resource = s5pv310_sysmmu_resource, +}; + +EXPORT_SYMBOL(s5pv310_device_sysmmu); diff --git a/arch/arm/mach-s5pv310/hotplug.c b/arch/arm/mach-s5pv310/hotplug.c index afa5392d9fc..c24235c89ee 100644 --- a/arch/arm/mach-s5pv310/hotplug.c +++ b/arch/arm/mach-s5pv310/hotplug.c @@ -30,10 +30,10 @@ static inline void cpu_enter_lowpower(void) * Turn off coherency */ " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, %2\n" + " bic %0, %0, #0x20\n" " mcr p15, 0, %0, c1, c0, 1\n" " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, #0x04\n" + " bic %0, %0, %2\n" " mcr p15, 0, %0, c1, c0, 0\n" : "=&r" (v) : "r" (0), "Ir" (CR_C) diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h index 3c05c58b539..536b0b59fc8 100644 --- a/arch/arm/mach-s5pv310/include/mach/irqs.h +++ b/arch/arm/mach-s5pv310/include/mach/irqs.h @@ -25,6 +25,8 @@ #define IRQ_SPI(x) S5P_IRQ(x+32) +#define IRQ_MCT1 IRQ_SPI(35) + #define IRQ_EINT0 IRQ_SPI(40) #define IRQ_EINT1 IRQ_SPI(41) #define IRQ_EINT2 IRQ_SPI(42) @@ -36,9 +38,8 @@ #define IRQ_JPEG IRQ_SPI(48) #define IRQ_2D IRQ_SPI(49) #define IRQ_PCIE IRQ_SPI(50) -#define IRQ_SYSTEM_TIMER IRQ_SPI(51) +#define IRQ_MCT0 IRQ_SPI(51) #define IRQ_MFC IRQ_SPI(52) -#define IRQ_WDT IRQ_SPI(53) #define IRQ_AUDIO_SS IRQ_SPI(54) #define IRQ_AC97 IRQ_SPI(55) #define IRQ_SPDIF IRQ_SPI(56) @@ -54,6 +55,24 @@ #define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64)) #define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) +#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) +#define IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1) +#define IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2) +#define IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3) +#define IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4) +#define IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5) +#define IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6) +#define IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7) + +#define IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0) +#define IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1) +#define IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2) +#define IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3) +#define IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4) +#define IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5) +#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) +#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) + #define IRQ_PDMA0 COMBINER_IRQ(21, 0) #define IRQ_PDMA1 COMBINER_IRQ(21, 1) @@ -86,8 +105,13 @@ #define IRQ_HSMMC2 COMBINER_IRQ(29, 2) #define IRQ_HSMMC3 COMBINER_IRQ(29, 3) +#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0) +#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1) + #define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) +#define IRQ_MCT_L1 COMBINER_IRQ(35, 3) + #define IRQ_EINT4 COMBINER_IRQ(37, 0) #define IRQ_EINT5 COMBINER_IRQ(37, 1) #define IRQ_EINT6 COMBINER_IRQ(37, 2) @@ -104,7 +128,11 @@ #define IRQ_EINT16_31 COMBINER_IRQ(39, 0) -#define MAX_COMBINER_NR 40 +#define IRQ_MCT_L0 COMBINER_IRQ(51, 0) + +#define IRQ_WDT COMBINER_IRQ(53, 0) + +#define MAX_COMBINER_NR 54 #define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h index 53994467605..74d400625a2 100644 --- a/arch/arm/mach-s5pv310/include/mach/map.h +++ b/arch/arm/mach-s5pv310/include/mach/map.h @@ -39,11 +39,15 @@ #define S5PV310_PA_SYSCON (0x10010000) #define S5P_PA_SYSCON S5PV310_PA_SYSCON +#define S5PV310_PA_PMU (0x10020000) + #define S5PV310_PA_CMU (0x10030000) #define S5PV310_PA_WATCHDOG (0x10060000) #define S5PV310_PA_RTC (0x10070000) +#define S5PV310_PA_DMC0 (0x10400000) + #define S5PV310_PA_COMBINER (0x10448000) #define S5PV310_PA_COREPERI (0x10500000) @@ -61,9 +65,13 @@ #define S5PV310_PA_GPIO2 (0x11000000) #define S5PV310_PA_GPIO3 (0x03860000) +#define S5PV310_PA_MIPI_CSIS0 0x11880000 +#define S5PV310_PA_MIPI_CSIS1 0x11890000 + #define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) #define S5PV310_PA_SROMC (0x12570000) +#define S5P_PA_SROMC S5PV310_PA_SROMC /* S/PDIF */ #define S5PV310_PA_SPDIF 0xE1100000 @@ -100,6 +108,25 @@ #define S5PV310_PA_SDRAM (0x40000000) #define S5P_PA_SDRAM S5PV310_PA_SDRAM +#define S5PV310_PA_SYSMMU_MDMA 0x10A40000 +#define S5PV310_PA_SYSMMU_SSS 0x10A50000 +#define S5PV310_PA_SYSMMU_FIMC0 0x11A20000 +#define S5PV310_PA_SYSMMU_FIMC1 0x11A30000 +#define S5PV310_PA_SYSMMU_FIMC2 0x11A40000 +#define S5PV310_PA_SYSMMU_FIMC3 0x11A50000 +#define S5PV310_PA_SYSMMU_JPEG 0x11A60000 +#define S5PV310_PA_SYSMMU_FIMD0 0x11E20000 +#define S5PV310_PA_SYSMMU_FIMD1 0x12220000 +#define S5PV310_PA_SYSMMU_PCIe 0x12620000 +#define S5PV310_PA_SYSMMU_G2D 0x12A20000 +#define S5PV310_PA_SYSMMU_ROTATOR 0x12A30000 +#define S5PV310_PA_SYSMMU_MDMA2 0x12A40000 +#define S5PV310_PA_SYSMMU_TV 0x12E20000 +#define S5PV310_PA_SYSMMU_MFC_L 0x13620000 +#define S5PV310_PA_SYSMMU_MFC_R 0x13630000 +#define S5PV310_SYSMMU_TOTAL_IPNUM 16 +#define S5P_SYSMMU_TOTAL_IPNUM S5PV310_SYSMMU_TOTAL_IPNUM + /* compatibiltiy defines. */ #define S3C_PA_UART S5PV310_PA_UART #define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0) @@ -116,5 +143,7 @@ #define S3C_PA_IIC7 S5PV310_PA_IIC(7) #define S3C_PA_RTC S5PV310_PA_RTC #define S3C_PA_WDT S5PV310_PA_WATCHDOG +#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0 +#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1 #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h index f1028cad978..b5c4ada1cff 100644 --- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h @@ -19,6 +19,12 @@ #define S5P_INFORM0 S5P_CLKREG(0x800) +#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500) +#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600) + +#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500) +#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) + #define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) #define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) #define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) @@ -58,6 +64,8 @@ #define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) #define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) +#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) + #define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) #define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) #define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) @@ -66,8 +74,9 @@ #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) #define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) -#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200) -#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500) +#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200) +#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500) +#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600) #define S5P_APLL_LOCK S5P_CLKREG(0x14000) #define S5P_MPLL_LOCK S5P_CLKREG(0x14004) @@ -80,10 +89,77 @@ #define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) #define S5P_CLKDIV_CPU S5P_CLKREG(0x14500) +#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504) #define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600) +#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604) #define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) +/* APLL_LOCK */ +#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */ + +/* APLL_CON0 */ +#define S5P_APLLCON0_ENABLE_SHIFT (31) +#define S5P_APLLCON0_LOCKED_SHIFT (29) +#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) +#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) + +/* CLK_SRC_CPU */ +#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) +#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) + +/* CLKDIV_CPU0 */ +#define S5P_CLKDIV_CPU0_CORE_SHIFT (0) +#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT) +#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4) +#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT) +#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8) +#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT) +#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12) +#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT) +#define S5P_CLKDIV_CPU0_ATB_SHIFT (16) +#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT) +#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20) +#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) +#define S5P_CLKDIV_CPU0_APLL_SHIFT (24) +#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT) + +/* CLKDIV_DMC0 */ +#define S5P_CLKDIV_DMC0_ACP_SHIFT (0) +#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT) +#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4) +#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) +#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8) +#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT) +#define S5P_CLKDIV_DMC0_DMC_SHIFT (12) +#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT) +#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16) +#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT) +#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20) +#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT) +#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24) +#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT) +#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28) +#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT) + +/* CLKDIV_TOP */ +#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0) +#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT) +#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4) +#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT) +#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8) +#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT) +#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12) +#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT) +#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16) +#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT) + +/* CLKDIV_LEFTBUS / CLKDIV_RIGHTBUS*/ +#define S5P_CLKDIV_BUS_GDLR_SHIFT (0) +#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT) +#define S5P_CLKDIV_BUS_GPLR_SHIFT (4) +#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) + /* Compatibility defines */ #define S5P_EPLL_CON S5P_EPLL_CON0 diff --git a/arch/arm/mach-s5pv310/include/mach/regs-mem.h b/arch/arm/mach-s5pv310/include/mach/regs-mem.h new file mode 100644 index 00000000000..834227140ea --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/regs-mem.h @@ -0,0 +1,23 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV310 - SROMC and DMC register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_MEM_H +#define __ASM_ARCH_REGS_MEM_H __FILE__ + +#include <mach/map.h> + +#define S5P_DMC0_MEMCON_OFFSET 0x04 + +#define S5P_DMC0_MEMTYPE_SHIFT 8 +#define S5P_DMC0_MEMTYPE_MASK 0xF + +#endif /* __ASM_ARCH_REGS_MEM_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h b/arch/arm/mach-s5pv310/include/mach/regs-pmu.h new file mode 100644 index 00000000000..fb333d0f607 --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/regs-pmu.h @@ -0,0 +1,30 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/regs-pmu.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV310 - Power management unit definition + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_PMU_H +#define __ASM_ARCH_REGS_PMU_H __FILE__ + +#include <mach/map.h> + +#define S5P_PMUREG(x) (S5P_VA_PMU + (x)) + +#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) +#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) +#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) +#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) +#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) +#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) +#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) + +#define S5P_INT_LOCAL_PWR_EN 0x7 + +#endif /* __ASM_ARCH_REGS_PMU_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/regs-srom.h b/arch/arm/mach-s5pv310/include/mach/regs-srom.h deleted file mode 100644 index 1898b3e1055..00000000000 --- a/arch/arm/mach-s5pv310/include/mach/regs-srom.h +++ /dev/null @@ -1,50 +0,0 @@ -/* linux/arch/arm/mach-s5pv310/include/mach/regs-srom.h - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * S5PV310 - SROMC register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_REGS_SROM_H -#define __ASM_ARCH_REGS_SROM_H __FILE__ - -#include <mach/map.h> - -#define S5PV310_SROMREG(x) (S5P_VA_SROMC + (x)) - -#define S5PV310_SROM_BW S5PV310_SROMREG(0x0) -#define S5PV310_SROM_BC0 S5PV310_SROMREG(0x4) -#define S5PV310_SROM_BC1 S5PV310_SROMREG(0x8) -#define S5PV310_SROM_BC2 S5PV310_SROMREG(0xc) -#define S5PV310_SROM_BC3 S5PV310_SROMREG(0x10) - -/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ - -#define S5PV310_SROM_BW__DATAWIDTH__SHIFT 0 -#define S5PV310_SROM_BW__ADDRMODE__SHIFT 1 -#define S5PV310_SROM_BW__WAITENABLE__SHIFT 2 -#define S5PV310_SROM_BW__BYTEENABLE__SHIFT 3 - -#define S5PV310_SROM_BW__CS_MASK 0xf - -#define S5PV310_SROM_BW__NCS0__SHIFT 0 -#define S5PV310_SROM_BW__NCS1__SHIFT 4 -#define S5PV310_SROM_BW__NCS2__SHIFT 8 -#define S5PV310_SROM_BW__NCS3__SHIFT 12 - -/* applies to same to BCS0 - BCS3 */ - -#define S5PV310_SROM_BCX__PMC__SHIFT 0 -#define S5PV310_SROM_BCX__TACP__SHIFT 4 -#define S5PV310_SROM_BCX__TCAH__SHIFT 8 -#define S5PV310_SROM_BCX__TCOH__SHIFT 12 -#define S5PV310_SROM_BCX__TACC__SHIFT 16 -#define S5PV310_SROM_BCX__TCOS__SHIFT 24 -#define S5PV310_SROM_BCX__TACS__SHIFT 28 - -#endif /* __ASM_ARCH_REGS_SROM_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h b/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h new file mode 100644 index 00000000000..0b28e81a16f --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h @@ -0,0 +1,24 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV310 - System MMU register + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_SYSMMU_H +#define __ASM_ARCH_REGS_SYSMMU_H __FILE__ + +#define S5P_MMU_CTRL 0x000 +#define S5P_MMU_CFG 0x004 +#define S5P_MMU_STATUS 0x008 +#define S5P_MMU_FLUSH 0x00C +#define S5P_PT_BASE_ADDR 0x014 +#define S5P_INT_STATUS 0x018 +#define S5P_PAGE_FAULT_ADDR 0x024 + +#endif /* __ASM_ARCH_REGS_SYSMMU_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/sysmmu.h b/arch/arm/mach-s5pv310/include/mach/sysmmu.h new file mode 100644 index 00000000000..662fe85ff4d --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/sysmmu.h @@ -0,0 +1,119 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/sysmmu.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Samsung sysmmu driver for S5PV310 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARM_ARCH_SYSMMU_H +#define __ASM_ARM_ARCH_SYSMMU_H __FILE__ + +enum s5pv310_sysmmu_ips { + SYSMMU_MDMA, + SYSMMU_SSS, + SYSMMU_FIMC0, + SYSMMU_FIMC1, + SYSMMU_FIMC2, + SYSMMU_FIMC3, + SYSMMU_JPEG, + SYSMMU_FIMD0, + SYSMMU_FIMD1, + SYSMMU_PCIe, + SYSMMU_G2D, + SYSMMU_ROTATOR, + SYSMMU_MDMA2, + SYSMMU_TV, + SYSMMU_MFC_L, + SYSMMU_MFC_R, +}; + +static char *sysmmu_ips_name[S5P_SYSMMU_TOTAL_IPNUM] = { + "SYSMMU_MDMA" , + "SYSMMU_SSS" , + "SYSMMU_FIMC0" , + "SYSMMU_FIMC1" , + "SYSMMU_FIMC2" , + "SYSMMU_FIMC3" , + "SYSMMU_JPEG" , + "SYSMMU_FIMD0" , + "SYSMMU_FIMD1" , + "SYSMMU_PCIe" , + "SYSMMU_G2D" , + "SYSMMU_ROTATOR", + "SYSMMU_MDMA2" , + "SYSMMU_TV" , + "SYSMMU_MFC_L" , + "SYSMMU_MFC_R" , +}; + +typedef enum s5pv310_sysmmu_ips sysmmu_ips; + +struct sysmmu_tt_info { + unsigned long *pgd; + unsigned long pgd_paddr; + unsigned long *pte; +}; + +struct sysmmu_controller { + const char *name; + + /* channels registers */ + void __iomem *regs; + + /* channel irq */ + unsigned int irq; + + sysmmu_ips ips; + + /* Translation Table Info. */ + struct sysmmu_tt_info *tt_info; + + struct resource *mem; + struct device *dev; + + /* SysMMU controller enable - true : enable */ + bool enable; +}; + +/** + * s5p_sysmmu_enable() - enable system mmu of ip + * @ips: The ip connected system mmu. + * + * This function enable system mmu to transfer address + * from virtual address to physical address + */ +int s5p_sysmmu_enable(sysmmu_ips ips); + +/** + * s5p_sysmmu_disable() - disable sysmmu mmu of ip + * @ips: The ip connected system mmu. + * + * This function disable system mmu to transfer address + * from virtual address to physical address + */ +int s5p_sysmmu_disable(sysmmu_ips ips); + +/** + * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table + * @ips: The ip connected system mmu. + * @pgd: The page table base address. + * + * This function set page table base address + * When system mmu transfer address from virtaul address to physical address, + * system mmu refer address information from page table + */ +int s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd); + +/** + * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu + * @ips: The ip connected system mmu. + * + * This function flush all TLB entry in system mmu + */ +int s5p_sysmmu_tlb_invalidate(sysmmu_ips ips); +#endif /* __ASM_ARM_ARCH_SYSMMU_H */ diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c index c3f88c3faf6..1ea4a9e83bb 100644 --- a/arch/arm/mach-s5pv310/irq-combiner.c +++ b/arch/arm/mach-s5pv310/irq-combiner.c @@ -24,29 +24,32 @@ static DEFINE_SPINLOCK(irq_controller_lock); struct combiner_chip_data { unsigned int irq_offset; + unsigned int irq_mask; void __iomem *base; }; static struct combiner_chip_data combiner_data[MAX_COMBINER_NR]; -static inline void __iomem *combiner_base(unsigned int irq) +static inline void __iomem *combiner_base(struct irq_data *data) { - struct combiner_chip_data *combiner_data = get_irq_chip_data(irq); + struct combiner_chip_data *combiner_data = + irq_data_get_irq_chip_data(data); + return combiner_data->base; } -static void combiner_mask_irq(unsigned int irq) +static void combiner_mask_irq(struct irq_data *data) { - u32 mask = 1 << (irq % 32); + u32 mask = 1 << (data->irq % 32); - __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_CLEAR); + __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); } -static void combiner_unmask_irq(unsigned int irq) +static void combiner_unmask_irq(struct irq_data *data) { - u32 mask = 1 << (irq % 32); + u32 mask = 1 << (data->irq % 32); - __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_SET); + __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET); } static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) @@ -57,11 +60,12 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) unsigned long status; /* primary controller ack'ing */ - chip->ack(irq); + chip->irq_ack(&desc->irq_data); spin_lock(&irq_controller_lock); status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); spin_unlock(&irq_controller_lock); + status &= chip_data->irq_mask; if (status == 0) goto out; @@ -76,13 +80,13 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) out: /* primary controller unmasking */ - chip->unmask(irq); + chip->irq_unmask(&desc->irq_data); } static struct irq_chip combiner_chip = { .name = "COMBINER", - .mask = combiner_mask_irq, - .unmask = combiner_unmask_irq, + .irq_mask = combiner_mask_irq, + .irq_unmask = combiner_unmask_irq, }; void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) @@ -104,10 +108,12 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base, combiner_data[combiner_nr].base = base; combiner_data[combiner_nr].irq_offset = irq_start; + combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3); /* Disable all interrupts */ - __raw_writel(0xffffffff, base + COMBINER_ENABLE_CLEAR); + __raw_writel(combiner_data[combiner_nr].irq_mask, + base + COMBINER_ENABLE_CLEAR); /* Setup the Linux IRQ subsystem */ diff --git a/arch/arm/mach-s5pv310/irq-eint.c b/arch/arm/mach-s5pv310/irq-eint.c index 5877503e92c..477bd9e97f0 100644 --- a/arch/arm/mach-s5pv310/irq-eint.c +++ b/arch/arm/mach-s5pv310/irq-eint.c @@ -48,42 +48,43 @@ static unsigned int s5pv310_get_irq_nr(unsigned int number) return ret; } -static inline void s5pv310_irq_eint_mask(unsigned int irq) +static inline void s5pv310_irq_eint_mask(struct irq_data *data) { u32 mask; spin_lock(&eint_lock); - mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); - mask |= eint_irq_to_bit(irq); - __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); + mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); + mask |= eint_irq_to_bit(data->irq); + __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); spin_unlock(&eint_lock); } -static void s5pv310_irq_eint_unmask(unsigned int irq) +static void s5pv310_irq_eint_unmask(struct irq_data *data) { u32 mask; spin_lock(&eint_lock); - mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); - mask &= ~(eint_irq_to_bit(irq)); - __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); + mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); + mask &= ~(eint_irq_to_bit(data->irq)); + __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); spin_unlock(&eint_lock); } -static inline void s5pv310_irq_eint_ack(unsigned int irq) +static inline void s5pv310_irq_eint_ack(struct irq_data *data) { - __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); + __raw_writel(eint_irq_to_bit(data->irq), + S5P_EINT_PEND(EINT_REG_NR(data->irq))); } -static void s5pv310_irq_eint_maskack(unsigned int irq) +static void s5pv310_irq_eint_maskack(struct irq_data *data) { - s5pv310_irq_eint_mask(irq); - s5pv310_irq_eint_ack(irq); + s5pv310_irq_eint_mask(data); + s5pv310_irq_eint_ack(data); } -static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type) +static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type) { - int offs = EINT_OFFSET(irq); + int offs = EINT_OFFSET(data->irq); int shift; u32 ctrl, mask; u32 newvalue = 0; @@ -118,10 +119,10 @@ static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type) mask = 0x7 << shift; spin_lock(&eint_lock); - ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq))); + ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq))); ctrl &= ~mask; ctrl |= newvalue << shift; - __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq))); + __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq))); spin_unlock(&eint_lock); switch (offs) { @@ -146,13 +147,13 @@ static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type) static struct irq_chip s5pv310_irq_eint = { .name = "s5pv310-eint", - .mask = s5pv310_irq_eint_mask, - .unmask = s5pv310_irq_eint_unmask, - .mask_ack = s5pv310_irq_eint_maskack, - .ack = s5pv310_irq_eint_ack, - .set_type = s5pv310_irq_eint_set_type, + .irq_mask = s5pv310_irq_eint_mask, + .irq_unmask = s5pv310_irq_eint_unmask, + .irq_mask_ack = s5pv310_irq_eint_maskack, + .irq_ack = s5pv310_irq_eint_ack, + .irq_set_type = s5pv310_irq_eint_set_type, #ifdef CONFIG_PM - .set_wake = s3c_irqext_wake, + .irq_set_wake = s3c_irqext_wake, #endif }; @@ -192,14 +193,14 @@ static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc) u32 *irq_data = get_irq_data(irq); struct irq_chip *chip = get_irq_chip(irq); - chip->mask(irq); + chip->irq_mask(&desc->irq_data); - if (chip->ack) - chip->ack(irq); + if (chip->irq_ack) + chip->irq_ack(&desc->irq_data); generic_handle_irq(*irq_data); - chip->unmask(irq); + chip->irq_unmask(&desc->irq_data); } int __init s5pv310_init_irq_eint(void) diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c index 2b8d4fc52d7..d9cab02e23c 100644 --- a/arch/arm/mach-s5pv310/mach-smdkc210.c +++ b/arch/arm/mach-s5pv310/mach-smdkc210.c @@ -14,18 +14,21 @@ #include <linux/platform_device.h> #include <linux/smsc911x.h> #include <linux/io.h> +#include <linux/i2c.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <plat/regs-serial.h> +#include <plat/regs-srom.h> #include <plat/s5pv310.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/sdhci.h> +#include <plat/iic.h> +#include <plat/pd.h> #include <mach/map.h> -#include <mach/regs-srom.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -139,13 +142,29 @@ static struct platform_device smdkc210_smsc911x = { }, }; +static struct i2c_board_info i2c_devs1[] __initdata = { + {I2C_BOARD_INFO("wm8994", 0x1a),}, +}; + static struct platform_device *smdkc210_devices[] __initdata = { &s3c_device_hsmmc0, &s3c_device_hsmmc1, &s3c_device_hsmmc2, &s3c_device_hsmmc3, + &s3c_device_i2c1, &s3c_device_rtc, &s3c_device_wdt, + &s5pv310_device_ac97, + &s5pv310_device_i2s0, + &s5pv310_device_pd[PD_MFC], + &s5pv310_device_pd[PD_G3D], + &s5pv310_device_pd[PD_LCD0], + &s5pv310_device_pd[PD_LCD1], + &s5pv310_device_pd[PD_CAM], + &s5pv310_device_pd[PD_TV], + &s5pv310_device_pd[PD_GPS], + &s5pv310_device_sysmmu, + &samsung_asoc_dma, &smdkc210_smsc911x, }; @@ -154,23 +173,22 @@ static void __init smdkc210_smsc911x_init(void) u32 cs1; /* configure nCS1 width to 16 bits */ - cs1 = __raw_readl(S5PV310_SROM_BW) & - ~(S5PV310_SROM_BW__CS_MASK << - S5PV310_SROM_BW__NCS1__SHIFT); - cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) | - (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) | - (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) << - S5PV310_SROM_BW__NCS1__SHIFT; - __raw_writel(cs1, S5PV310_SROM_BW); + cs1 = __raw_readl(S5P_SROM_BW) & + ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT); + cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) | + (1 << S5P_SROM_BW__WAITENABLE__SHIFT) | + (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << + S5P_SROM_BW__NCS1__SHIFT; + __raw_writel(cs1, S5P_SROM_BW); /* set timing for nCS1 suitable for ethernet chip */ - __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) | - (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) | - (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) | - (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) | - (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) | - (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) | - (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1); + __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) | + (0x9 << S5P_SROM_BCX__TACP__SHIFT) | + (0xc << S5P_SROM_BCX__TCAH__SHIFT) | + (0x1 << S5P_SROM_BCX__TCOH__SHIFT) | + (0x6 << S5P_SROM_BCX__TACC__SHIFT) | + (0x1 << S5P_SROM_BCX__TCOS__SHIFT) | + (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); } static void __init smdkc210_map_io(void) @@ -182,6 +200,9 @@ static void __init smdkc210_map_io(void) static void __init smdkc210_machine_init(void) { + s3c_i2c1_set_platdata(NULL); + i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); + smdkc210_smsc911x_init(); s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata); diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c index 35826d66632..b1cddbf3c61 100644 --- a/arch/arm/mach-s5pv310/mach-smdkv310.c +++ b/arch/arm/mach-s5pv310/mach-smdkv310.c @@ -14,18 +14,21 @@ #include <linux/platform_device.h> #include <linux/smsc911x.h> #include <linux/io.h> +#include <linux/i2c.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <plat/regs-serial.h> +#include <plat/regs-srom.h> #include <plat/s5pv310.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/sdhci.h> +#include <plat/iic.h> +#include <plat/pd.h> #include <mach/map.h> -#include <mach/regs-srom.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -139,13 +142,29 @@ static struct platform_device smdkv310_smsc911x = { }, }; +static struct i2c_board_info i2c_devs1[] __initdata = { + {I2C_BOARD_INFO("wm8994", 0x1a),}, +}; + static struct platform_device *smdkv310_devices[] __initdata = { &s3c_device_hsmmc0, &s3c_device_hsmmc1, &s3c_device_hsmmc2, &s3c_device_hsmmc3, + &s3c_device_i2c1, &s3c_device_rtc, &s3c_device_wdt, + &s5pv310_device_ac97, + &s5pv310_device_i2s0, + &s5pv310_device_pd[PD_MFC], + &s5pv310_device_pd[PD_G3D], + &s5pv310_device_pd[PD_LCD0], + &s5pv310_device_pd[PD_LCD1], + &s5pv310_device_pd[PD_CAM], + &s5pv310_device_pd[PD_TV], + &s5pv310_device_pd[PD_GPS], + &s5pv310_device_sysmmu, + &samsung_asoc_dma, &smdkv310_smsc911x, }; @@ -154,23 +173,22 @@ static void __init smdkv310_smsc911x_init(void) u32 cs1; /* configure nCS1 width to 16 bits */ - cs1 = __raw_readl(S5PV310_SROM_BW) & - ~(S5PV310_SROM_BW__CS_MASK << - S5PV310_SROM_BW__NCS1__SHIFT); - cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) | - (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) | - (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) << - S5PV310_SROM_BW__NCS1__SHIFT; - __raw_writel(cs1, S5PV310_SROM_BW); + cs1 = __raw_readl(S5P_SROM_BW) & + ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT); + cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) | + (1 << S5P_SROM_BW__WAITENABLE__SHIFT) | + (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << + S5P_SROM_BW__NCS1__SHIFT; + __raw_writel(cs1, S5P_SROM_BW); /* set timing for nCS1 suitable for ethernet chip */ - __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) | - (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) | - (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) | - (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) | - (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) | - (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) | - (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1); + __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) | + (0x9 << S5P_SROM_BCX__TACP__SHIFT) | + (0xc << S5P_SROM_BCX__TCAH__SHIFT) | + (0x1 << S5P_SROM_BCX__TCOH__SHIFT) | + (0x6 << S5P_SROM_BCX__TACC__SHIFT) | + (0x1 << S5P_SROM_BCX__TCOS__SHIFT) | + (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); } static void __init smdkv310_map_io(void) @@ -182,6 +200,9 @@ static void __init smdkv310_map_io(void) static void __init smdkv310_machine_init(void) { + s3c_i2c1_set_platdata(NULL); + i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); + smdkv310_smsc911x_init(); s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata); diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c index 16d8fc00caf..36bc3cf825e 100644 --- a/arch/arm/mach-s5pv310/mach-universal_c210.c +++ b/arch/arm/mach-s5pv310/mach-universal_c210.c @@ -13,6 +13,9 @@ #include <linux/i2c.h> #include <linux/gpio_keys.h> #include <linux/gpio.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> +#include <linux/mmc/host.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -21,6 +24,7 @@ #include <plat/s5pv310.h> #include <plat/cpu.h> #include <plat/devs.h> +#include <plat/sdhci.h> #include <mach/map.h> @@ -116,6 +120,73 @@ static struct platform_device universal_gpio_keys = { }, }; +/* eMMC */ +static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = { + .max_width = 8, + .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | + MMC_CAP_DISABLE), + .cd_type = S3C_SDHCI_CD_PERMANENT, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, +}; + +static struct regulator_consumer_supply mmc0_supplies[] = { + REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"), +}; + +static struct regulator_init_data mmc0_fixed_voltage_init_data = { + .constraints = { + .name = "VMEM_VDD_2.8V", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies), + .consumer_supplies = mmc0_supplies, +}; + +static struct fixed_voltage_config mmc0_fixed_voltage_config = { + .supply_name = "MASSMEMORY_EN", + .microvolts = 2800000, + .gpio = S5PV310_GPE1(3), + .enable_high = true, + .init_data = &mmc0_fixed_voltage_init_data, +}; + +static struct platform_device mmc0_fixed_voltage = { + .name = "reg-fixed-voltage", + .id = 0, + .dev = { + .platform_data = &mmc0_fixed_voltage_config, + }, +}; + +/* SD */ +static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = { + .max_width = 4, + .host_caps = MMC_CAP_4_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | + MMC_CAP_DISABLE, + .ext_cd_gpio = S5PV310_GPX3(4), /* XEINT_28 */ + .ext_cd_gpio_invert = 1, + .cd_type = S3C_SDHCI_CD_GPIO, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, +}; + +/* WiFi */ +static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = { + .max_width = 4, + .host_caps = MMC_CAP_4_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | + MMC_CAP_DISABLE, + .cd_type = S3C_SDHCI_CD_EXTERNAL, +}; + +static void __init universal_sdhci_init(void) +{ + s3c_sdhci0_set_platdata(&universal_hsmmc0_data); + s3c_sdhci2_set_platdata(&universal_hsmmc2_data); + s3c_sdhci3_set_platdata(&universal_hsmmc3_data); +} + /* I2C0 */ static struct i2c_board_info i2c0_devs[] __initdata = { /* Camera, To be updated */ @@ -127,6 +198,13 @@ static struct i2c_board_info i2c1_devs[] __initdata = { }; static struct platform_device *universal_devices[] __initdata = { + /* Samsung Platform Devices */ + &mmc0_fixed_voltage, + &s3c_device_hsmmc0, + &s3c_device_hsmmc2, + &s3c_device_hsmmc3, + + /* Universal Devices */ &universal_gpio_keys, &s5p_device_onenand, }; @@ -140,6 +218,8 @@ static void __init universal_map_io(void) static void __init universal_machine_init(void) { + universal_sdhci_init(); + i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 59d14f0fdcf..e21f3470eec 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c @@ -21,7 +21,6 @@ #include <asm/div64.h> #include <mach/hardware.h> #include <asm/system.h> -#include <asm/pgtable.h> #include <asm/mach/map.h> #include <asm/mach/flash.h> #include <asm/irq.h> diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 3093d46a9c6..3d85dfad9c1 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c @@ -37,14 +37,14 @@ static int GPIO_IRQ_mask = (1 << 11) - 1; #define GPIO_11_27_IRQ(i) ((i) - 21) #define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq)) -static int sa1100_gpio_type(unsigned int irq, unsigned int type) +static int sa1100_gpio_type(struct irq_data *d, unsigned int type) { unsigned int mask; - if (irq <= 10) - mask = 1 << irq; + if (d->irq <= 10) + mask = 1 << d->irq; else - mask = GPIO11_27_MASK(irq); + mask = GPIO11_27_MASK(d->irq); if (type == IRQ_TYPE_PROBE) { if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) @@ -70,37 +70,37 @@ static int sa1100_gpio_type(unsigned int irq, unsigned int type) /* * GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10. */ -static void sa1100_low_gpio_ack(unsigned int irq) +static void sa1100_low_gpio_ack(struct irq_data *d) { - GEDR = (1 << irq); + GEDR = (1 << d->irq); } -static void sa1100_low_gpio_mask(unsigned int irq) +static void sa1100_low_gpio_mask(struct irq_data *d) { - ICMR &= ~(1 << irq); + ICMR &= ~(1 << d->irq); } -static void sa1100_low_gpio_unmask(unsigned int irq) +static void sa1100_low_gpio_unmask(struct irq_data *d) { - ICMR |= 1 << irq; + ICMR |= 1 << d->irq; } -static int sa1100_low_gpio_wake(unsigned int irq, unsigned int on) +static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on) { if (on) - PWER |= 1 << irq; + PWER |= 1 << d->irq; else - PWER &= ~(1 << irq); + PWER &= ~(1 << d->irq); return 0; } static struct irq_chip sa1100_low_gpio_chip = { .name = "GPIO-l", - .ack = sa1100_low_gpio_ack, - .mask = sa1100_low_gpio_mask, - .unmask = sa1100_low_gpio_unmask, - .set_type = sa1100_gpio_type, - .set_wake = sa1100_low_gpio_wake, + .irq_ack = sa1100_low_gpio_ack, + .irq_mask = sa1100_low_gpio_mask, + .irq_unmask = sa1100_low_gpio_unmask, + .irq_set_type = sa1100_gpio_type, + .irq_set_wake = sa1100_low_gpio_wake, }; /* @@ -139,16 +139,16 @@ sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc) * In addition, the IRQs are all collected up into one bit in the * interrupt controller registers. */ -static void sa1100_high_gpio_ack(unsigned int irq) +static void sa1100_high_gpio_ack(struct irq_data *d) { - unsigned int mask = GPIO11_27_MASK(irq); + unsigned int mask = GPIO11_27_MASK(d->irq); GEDR = mask; } -static void sa1100_high_gpio_mask(unsigned int irq) +static void sa1100_high_gpio_mask(struct irq_data *d) { - unsigned int mask = GPIO11_27_MASK(irq); + unsigned int mask = GPIO11_27_MASK(d->irq); GPIO_IRQ_mask &= ~mask; @@ -156,9 +156,9 @@ static void sa1100_high_gpio_mask(unsigned int irq) GFER &= ~mask; } -static void sa1100_high_gpio_unmask(unsigned int irq) +static void sa1100_high_gpio_unmask(struct irq_data *d) { - unsigned int mask = GPIO11_27_MASK(irq); + unsigned int mask = GPIO11_27_MASK(d->irq); GPIO_IRQ_mask |= mask; @@ -166,44 +166,44 @@ static void sa1100_high_gpio_unmask(unsigned int irq) GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; } -static int sa1100_high_gpio_wake(unsigned int irq, unsigned int on) +static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on) { if (on) - PWER |= GPIO11_27_MASK(irq); + PWER |= GPIO11_27_MASK(d->irq); else - PWER &= ~GPIO11_27_MASK(irq); + PWER &= ~GPIO11_27_MASK(d->irq); return 0; } static struct irq_chip sa1100_high_gpio_chip = { .name = "GPIO-h", - .ack = sa1100_high_gpio_ack, - .mask = sa1100_high_gpio_mask, - .unmask = sa1100_high_gpio_unmask, - .set_type = sa1100_gpio_type, - .set_wake = sa1100_high_gpio_wake, + .irq_ack = sa1100_high_gpio_ack, + .irq_mask = sa1100_high_gpio_mask, + .irq_unmask = sa1100_high_gpio_unmask, + .irq_set_type = sa1100_gpio_type, + .irq_set_wake = sa1100_high_gpio_wake, }; /* * We don't need to ACK IRQs on the SA1100 unless they're GPIOs * this is for internal IRQs i.e. from 11 to 31. */ -static void sa1100_mask_irq(unsigned int irq) +static void sa1100_mask_irq(struct irq_data *d) { - ICMR &= ~(1 << irq); + ICMR &= ~(1 << d->irq); } -static void sa1100_unmask_irq(unsigned int irq) +static void sa1100_unmask_irq(struct irq_data *d) { - ICMR |= (1 << irq); + ICMR |= (1 << d->irq); } /* * Apart form GPIOs, only the RTC alarm can be a wakeup event. */ -static int sa1100_set_wake(unsigned int irq, unsigned int on) +static int sa1100_set_wake(struct irq_data *d, unsigned int on) { - if (irq == IRQ_RTCAlrm) { + if (d->irq == IRQ_RTCAlrm) { if (on) PWER |= PWER_RTC; else @@ -215,10 +215,10 @@ static int sa1100_set_wake(unsigned int irq, unsigned int on) static struct irq_chip sa1100_normal_chip = { .name = "SC", - .ack = sa1100_mask_irq, - .mask = sa1100_mask_irq, - .unmask = sa1100_unmask_irq, - .set_wake = sa1100_set_wake, + .irq_ack = sa1100_mask_irq, + .irq_mask = sa1100_mask_irq, + .irq_unmask = sa1100_unmask_irq, + .irq_set_wake = sa1100_set_wake, }; static struct resource irq_resource = { diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index c601a75a333..4aad01f7366 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -35,7 +35,7 @@ neponset_irq_handler(unsigned int irq, struct irq_desc *desc) /* * Acknowledge the parent IRQ. */ - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); /* * Read the interrupt reason register. Let's have all @@ -53,7 +53,7 @@ neponset_irq_handler(unsigned int irq, struct irq_desc *desc) * recheck the register for any pending IRQs. */ if (irr & (IRR_ETHERNET | IRR_USAR)) { - desc->chip->mask(irq); + desc->irq_data.chip->irq_mask(&desc->irq_data); /* * Ack the interrupt now to prevent re-entering @@ -61,7 +61,7 @@ neponset_irq_handler(unsigned int irq, struct irq_desc *desc) * since we'll check the IRR register prior to * leaving. */ - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); if (irr & IRR_ETHERNET) { generic_handle_irq(IRQ_NEPONSET_SMC9196); @@ -71,7 +71,7 @@ neponset_irq_handler(unsigned int irq, struct irq_desc *desc) generic_handle_irq(IRQ_NEPONSET_USAR); } - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); } if (irr & IRR_SA1111) { diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c index c04eb6a1e2b..831fc66dfa4 100644 --- a/arch/arm/mach-shark/irq.c +++ b/arch/arm/mach-shark/irq.c @@ -30,35 +30,35 @@ static unsigned char cached_irq_mask[2] = { 0xfb, 0xff }; * These have to be protected by the irq controller spinlock * before being called. */ -static void shark_disable_8259A_irq(unsigned int irq) +static void shark_disable_8259A_irq(struct irq_data *d) { unsigned int mask; - if (irq<8) { - mask = 1 << irq; + if (d->irq<8) { + mask = 1 << d->irq; cached_irq_mask[0] |= mask; outb(cached_irq_mask[1],0xA1); } else { - mask = 1 << (irq-8); + mask = 1 << (d->irq-8); cached_irq_mask[1] |= mask; outb(cached_irq_mask[0],0x21); } } -static void shark_enable_8259A_irq(unsigned int irq) +static void shark_enable_8259A_irq(struct irq_data *d) { unsigned int mask; - if (irq<8) { - mask = ~(1 << irq); + if (d->irq<8) { + mask = ~(1 << d->irq); cached_irq_mask[0] &= mask; outb(cached_irq_mask[0],0x21); } else { - mask = ~(1 << (irq-8)); + mask = ~(1 << (d->irq-8)); cached_irq_mask[1] &= mask; outb(cached_irq_mask[1],0xA1); } } -static void shark_ack_8259A_irq(unsigned int irq){} +static void shark_ack_8259A_irq(struct irq_data *d){} static irqreturn_t bogus_int(int irq, void *dev_id) { @@ -69,10 +69,10 @@ static irqreturn_t bogus_int(int irq, void *dev_id) static struct irqaction cascade; static struct irq_chip fb_chip = { - .name = "XT-PIC", - .ack = shark_ack_8259A_irq, - .mask = shark_disable_8259A_irq, - .unmask = shark_enable_8259A_irq, + .name = "XT-PIC", + .irq_ack = shark_ack_8259A_irq, + .irq_mask = shark_disable_8259A_irq, + .irq_unmask = shark_enable_8259A_irq, }; void __init shark_init_irq(void) diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c index ddd49a760fd..c2f9fe04c11 100644 --- a/arch/arm/mach-stmp378x/stmp378x.c +++ b/arch/arm/mach-stmp378x/stmp378x.c @@ -47,7 +47,7 @@ /* * IRQ handling */ -static void stmp378x_ack_irq(unsigned int irq) +static void stmp378x_ack_irq(struct irq_data *d) { /* Tell ICOLL to release IRQ line */ __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR); @@ -60,24 +60,24 @@ static void stmp378x_ack_irq(unsigned int irq) (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT); } -static void stmp378x_mask_irq(unsigned int irq) +static void stmp378x_mask_irq(struct irq_data *d) { /* IRQ disable */ stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE, - REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10); + REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10); } -static void stmp378x_unmask_irq(unsigned int irq) +static void stmp378x_unmask_irq(struct irq_data *d) { /* IRQ enable */ stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE, - REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10); + REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10); } static struct irq_chip stmp378x_chip = { - .ack = stmp378x_ack_irq, - .mask = stmp378x_mask_irq, - .unmask = stmp378x_unmask_irq, + .irq_ack = stmp378x_ack_irq, + .irq_mask = stmp378x_mask_irq, + .irq_unmask = stmp378x_unmask_irq, }; void __init stmp378x_init_irq(void) diff --git a/arch/arm/mach-stmp37xx/stmp37xx.c b/arch/arm/mach-stmp37xx/stmp37xx.c index 8c7d6fb191a..a9aed06ff37 100644 --- a/arch/arm/mach-stmp37xx/stmp37xx.c +++ b/arch/arm/mach-stmp37xx/stmp37xx.c @@ -43,11 +43,11 @@ /* * IRQ handling */ -static void stmp37xx_ack_irq(unsigned int irq) +static void stmp37xx_ack_irq(struct irq_data *d) { /* Disable IRQ */ - stmp3xxx_clearl(0x04 << ((irq % 4) * 8), - REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10); + stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8), + REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10); /* ACK current interrupt */ __raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK); @@ -56,24 +56,24 @@ static void stmp37xx_ack_irq(unsigned int irq) (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT); } -static void stmp37xx_mask_irq(unsigned int irq) +static void stmp37xx_mask_irq(struct irq_data *d) { /* IRQ disable */ - stmp3xxx_clearl(0x04 << ((irq % 4) * 8), - REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10); + stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8), + REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10); } -static void stmp37xx_unmask_irq(unsigned int irq) +static void stmp37xx_unmask_irq(struct irq_data *d) { /* IRQ enable */ - stmp3xxx_setl(0x04 << ((irq % 4) * 8), - REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10); + stmp3xxx_setl(0x04 << ((d->irq % 4) * 8), + REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10); } static struct irq_chip stmp37xx_chip = { - .ack = stmp37xx_ack_irq, - .mask = stmp37xx_mask_irq, - .unmask = stmp37xx_unmask_irq, + .irq_ack = stmp37xx_ack_irq, + .irq_mask = stmp37xx_mask_irq, + .irq_unmask = stmp37xx_unmask_irq, }; void __init stmp37xx_init_irq(void) diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c index 34575c4963f..aa9231f4fc6 100644 --- a/arch/arm/mach-tcc8k/irq.c +++ b/arch/arm/mach-tcc8k/irq.c @@ -18,65 +18,65 @@ #include "common.h" /* Disable IRQ */ -static void tcc8000_mask_ack_irq0(unsigned int irq) +static void tcc8000_mask_ack_irq0(struct irq_data *d) { - PIC0_IEN &= ~(1 << irq); - PIC0_CREQ |= (1 << irq); + PIC0_IEN &= ~(1 << d->irq); + PIC0_CREQ |= (1 << d->irq); } -static void tcc8000_mask_ack_irq1(unsigned int irq) +static void tcc8000_mask_ack_irq1(struct irq_data *d) { - PIC1_IEN &= ~(1 << (irq - 32)); - PIC1_CREQ |= (1 << (irq - 32)); + PIC1_IEN &= ~(1 << (d->irq - 32)); + PIC1_CREQ |= (1 << (d->irq - 32)); } -static void tcc8000_mask_irq0(unsigned int irq) +static void tcc8000_mask_irq0(struct irq_data *d) { - PIC0_IEN &= ~(1 << irq); + PIC0_IEN &= ~(1 << d->irq); } -static void tcc8000_mask_irq1(unsigned int irq) +static void tcc8000_mask_irq1(struct irq_data *d) { - PIC1_IEN &= ~(1 << (irq - 32)); + PIC1_IEN &= ~(1 << (d->irq - 32)); } -static void tcc8000_ack_irq0(unsigned int irq) +static void tcc8000_ack_irq0(struct irq_data *d) { - PIC0_CREQ |= (1 << irq); + PIC0_CREQ |= (1 << d->irq); } -static void tcc8000_ack_irq1(unsigned int irq) +static void tcc8000_ack_irq1(struct irq_data *d) { - PIC1_CREQ |= (1 << (irq - 32)); + PIC1_CREQ |= (1 << (d->irq - 32)); } /* Enable IRQ */ -static void tcc8000_unmask_irq0(unsigned int irq) +static void tcc8000_unmask_irq0(struct irq_data *d) { - PIC0_IEN |= (1 << irq); - PIC0_INTOEN |= (1 << irq); + PIC0_IEN |= (1 << d->irq); + PIC0_INTOEN |= (1 << d->irq); } -static void tcc8000_unmask_irq1(unsigned int irq) +static void tcc8000_unmask_irq1(struct irq_data *d) { - PIC1_IEN |= (1 << (irq - 32)); - PIC1_INTOEN |= (1 << (irq - 32)); + PIC1_IEN |= (1 << (d->irq - 32)); + PIC1_INTOEN |= (1 << (d->irq - 32)); } static struct irq_chip tcc8000_irq_chip0 = { .name = "tcc_irq0", - .mask = tcc8000_mask_irq0, - .ack = tcc8000_ack_irq0, - .mask_ack = tcc8000_mask_ack_irq0, - .unmask = tcc8000_unmask_irq0, + .irq_mask = tcc8000_mask_irq0, + .irq_ack = tcc8000_ack_irq0, + .irq_mask_ack = tcc8000_mask_ack_irq0, + .irq_unmask = tcc8000_unmask_irq0, }; static struct irq_chip tcc8000_irq_chip1 = { .name = "tcc_irq1", - .mask = tcc8000_mask_irq1, - .ack = tcc8000_ack_irq1, - .mask_ack = tcc8000_mask_ack_irq1, - .unmask = tcc8000_unmask_irq1, + .irq_mask = tcc8000_mask_irq1, + .irq_ack = tcc8000_ack_irq1, + .irq_mask_ack = tcc8000_mask_ack_irq1, + .irq_unmask = tcc8000_unmask_irq1, }; void __init tcc8k_init_irq(void) diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c index 0775265e69f..bd066206e11 100644 --- a/arch/arm/mach-tegra/gpio.c +++ b/arch/arm/mach-tegra/gpio.c @@ -142,31 +142,31 @@ static struct gpio_chip tegra_gpio_chip = { .ngpio = TEGRA_NR_GPIOS, }; -static void tegra_gpio_irq_ack(unsigned int irq) +static void tegra_gpio_irq_ack(struct irq_data *d) { - int gpio = irq - INT_GPIO_BASE; + int gpio = d->irq - INT_GPIO_BASE; __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio)); } -static void tegra_gpio_irq_mask(unsigned int irq) +static void tegra_gpio_irq_mask(struct irq_data *d) { - int gpio = irq - INT_GPIO_BASE; + int gpio = d->irq - INT_GPIO_BASE; tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0); } -static void tegra_gpio_irq_unmask(unsigned int irq) +static void tegra_gpio_irq_unmask(struct irq_data *d) { - int gpio = irq - INT_GPIO_BASE; + int gpio = d->irq - INT_GPIO_BASE; tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1); } -static int tegra_gpio_irq_set_type(unsigned int irq, unsigned int type) +static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) { - int gpio = irq - INT_GPIO_BASE; - struct tegra_gpio_bank *bank = get_irq_chip_data(irq); + int gpio = d->irq - INT_GPIO_BASE; + struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); int port = GPIO_PORT(gpio); int lvl_type; int val; @@ -221,7 +221,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) int pin; int unmasked = 0; - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); bank = get_irq_data(irq); @@ -240,7 +240,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) */ if (lvl & (0x100 << pin)) { unmasked = 1; - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); } generic_handle_irq(gpio_to_irq(gpio + pin)); @@ -248,7 +248,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) } if (!unmasked) - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); } @@ -316,21 +316,21 @@ void tegra_gpio_suspend(void) local_irq_restore(flags); } -static int tegra_gpio_wake_enable(unsigned int irq, unsigned int enable) +static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) { - struct tegra_gpio_bank *bank = get_irq_chip_data(irq); + struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); return set_irq_wake(bank->irq, enable); } #endif static struct irq_chip tegra_gpio_irq_chip = { .name = "GPIO", - .ack = tegra_gpio_irq_ack, - .mask = tegra_gpio_irq_mask, - .unmask = tegra_gpio_irq_unmask, - .set_type = tegra_gpio_irq_set_type, + .irq_ack = tegra_gpio_irq_ack, + .irq_mask = tegra_gpio_irq_mask, + .irq_unmask = tegra_gpio_irq_unmask, + .irq_set_type = tegra_gpio_irq_set_type, #ifdef CONFIG_PM - .set_wake = tegra_gpio_wake_enable, + .irq_set_wake = tegra_gpio_wake_enable, #endif }; diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index a5cb1ce76ff..f3294040d35 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c @@ -26,10 +26,10 @@ static inline void cpu_enter_lowpower(void) * Turn off coherency */ " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, %2\n" + " bic %0, %0, #0x20\n" " mcr p15, 0, %0, c1, c0, 1\n" " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, #0x04\n" + " bic %0, %0, %2\n" " mcr p15, 0, %0, c1, c0, 0\n" : "=&r" (v) : "r" (0), "Ir" (CR_C) diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 5407de01abf..de7dfad6f76 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -46,30 +46,30 @@ #define ICTLR_COP_IER_CLR 0x38 #define ICTLR_COP_IEP_CLASS 0x3c -static void (*gic_mask_irq)(unsigned int irq); -static void (*gic_unmask_irq)(unsigned int irq); +static void (*gic_mask_irq)(struct irq_data *d); +static void (*gic_unmask_irq)(struct irq_data *d); #define irq_to_ictlr(irq) (((irq)-32) >> 5) static void __iomem *tegra_ictlr_base = IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE); #define ictlr_to_virt(ictlr) (tegra_ictlr_base + (ictlr)*0x100) -static void tegra_mask(unsigned int irq) +static void tegra_mask(struct irq_data *d) { - void __iomem *addr = ictlr_to_virt(irq_to_ictlr(irq)); - gic_mask_irq(irq); - writel(1<<(irq&31), addr+ICTLR_CPU_IER_CLR); + void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq)); + gic_mask_irq(d); + writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_CLR); } -static void tegra_unmask(unsigned int irq) +static void tegra_unmask(struct irq_data *d) { - void __iomem *addr = ictlr_to_virt(irq_to_ictlr(irq)); - gic_unmask_irq(irq); - writel(1<<(irq&31), addr+ICTLR_CPU_IER_SET); + void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq)); + gic_unmask_irq(d); + writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_SET); } #ifdef CONFIG_PM -static int tegra_set_wake(unsigned int irq, unsigned int on) +static int tegra_set_wake(struct irq_data *d, unsigned int on) { return 0; } @@ -77,10 +77,10 @@ static int tegra_set_wake(unsigned int irq, unsigned int on) static struct irq_chip tegra_irq = { .name = "PPI", - .mask = tegra_mask, - .unmask = tegra_unmask, + .irq_mask = tegra_mask, + .irq_unmask = tegra_unmask, #ifdef CONFIG_PM - .set_wake = tegra_set_wake, + .irq_set_wake = tegra_set_wake, #endif }; @@ -98,11 +98,11 @@ void __init tegra_init_irq(void) IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); gic = get_irq_chip(29); - gic_unmask_irq = gic->unmask; - gic_mask_irq = gic->mask; - tegra_irq.ack = gic->ack; + gic_unmask_irq = gic->irq_unmask; + gic_mask_irq = gic->irq_mask; + tegra_irq.irq_ack = gic->irq_ack; #ifdef CONFIG_SMP - tegra_irq.set_affinity = gic->set_affinity; + tegra_irq.irq_set_affinity = gic->irq_set_affinity; #endif for (i = INT_PRI_BASE; i < INT_GPIO_BASE; i++) { diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 13a83e45a33..136c32e7ed8 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -63,23 +63,25 @@ #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) -static void sic_mask_irq(unsigned int irq) +static void sic_mask_irq(struct irq_data *d) { - irq -= IRQ_SIC_START; + unsigned int irq = d->irq - IRQ_SIC_START; + writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); } -static void sic_unmask_irq(unsigned int irq) +static void sic_unmask_irq(struct irq_data *d) { - irq -= IRQ_SIC_START; + unsigned int irq = d->irq - IRQ_SIC_START; + writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET); } static struct irq_chip sic_chip = { - .name = "SIC", - .ack = sic_mask_irq, - .mask = sic_mask_irq, - .unmask = sic_unmask_irq, + .name = "SIC", + .irq_ack = sic_mask_irq, + .irq_mask = sic_mask_irq, + .irq_unmask = sic_unmask_irq, }; static void diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c index 0ce9d8e867e..9c350103dcd 100644 --- a/arch/arm/mach-w90x900/irq.c +++ b/arch/arm/mach-w90x900/irq.c @@ -92,15 +92,15 @@ static void nuc900_group_enable(struct group_irq *gpirq, int enable) __raw_writel(regval, REG_AIC_GEN); } -static void nuc900_irq_mask(unsigned int irq) +static void nuc900_irq_mask(struct irq_data *d) { struct group_irq *group_irq; group_irq = NULL; - __raw_writel(1 << irq, REG_AIC_MDCR); + __raw_writel(1 << d->irq, REG_AIC_MDCR); - switch (irq) { + switch (d->irq) { case IRQ_GROUP0: group_irq = &group_nirq0; break; @@ -143,20 +143,20 @@ static void nuc900_irq_mask(unsigned int irq) * to REG_AIC_EOSCR for ACK */ -static void nuc900_irq_ack(unsigned int irq) +static void nuc900_irq_ack(struct irq_data *d) { __raw_writel(0x01, REG_AIC_EOSCR); } -static void nuc900_irq_unmask(unsigned int irq) +static void nuc900_irq_unmask(struct irq_data *d) { struct group_irq *group_irq; group_irq = NULL; - __raw_writel(1 << irq, REG_AIC_MECR); + __raw_writel(1 << d->irq, REG_AIC_MECR); - switch (irq) { + switch (d->irq) { case IRQ_GROUP0: group_irq = &group_nirq0; break; @@ -195,9 +195,9 @@ static void nuc900_irq_unmask(unsigned int irq) } static struct irq_chip nuc900_irq_chip = { - .ack = nuc900_irq_ack, - .mask = nuc900_irq_mask, - .unmask = nuc900_irq_unmask, + .irq_ack = nuc900_irq_ack, + .irq_mask = nuc900_irq_mask, + .irq_unmask = nuc900_irq_unmask, }; void __init nuc900_init_irq(void) diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index fcc1e628e05..9d30c6f804b 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -644,7 +644,7 @@ config ARM_THUMBEE config SWP_EMULATE bool "Emulate SWP/SWPB instructions" - depends on CPU_V7 + depends on CPU_V7 && !CPU_V6 select HAVE_PROC_CPU if PROC_FS default y if SMP help diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 6b48e0a3d7a..4771dba6144 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -577,7 +577,7 @@ EXPORT_SYMBOL(dma_map_sg); * dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices * @sg: list of buffers - * @nents: number of buffers to unmap (returned from dma_map_sg) + * @nents: number of buffers to unmap (same as was passed to dma_map_sg) * @dir: DMA transfer direction (same as was passed to dma_map_sg) * * Unmap a set of streaming mode DMA translations. Again, CPU access diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index b49fab21517..0c1172b56b4 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -159,7 +159,9 @@ ENTRY(cpu_v7_set_pte_ext) tstne r1, #L_PTE_PRESENT moveq r3, #0 - str r3, [r0, #2048]! + ARM( str r3, [r0, #2048]! ) + THUMB( add r0, r0, #2048 ) + THUMB( str r3, [r0] ) mcr p15, 0, r0, c7, c10, 1 @ flush_pte #endif mov pc, lr diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c index 639c54a0799..c856fa39760 100644 --- a/arch/arm/plat-mxc/3ds_debugboard.c +++ b/arch/arm/plat-mxc/3ds_debugboard.c @@ -60,7 +60,6 @@ #define EXPIO_INT_BUTTON_B (MXC_BOARD_IRQ_START + 4) static void __iomem *brd_io; -static void expio_ack_irq(u32 irq); static struct resource smsc911x_resources[] = { { @@ -93,7 +92,8 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) u32 int_valid; u32 expio_irq; - desc->chip->mask(irq); /* irq = gpio irq number */ + /* irq = gpio irq number */ + desc->irq_data.chip->irq_mask(&desc->irq_data); imr_val = __raw_readw(brd_io + INTR_MASK_REG); int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val; @@ -110,37 +110,37 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) d->handle_irq(expio_irq, d); } - desc->chip->ack(irq); - desc->chip->unmask(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); + desc->irq_data.chip->irq_unmask(&desc->irq_data); } /* * Disable an expio pin's interrupt by setting the bit in the imr. * Irq is an expio virtual irq number */ -static void expio_mask_irq(u32 irq) +static void expio_mask_irq(struct irq_data *d) { u16 reg; - u32 expio = MXC_IRQ_TO_EXPIO(irq); + u32 expio = MXC_IRQ_TO_EXPIO(d->irq); reg = __raw_readw(brd_io + INTR_MASK_REG); reg |= (1 << expio); __raw_writew(reg, brd_io + INTR_MASK_REG); } -static void expio_ack_irq(u32 irq) +static void expio_ack_irq(struct irq_data *d) { - u32 expio = MXC_IRQ_TO_EXPIO(irq); + u32 expio = MXC_IRQ_TO_EXPIO(d->irq); __raw_writew(1 << expio, brd_io + INTR_RESET_REG); __raw_writew(0, brd_io + INTR_RESET_REG); - expio_mask_irq(irq); + expio_mask_irq(d); } -static void expio_unmask_irq(u32 irq) +static void expio_unmask_irq(struct irq_data *d) { u16 reg; - u32 expio = MXC_IRQ_TO_EXPIO(irq); + u32 expio = MXC_IRQ_TO_EXPIO(d->irq); reg = __raw_readw(brd_io + INTR_MASK_REG); reg &= ~(1 << expio); @@ -148,9 +148,9 @@ static void expio_unmask_irq(u32 irq) } static struct irq_chip expio_irq_chip = { - .ack = expio_ack_irq, - .mask = expio_mask_irq, - .unmask = expio_unmask_irq, + .irq_ack = expio_ack_irq, + .irq_mask = expio_mask_irq, + .irq_unmask = expio_unmask_irq, }; int __init mxc_expio_init(u32 base, u32 p_irq) diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c index 9a4e8a22dd0..deb284bc7c4 100644 --- a/arch/arm/plat-mxc/avic.c +++ b/arch/arm/plat-mxc/avic.c @@ -89,22 +89,22 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type) #endif /* CONFIG_FIQ */ /* Disable interrupt number "irq" in the AVIC */ -static void mxc_mask_irq(unsigned int irq) +static void mxc_mask_irq(struct irq_data *d) { - __raw_writel(irq, avic_base + AVIC_INTDISNUM); + __raw_writel(d->irq, avic_base + AVIC_INTDISNUM); } /* Enable interrupt number "irq" in the AVIC */ -static void mxc_unmask_irq(unsigned int irq) +static void mxc_unmask_irq(struct irq_data *d) { - __raw_writel(irq, avic_base + AVIC_INTENNUM); + __raw_writel(d->irq, avic_base + AVIC_INTENNUM); } static struct mxc_irq_chip mxc_avic_chip = { .base = { - .ack = mxc_mask_irq, - .mask = mxc_mask_irq, - .unmask = mxc_unmask_irq, + .irq_ack = mxc_mask_irq, + .irq_mask = mxc_mask_irq, + .irq_unmask = mxc_unmask_irq, }, #ifdef CONFIG_MXC_IRQ_PRIOR .set_priority = avic_irq_set_priority, diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 2537166468a..b9ab1d58b5e 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -1,6 +1,6 @@ config IMX_HAVE_PLATFORM_FEC bool - default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 + default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53 config IMX_HAVE_PLATFORM_FLEXCAN select HAVE_CAN_FLEXCAN if CAN diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index 269ec78aba7..b50c3517d08 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c @@ -36,6 +36,11 @@ const struct imx_fec_data imx51_fec_data __initconst = imx_fec_data_entry_single(MX51); #endif +#ifdef CONFIG_SOC_IMX53 +const struct imx_fec_data imx53_fec_data __initconst = + imx_fec_data_entry_single(MX53); +#endif + struct platform_device *__init imx_add_fec( const struct imx_fec_data *data, const struct fec_platform_data *pdata) diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index 72ba880c75a..7ba94e1bbda 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -78,6 +78,15 @@ const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX51 */ +#ifdef CONFIG_SOC_IMX53 +const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst = { +#define imx53_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX53, _id, _hwid, SZ_4K) + imx53_imx_i2c_data_entry(0, 1), + imx53_imx_i2c_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + struct platform_device *__init imx_add_imx_i2c( const struct imx_imx_i2c_data *data, const struct imxi2c_platform_data *pdata) diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c index 40238f0b864..26366114b02 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-keypad.c +++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c @@ -41,6 +41,11 @@ const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst = imx_imx_keypad_data_entry_single(MX35, SZ_16); #endif /* ifdef CONFIG_SOC_IMX35 */ +#ifdef CONFIG_SOC_IMX51 +const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX51, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX51 */ + struct platform_device *__init imx_add_imx_keypad( const struct imx_imx_keypad_data *data, const struct matrix_keymap_data *pdata) diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c index 3d8ebdba38e..b0c4ae29811 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c @@ -40,6 +40,15 @@ const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst = imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K); #endif /* ifdef CONFIG_SOC_IMX27 */ +#ifdef CONFIG_SOC_IMX51 +const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = { +#define imx51_mxc_pwm_data_entry(_id, _hwid) \ + imx_mxc_pwm_data_entry(MX51, _id, _hwid, SZ_16K) + imx51_mxc_pwm_data_entry(0, 1), + imx51_mxc_pwm_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + struct platform_device *__init imx_add_mxc_pwm( const struct imx_mxc_pwm_data *data) { diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c index b3525648a01..6b2940b93d9 100644 --- a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c +++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c @@ -53,6 +53,18 @@ imx51_sdhci_esdhc_imx_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX51 */ +#ifdef CONFIG_SOC_IMX53 +const struct imx_sdhci_esdhc_imx_data +imx53_sdhci_esdhc_imx_data[] __initconst = { +#define imx53_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX53, _id, _hwid) + imx53_sdhci_esdhc_imx_data_entry(0, 1), + imx53_sdhci_esdhc_imx_data_entry(1, 2), + imx53_sdhci_esdhc_imx_data_entry(2, 3), + imx53_sdhci_esdhc_imx_data_entry(3, 4), +}; +#endif /* ifdef CONFIG_SOC_IMX53 */ + struct platform_device *__init imx_add_sdhci_esdhc_imx( const struct imx_sdhci_esdhc_imx_data *data, const struct esdhc_platform_data *pdata) diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index 8ea49adcdfc..013c85f20b5 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -81,6 +81,18 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX51 */ +#ifdef CONFIG_SOC_IMX53 +const struct imx_spi_imx_data imx53_cspi_data __initconst = + imx_spi_imx_data_entry_single(MX53, CSPI, "imx53-cspi", 0, , SZ_4K); + +const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = { +#define imx53_ecspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX53, ECSPI, "imx53-ecspi", _id, _hwid, SZ_4K) + imx53_ecspi_data_entry(0, 1), + imx53_ecspi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX53 */ + struct platform_device *__init imx_add_spi_imx( const struct imx_spi_imx_data *data, const struct spi_imx_master *pdata) diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index bc2c7bc6f10..d17b3c996b8 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -63,29 +63,29 @@ static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index, __raw_writel(l, port->base + GPIO_IMR); } -static void gpio_ack_irq(u32 irq) +static void gpio_ack_irq(struct irq_data *d) { - u32 gpio = irq_to_gpio(irq); + u32 gpio = irq_to_gpio(d->irq); _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f); } -static void gpio_mask_irq(u32 irq) +static void gpio_mask_irq(struct irq_data *d) { - u32 gpio = irq_to_gpio(irq); + u32 gpio = irq_to_gpio(d->irq); _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0); } -static void gpio_unmask_irq(u32 irq) +static void gpio_unmask_irq(struct irq_data *d) { - u32 gpio = irq_to_gpio(irq); + u32 gpio = irq_to_gpio(d->irq); _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1); } static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset); -static int gpio_set_irq_type(u32 irq, u32 type) +static int gpio_set_irq_type(struct irq_data *d, u32 type) { - u32 gpio = irq_to_gpio(irq); + u32 gpio = irq_to_gpio(d->irq); struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32]; u32 bit, val; int edge; @@ -211,9 +211,9 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) * @param enable enable as wake-up if equal to non-zero * @return This function returns 0 on success. */ -static int gpio_set_wake_irq(u32 irq, u32 enable) +static int gpio_set_wake_irq(struct irq_data *d, u32 enable) { - u32 gpio = irq_to_gpio(irq); + u32 gpio = irq_to_gpio(d->irq); u32 gpio_idx = gpio & 0x1F; struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32]; @@ -233,11 +233,11 @@ static int gpio_set_wake_irq(u32 irq, u32 enable) } static struct irq_chip gpio_irq_chip = { - .ack = gpio_ack_irq, - .mask = gpio_mask_irq, - .unmask = gpio_unmask_irq, - .set_type = gpio_set_irq_type, - .set_wake = gpio_set_wake_irq, + .irq_ack = gpio_ack_irq, + .irq_mask = gpio_mask_irq, + .irq_unmask = gpio_unmask_irq, + .irq_set_type = gpio_set_irq_type, + .irq_set_wake = gpio_set_wake_irq, }; static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h index 5deee019c29..68e11d7ab79 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -34,7 +34,6 @@ typedef enum iomux_config { IOMUX_CONFIG_ALT6, IOMUX_CONFIG_ALT7, IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ - IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ } iomux_pin_cfg_t; /* These 2 defines are for pins that may not have a mux register, but could @@ -135,6 +134,9 @@ typedef enum iomux_config { #define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) #define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) #define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__CSPI1_SCLK IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT4, 0x79c, 3, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__CSPI1_MISO IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT4, 0x7a0, 3, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__CSPI1_MOSI IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT4, 0x7a4, 3, NO_PAD_CTRL) #define MX53_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) #define MX53_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) #define MX53_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index 2277b01c855..82620af1922 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -105,6 +105,7 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_SRE_FAST (1 << 0) #define PAD_CTL_SRE_SLOW (0 << 0) +#define IOMUX_CONFIG_SION (0x1 << 4) #define MX51_NUM_GPIO_PORT 4 diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 873807f96d7..1eb339e6c85 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -301,8 +301,8 @@ #define MX51_MXC_INT_GPIO4_HIGH 57 #define MX51_MXC_INT_WDOG1 58 #define MX51_MXC_INT_WDOG2 59 -#define MX51_MXC_INT_KPP 60 -#define MX51_MXC_INT_PWM1 61 +#define MX51_INT_KPP 60 +#define MX51_INT_PWM1 61 #define MX51_INT_I2C1 62 #define MX51_INT_I2C2 63 #define MX51_MXC_INT_HS_I2C 64 @@ -335,7 +335,7 @@ #define MX51_MXC_INT_SPDIF 91 #define MX51_MXC_INT_TVE 92 #define MX51_MXC_INT_FIRI 93 -#define MX51_MXC_INT_PWM2 94 +#define MX51_INT_PWM2 94 #define MX51_MXC_INT_SLIM_EXP 95 #define MX51_INT_SSI3 96 #define MX51_MXC_INT_EMI_BOOT 97 diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index 9577cdbf7fa..d7a8e52181e 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -53,13 +53,13 @@ #define MX53_SPBA0_BASE_ADDR 0x50000000 #define MX53_SPBA0_SIZE SZ_1M -#define MX53_MMC_SDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) -#define MX53_MMC_SDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) +#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) +#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) #define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) -#define MX53_CSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) +#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) #define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) -#define MX53_MMC_SDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) -#define MX53_MMC_SDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) +#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) +#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) #define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) #define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) #define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) @@ -117,12 +117,12 @@ #define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) #define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) #define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) -#define MX53_CSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) +#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) #define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) #define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) #define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) #define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) -#define MX53_CSPI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) +#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) #define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) #define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) #define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) @@ -136,7 +136,7 @@ #define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000) #define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000) #define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000) -#define MX53_MXC_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) +#define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) #define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000) #define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000) #define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000) @@ -229,10 +229,10 @@ * Interrupt numbers */ #define MX53_INT_RESV0 0 -#define MX53_INT_MMC_SDHC1 1 -#define MX53_INT_MMC_SDHC2 2 -#define MX53_INT_MMC_SDHC3 3 -#define MX53_INT_MMC_SDHC4 4 +#define MX53_INT_ESDHC1 1 +#define MX53_INT_ESDHC2 2 +#define MX53_INT_ESDHC3 3 +#define MX53_INT_ESDHC4 4 #define MX53_INT_RESV5 5 #define MX53_INT_SDMA 6 #define MX53_INT_IOMUX 7 @@ -264,8 +264,8 @@ #define MX53_INT_UART3 33 #define MX53_INT_RESV34 34 #define MX53_INT_RESV35 35 -#define MX53_INT_CSPI1 36 -#define MX53_INT_CSPI2 37 +#define MX53_INT_ECSPI1 36 +#define MX53_INT_ECSPI2 37 #define MX53_INT_CSPI 38 #define MX53_INT_GPT 39 #define MX53_INT_EPIT1 40 diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c index c36f2630ed9..7a61ef8f471 100644 --- a/arch/arm/plat-mxc/pwm.c +++ b/arch/arm/plat-mxc/pwm.c @@ -57,7 +57,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) return -EINVAL; - if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25()) { + if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { unsigned long long c; unsigned long period_cycles, duty_cycles, prescale; u32 cr; diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index e69ed8a8c20..bc3a6be8a27 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -69,50 +69,50 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) #endif /** - * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC + * tzic_mask_irq() - Disable interrupt source "d" in the TZIC * - * @param irq interrupt source number + * @param d interrupt source */ -static void tzic_mask_irq(unsigned int irq) +static void tzic_mask_irq(struct irq_data *d) { int index, off; - index = irq >> 5; - off = irq & 0x1F; + index = d->irq >> 5; + off = d->irq & 0x1F; __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index)); } /** - * tzic_unmask_irq() - Enable interrupt number "irq" in the TZIC + * tzic_unmask_irq() - Enable interrupt source "d" in the TZIC * - * @param irq interrupt source number + * @param d interrupt source */ -static void tzic_unmask_irq(unsigned int irq) +static void tzic_unmask_irq(struct irq_data *d) { int index, off; - index = irq >> 5; - off = irq & 0x1F; + index = d->irq >> 5; + off = d->irq & 0x1F; __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index)); } static unsigned int wakeup_intr[4]; /** - * tzic_set_wake_irq() - Set interrupt number "irq" in the TZIC as a wake-up source. + * tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source. * - * @param irq interrupt source number + * @param d interrupt source * @param enable enable as wake-up if equal to non-zero * disble as wake-up if equal to zero * * @return This function returns 0 on success. */ -static int tzic_set_wake_irq(unsigned int irq, unsigned int enable) +static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable) { unsigned int index, off; - index = irq >> 5; - off = irq & 0x1F; + index = d->irq >> 5; + off = d->irq & 0x1F; if (index > 3) return -EINVAL; @@ -128,10 +128,10 @@ static int tzic_set_wake_irq(unsigned int irq, unsigned int enable) static struct mxc_irq_chip mxc_tzic_chip = { .base = { .name = "MXC_TZIC", - .ack = tzic_mask_irq, - .mask = tzic_mask_irq, - .unmask = tzic_unmask_irq, - .set_wake = tzic_set_wake_irq, + .irq_ack = tzic_mask_irq, + .irq_mask = tzic_mask_irq, + .irq_unmask = tzic_unmask_irq, + .irq_set_wake = tzic_set_wake_irq, }, #ifdef CONFIG_FIQ .set_irq_fiq = tzic_set_irq_fiq, diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c index eda4e3a11a3..1e88ecb846d 100644 --- a/arch/arm/plat-nomadik/gpio.c +++ b/arch/arm/plat-nomadik/gpio.c @@ -356,13 +356,13 @@ static inline int nmk_gpio_get_bitmask(int gpio) return 1 << (gpio % 32); } -static void nmk_gpio_irq_ack(unsigned int irq) +static void nmk_gpio_irq_ack(struct irq_data *d) { int gpio; struct nmk_gpio_chip *nmk_chip; - gpio = NOMADIK_IRQ_TO_GPIO(irq); - nmk_chip = get_irq_chip_data(irq); + gpio = NOMADIK_IRQ_TO_GPIO(d->irq); + nmk_chip = irq_data_get_irq_chip_data(d); if (!nmk_chip) return; writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); @@ -401,7 +401,7 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, } } -static int nmk_gpio_irq_modify(unsigned int irq, enum nmk_gpio_irq_type which, +static int nmk_gpio_irq_modify(struct irq_data *d, enum nmk_gpio_irq_type which, bool enable) { int gpio; @@ -409,8 +409,8 @@ static int nmk_gpio_irq_modify(unsigned int irq, enum nmk_gpio_irq_type which, unsigned long flags; u32 bitmask; - gpio = NOMADIK_IRQ_TO_GPIO(irq); - nmk_chip = get_irq_chip_data(irq); + gpio = NOMADIK_IRQ_TO_GPIO(d->irq); + nmk_chip = irq_data_get_irq_chip_data(d); bitmask = nmk_gpio_get_bitmask(gpio); if (!nmk_chip) return -EINVAL; @@ -422,24 +422,24 @@ static int nmk_gpio_irq_modify(unsigned int irq, enum nmk_gpio_irq_type which, return 0; } -static void nmk_gpio_irq_mask(unsigned int irq) +static void nmk_gpio_irq_mask(struct irq_data *d) { - nmk_gpio_irq_modify(irq, NORMAL, false); + nmk_gpio_irq_modify(d, NORMAL, false); } -static void nmk_gpio_irq_unmask(unsigned int irq) +static void nmk_gpio_irq_unmask(struct irq_data *d) { - nmk_gpio_irq_modify(irq, NORMAL, true); + nmk_gpio_irq_modify(d, NORMAL, true); } -static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on) +static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) { struct nmk_gpio_chip *nmk_chip; unsigned long flags; int gpio; - gpio = NOMADIK_IRQ_TO_GPIO(irq); - nmk_chip = get_irq_chip_data(irq); + gpio = NOMADIK_IRQ_TO_GPIO(d->irq); + nmk_chip = irq_data_get_irq_chip_data(d); if (!nmk_chip) return -EINVAL; @@ -457,9 +457,9 @@ static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on) return 0; } -static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type) +static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) { - struct irq_desc *desc = irq_to_desc(irq); + struct irq_desc *desc = irq_to_desc(d->irq); bool enabled = !(desc->status & IRQ_DISABLED); bool wake = desc->wake_depth; int gpio; @@ -467,8 +467,8 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type) unsigned long flags; u32 bitmask; - gpio = NOMADIK_IRQ_TO_GPIO(irq); - nmk_chip = get_irq_chip_data(irq); + gpio = NOMADIK_IRQ_TO_GPIO(d->irq); + nmk_chip = irq_data_get_irq_chip_data(d); bitmask = nmk_gpio_get_bitmask(gpio); if (!nmk_chip) return -EINVAL; @@ -507,11 +507,11 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type) static struct irq_chip nmk_gpio_irq_chip = { .name = "Nomadik-GPIO", - .ack = nmk_gpio_irq_ack, - .mask = nmk_gpio_irq_mask, - .unmask = nmk_gpio_irq_unmask, - .set_type = nmk_gpio_irq_set_type, - .set_wake = nmk_gpio_irq_set_wake, + .irq_ack = nmk_gpio_irq_ack, + .irq_mask = nmk_gpio_irq_mask, + .irq_unmask = nmk_gpio_irq_unmask, + .irq_set_type = nmk_gpio_irq_set_type, + .irq_set_wake = nmk_gpio_irq_set_wake, }; static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) @@ -522,12 +522,12 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) u32 pending; unsigned int first_irq; - if (host_chip->mask_ack) - host_chip->mask_ack(irq); + if (host_chip->irq_mask_ack) + host_chip->irq_mask_ack(&desc->irq_data); else { - host_chip->mask(irq); - if (host_chip->ack) - host_chip->ack(irq); + host_chip->irq_mask(&desc->irq_data); + if (host_chip->irq_ack) + host_chip->irq_ack(&desc->irq_data); } nmk_chip = get_irq_data(irq); @@ -537,7 +537,7 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) generic_handle_irq(gpio_irq); } - host_chip->unmask(irq); + host_chip->irq_unmask(&desc->irq_data); } static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h index 74b62f10d07..4d6dd4c39b7 100644 --- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h +++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h @@ -13,6 +13,14 @@ #include <linux/workqueue.h> #include <linux/interrupt.h> +/* + * Maxium size for a single dma descriptor + * Size is limited to 16 bits. + * Size is in the units of addr-widths (1,2,4,8 bytes) + * Larger transfers will be split up to multiple linked desc + */ +#define STEDMA40_MAX_SEG_SIZE 0xFFFF + /* dev types for memcpy */ #define STEDMA40_DEV_DST_MEMORY (-1) #define STEDMA40_DEV_SRC_MEMORY (-1) diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 18fe3cb195d..b6333ae3f92 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -144,12 +144,9 @@ config OMAP_IOMMU_DEBUG config OMAP_IOMMU_IVA2 bool -choice - prompt "System timer" - default OMAP_32K_TIMER if !ARCH_OMAP15XX - config OMAP_MPU_TIMER bool "Use mpu timer" + depends on ARCH_OMAP1 help Select this option if you want to use the OMAP mpu timer. This timer provides more intra-tick resolution than the 32KHz timer, @@ -158,6 +155,7 @@ config OMAP_MPU_TIMER config OMAP_32K_TIMER bool "Use 32KHz timer" depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS + default y if (ARCH_OMAP16XX || ARCH_OMAP2PLUS) help Select this option if you want to enable the OMAP 32KHz timer. This timer saves power compared to the OMAP_MPU_TIMER, and has @@ -165,8 +163,6 @@ config OMAP_32K_TIMER intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is currently only available for OMAP16XX, 24XX, 34XX and OMAP4. -endchoice - config OMAP3_L2_AUX_SECURE_SAVE_RESTORE bool "OMAP3 HS/EMU save and restore for L2 AUX control register" depends on ARCH_OMAP3 && PM diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c index ea4644021fb..862dda95d61 100644 --- a/arch/arm/plat-omap/counter_32k.c +++ b/arch/arm/plat-omap/counter_32k.c @@ -36,8 +36,6 @@ #define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410 -#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) - #include <linux/clocksource.h> /* @@ -122,12 +120,24 @@ static DEFINE_CLOCK_DATA(cd); #define SC_MULT 4000000000u #define SC_SHIFT 17 -unsigned long long notrace sched_clock(void) +static inline unsigned long long notrace _omap_32k_sched_clock(void) { u32 cyc = clocksource_32k.read(&clocksource_32k); return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT); } +#ifndef CONFIG_OMAP_MPU_TIMER +unsigned long long notrace sched_clock(void) +{ + return _omap_32k_sched_clock(); +} +#else +unsigned long long notrace omap_32k_sched_clock(void) +{ + return _omap_32k_sched_clock(); +} +#endif + static void notrace omap_update_sched_clock(void) { u32 cyc = clocksource_32k.read(&clocksource_32k); @@ -160,7 +170,7 @@ void read_persistent_clock(struct timespec *ts) *ts = *tsp; } -static int __init omap_init_clocksource_32k(void) +int __init omap_init_clocksource_32k(void) { static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; @@ -195,7 +205,3 @@ static int __init omap_init_clocksource_32k(void) } return 0; } -arch_initcall(omap_init_clocksource_32k); - -#endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */ - diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index c4b2b478b1a..85363084cc1 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -53,7 +53,7 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; #endif #define OMAP_DMA_ACTIVE 0x01 -#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe +#define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) @@ -1873,7 +1873,7 @@ static int omap2_dma_handle_ch(int ch) printk(KERN_INFO "DMA misaligned error with device %d\n", dma_chan[ch].dev_id); - p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, ch); + p->dma_write(status, CSR, ch); p->dma_write(1 << ch, IRQSTATUS_L0, ch); /* read back the register to flush the write */ p->dma_read(IRQSTATUS_L0, ch); @@ -1893,10 +1893,9 @@ static int omap2_dma_handle_ch(int ch) OMAP_DMA_CHAIN_INCQHEAD(chain_id); status = p->dma_read(CSR, ch); + p->dma_write(status, CSR, ch); } - p->dma_write(status, CSR, ch); - if (likely(dma_chan[ch].callback != NULL)) dma_chan[ch].callback(ch, status, dma_chan[ch].data); diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 1f98e0b9484..971d1863694 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -718,7 +718,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) case METHOD_GPIO_24XX: case METHOD_GPIO_44XX: set_24xx_gpio_triggering(bank, gpio, trigger); - break; + return 0; #endif default: goto bad; @@ -729,17 +729,17 @@ bad: return -EINVAL; } -static int gpio_irq_type(unsigned irq, unsigned type) +static int gpio_irq_type(struct irq_data *d, unsigned type) { struct gpio_bank *bank; unsigned gpio; int retval; unsigned long flags; - if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) - gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); + if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) + gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); else - gpio = irq - IH_GPIO_BASE; + gpio = d->irq - IH_GPIO_BASE; if (check_gpio(gpio) < 0) return -EINVAL; @@ -752,19 +752,21 @@ static int gpio_irq_type(unsigned irq, unsigned type) && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) return -EINVAL; - bank = get_irq_chip_data(irq); + bank = irq_data_get_irq_chip_data(d); spin_lock_irqsave(&bank->lock, flags); retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); if (retval == 0) { - irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; - irq_desc[irq].status |= type; + struct irq_desc *desc = irq_to_desc(d->irq); + + desc->status &= ~IRQ_TYPE_SENSE_MASK; + desc->status |= type; } spin_unlock_irqrestore(&bank->lock, flags); if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) - __set_irq_handler_unlocked(irq, handle_level_irq); + __set_irq_handler_unlocked(d->irq, handle_level_irq); else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) - __set_irq_handler_unlocked(irq, handle_edge_irq); + __set_irq_handler_unlocked(d->irq, handle_edge_irq); return retval; } @@ -1021,15 +1023,15 @@ static void _reset_gpio(struct gpio_bank *bank, int gpio) } /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ -static int gpio_wake_enable(unsigned int irq, unsigned int enable) +static int gpio_wake_enable(struct irq_data *d, unsigned int enable) { - unsigned int gpio = irq - IH_GPIO_BASE; + unsigned int gpio = d->irq - IH_GPIO_BASE; struct gpio_bank *bank; int retval; if (check_gpio(gpio) < 0) return -ENODEV; - bank = get_irq_chip_data(irq); + bank = irq_data_get_irq_chip_data(d); retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); return retval; @@ -1142,7 +1144,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) u32 retrigger = 0; int unmasked = 0; - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); bank = get_irq_data(irq); #ifdef CONFIG_ARCH_OMAP1 @@ -1199,7 +1201,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) configured, we could unmask GPIO bank interrupt immediately */ if (!level_mask && !unmasked) { unmasked = 1; - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); } isr |= retrigger; @@ -1235,41 +1237,40 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) interrupt */ exit: if (!unmasked) - desc->chip->unmask(irq); - + desc->irq_data.chip->irq_unmask(&desc->irq_data); } -static void gpio_irq_shutdown(unsigned int irq) +static void gpio_irq_shutdown(struct irq_data *d) { - unsigned int gpio = irq - IH_GPIO_BASE; - struct gpio_bank *bank = get_irq_chip_data(irq); + unsigned int gpio = d->irq - IH_GPIO_BASE; + struct gpio_bank *bank = irq_data_get_irq_chip_data(d); _reset_gpio(bank, gpio); } -static void gpio_ack_irq(unsigned int irq) +static void gpio_ack_irq(struct irq_data *d) { - unsigned int gpio = irq - IH_GPIO_BASE; - struct gpio_bank *bank = get_irq_chip_data(irq); + unsigned int gpio = d->irq - IH_GPIO_BASE; + struct gpio_bank *bank = irq_data_get_irq_chip_data(d); _clear_gpio_irqstatus(bank, gpio); } -static void gpio_mask_irq(unsigned int irq) +static void gpio_mask_irq(struct irq_data *d) { - unsigned int gpio = irq - IH_GPIO_BASE; - struct gpio_bank *bank = get_irq_chip_data(irq); + unsigned int gpio = d->irq - IH_GPIO_BASE; + struct gpio_bank *bank = irq_data_get_irq_chip_data(d); _set_gpio_irqenable(bank, gpio, 0); _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); } -static void gpio_unmask_irq(unsigned int irq) +static void gpio_unmask_irq(struct irq_data *d) { - unsigned int gpio = irq - IH_GPIO_BASE; - struct gpio_bank *bank = get_irq_chip_data(irq); + unsigned int gpio = d->irq - IH_GPIO_BASE; + struct gpio_bank *bank = irq_data_get_irq_chip_data(d); unsigned int irq_mask = 1 << get_gpio_index(gpio); - struct irq_desc *desc = irq_to_desc(irq); + struct irq_desc *desc = irq_to_desc(d->irq); u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK; if (trigger) @@ -1287,12 +1288,12 @@ static void gpio_unmask_irq(unsigned int irq) static struct irq_chip gpio_irq_chip = { .name = "GPIO", - .shutdown = gpio_irq_shutdown, - .ack = gpio_ack_irq, - .mask = gpio_mask_irq, - .unmask = gpio_unmask_irq, - .set_type = gpio_irq_type, - .set_wake = gpio_wake_enable, + .irq_shutdown = gpio_irq_shutdown, + .irq_ack = gpio_ack_irq, + .irq_mask = gpio_mask_irq, + .irq_unmask = gpio_unmask_irq, + .irq_set_type = gpio_irq_type, + .irq_set_wake = gpio_wake_enable, }; /*---------------------------------------------------------------------*/ @@ -1301,36 +1302,36 @@ static struct irq_chip gpio_irq_chip = { /* MPUIO uses the always-on 32k clock */ -static void mpuio_ack_irq(unsigned int irq) +static void mpuio_ack_irq(struct irq_data *d) { /* The ISR is reset automatically, so do nothing here. */ } -static void mpuio_mask_irq(unsigned int irq) +static void mpuio_mask_irq(struct irq_data *d) { - unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); - struct gpio_bank *bank = get_irq_chip_data(irq); + unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); + struct gpio_bank *bank = irq_data_get_irq_chip_data(d); _set_gpio_irqenable(bank, gpio, 0); } -static void mpuio_unmask_irq(unsigned int irq) +static void mpuio_unmask_irq(struct irq_data *d) { - unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); - struct gpio_bank *bank = get_irq_chip_data(irq); + unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); + struct gpio_bank *bank = irq_data_get_irq_chip_data(d); _set_gpio_irqenable(bank, gpio, 1); } static struct irq_chip mpuio_irq_chip = { .name = "MPUIO", - .ack = mpuio_ack_irq, - .mask = mpuio_mask_irq, - .unmask = mpuio_unmask_irq, - .set_type = gpio_irq_type, + .irq_ack = mpuio_ack_irq, + .irq_mask = mpuio_mask_irq, + .irq_unmask = mpuio_unmask_irq, + .irq_set_type = gpio_irq_type, #ifdef CONFIG_ARCH_OMAP16XX /* REVISIT: assuming only 16xx supports MPUIO wake events */ - .set_wake = gpio_wake_enable, + .irq_set_wake = gpio_wake_enable, #endif }; @@ -1671,7 +1672,9 @@ static void __init omap_gpio_chip_init(struct gpio_bank *bank) for (j = bank->virtual_irq_start; j < bank->virtual_irq_start + bank_width; j++) { - lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); + struct irq_desc *d = irq_to_desc(j); + + lockdep_set_class(&d->lock, &gpio_lock_class); set_irq_chip_data(j, bank); if (bank_is_mpuio(bank)) set_irq_chip(j, &mpuio_irq_chip); diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 6b8088ec74a..29b2afb4288 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -35,6 +35,9 @@ struct sys_timer; extern void omap_map_common_io(void); extern struct sys_timer omap_timer; +extern bool omap_32k_timer_init(void); +extern int __init omap_init_clocksource_32k(void); +extern unsigned long long notrace omap_32k_sched_clock(void); extern void omap_reserve(void); diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h index 72f433d7d82..affe87e9ece 100644 --- a/arch/arm/plat-omap/include/plat/onenand.h +++ b/arch/arm/plat-omap/include/plat/onenand.h @@ -23,6 +23,7 @@ struct omap_onenand_platform_data { int (*onenand_setup)(void __iomem *, int freq); int dma_channel; u8 flags; + u8 regulator_can_sleep; }; #define ONENAND_MAX_PARTITIONS 8 diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h index 0ff123399f3..5bd204e55c3 100644 --- a/arch/arm/plat-omap/include/plat/voltage.h +++ b/arch/arm/plat-omap/include/plat/voltage.h @@ -14,6 +14,8 @@ #ifndef __ARCH_ARM_MACH_OMAP2_VOLTAGE_H #define __ARCH_ARM_MACH_OMAP2_VOLTAGE_H +#include <linux/err.h> + #define VOLTSCALE_VPFORCEUPDATE 1 #define VOLTSCALE_VCBYPASS 2 @@ -65,9 +67,6 @@ struct voltagedomain { char *name; }; -/* API to get the voltagedomain pointer */ -struct voltagedomain *omap_voltage_domain_lookup(char *name); - /** * struct omap_volt_data - Omap voltage specific data. * @voltage_nominal: The possible voltage value in uV @@ -131,16 +130,26 @@ int omap_voltage_register_pmic(struct voltagedomain *voltdm, struct omap_volt_pmic_info *pmic_info); void omap_change_voltscale_method(struct voltagedomain *voltdm, int voltscale_method); +/* API to get the voltagedomain pointer */ +struct voltagedomain *omap_voltage_domain_lookup(char *name); + int omap_voltage_late_init(void); #else static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm, - struct omap_volt_pmic_info *pmic_info) {} + struct omap_volt_pmic_info *pmic_info) +{ + return -EINVAL; +} static inline void omap_change_voltscale_method(struct voltagedomain *voltdm, int voltscale_method) {} static inline int omap_voltage_late_init(void) { return -EINVAL; } +static inline struct voltagedomain *omap_voltage_domain_lookup(char *name) +{ + return ERR_PTR(-EINVAL); +} #endif #endif diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index e814803d474..5f352231481 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -232,20 +232,19 @@ EXPORT_SYMBOL(orion_gpio_set_blink); * polarity LEVEL mask * ****************************************************************************/ - -static void gpio_irq_ack(u32 irq) +static void gpio_irq_ack(struct irq_data *d) { - int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK; + int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - int pin = irq_to_gpio(irq); + int pin = irq_to_gpio(d->irq); writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin)); } } -static void gpio_irq_mask(u32 irq) +static void gpio_irq_mask(struct irq_data *d) { - int pin = irq_to_gpio(irq); - int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK; + int pin = irq_to_gpio(d->irq); + int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ? GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin); u32 u = readl(reg); @@ -253,10 +252,10 @@ static void gpio_irq_mask(u32 irq) writel(u, reg); } -static void gpio_irq_unmask(u32 irq) +static void gpio_irq_unmask(struct irq_data *d) { - int pin = irq_to_gpio(irq); - int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK; + int pin = irq_to_gpio(d->irq); + int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ? GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin); u32 u = readl(reg); @@ -264,20 +263,20 @@ static void gpio_irq_unmask(u32 irq) writel(u, reg); } -static int gpio_irq_set_type(u32 irq, u32 type) +static int gpio_irq_set_type(struct irq_data *d, u32 type) { - int pin = irq_to_gpio(irq); + int pin = irq_to_gpio(d->irq); struct irq_desc *desc; u32 u; u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)); if (!u) { printk(KERN_ERR "orion gpio_irq_set_type failed " - "(irq %d, pin %d).\n", irq, pin); + "(irq %d, pin %d).\n", d->irq, pin); return -EINVAL; } - desc = irq_desc + irq; + desc = irq_desc + d->irq; /* * Set edge/level type. @@ -287,7 +286,7 @@ static int gpio_irq_set_type(u32 irq, u32 type) } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { desc->handle_irq = handle_level_irq; } else { - printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type); + printk(KERN_ERR "failed to set irq=%d (type=%d)\n", d->irq, type); return -EINVAL; } @@ -325,10 +324,10 @@ static int gpio_irq_set_type(u32 irq, u32 type) struct irq_chip orion_gpio_irq_chip = { .name = "orion_gpio_irq", - .ack = gpio_irq_ack, - .mask = gpio_irq_mask, - .unmask = gpio_irq_unmask, - .set_type = gpio_irq_set_type, + .irq_ack = gpio_irq_ack, + .irq_mask = gpio_irq_mask, + .irq_unmask = gpio_irq_unmask, + .irq_set_type = gpio_irq_set_type, }; void orion_gpio_irq_handler(int pinoff) diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index 3f9d34fc738..7d0c7eb59f0 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c @@ -14,31 +14,31 @@ #include <linux/io.h> #include <plat/irq.h> -static void orion_irq_mask(u32 irq) +static void orion_irq_mask(struct irq_data *d) { - void __iomem *maskaddr = get_irq_chip_data(irq); + void __iomem *maskaddr = irq_data_get_irq_chip_data(d); u32 mask; mask = readl(maskaddr); - mask &= ~(1 << (irq & 31)); + mask &= ~(1 << (d->irq & 31)); writel(mask, maskaddr); } -static void orion_irq_unmask(u32 irq) +static void orion_irq_unmask(struct irq_data *d) { - void __iomem *maskaddr = get_irq_chip_data(irq); + void __iomem *maskaddr = irq_data_get_irq_chip_data(d); u32 mask; mask = readl(maskaddr); - mask |= 1 << (irq & 31); + mask |= 1 << (d->irq & 31); writel(mask, maskaddr); } static struct irq_chip orion_irq_chip = { .name = "orion_irq", - .mask = orion_irq_mask, - .mask_ack = orion_irq_mask, - .unmask = orion_irq_unmask, + .irq_mask = orion_irq_mask, + .irq_mask_ack = orion_irq_mask, + .irq_unmask = orion_irq_unmask, }; void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c index 98548c6903a..e7de6ae2a1e 100644 --- a/arch/arm/plat-pxa/gpio.c +++ b/arch/arm/plat-pxa/gpio.c @@ -155,10 +155,10 @@ static inline void update_edge_detect(struct pxa_gpio_chip *c) __raw_writel(gfer, c->regbase + GFER_OFFSET); } -static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) +static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) { struct pxa_gpio_chip *c; - int gpio = irq_to_gpio(irq); + int gpio = irq_to_gpio(d->irq); unsigned long gpdr, mask = GPIO_bit(gpio); c = gpio_to_chip(gpio); @@ -195,7 +195,7 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) update_edge_detect(c); - pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, + pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); return 0; @@ -227,17 +227,17 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) } while (loop); } -static void pxa_ack_muxed_gpio(unsigned int irq) +static void pxa_ack_muxed_gpio(struct irq_data *d) { - int gpio = irq_to_gpio(irq); + int gpio = irq_to_gpio(d->irq); struct pxa_gpio_chip *c = gpio_to_chip(gpio); __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); } -static void pxa_mask_muxed_gpio(unsigned int irq) +static void pxa_mask_muxed_gpio(struct irq_data *d) { - int gpio = irq_to_gpio(irq); + int gpio = irq_to_gpio(d->irq); struct pxa_gpio_chip *c = gpio_to_chip(gpio); uint32_t grer, gfer; @@ -249,9 +249,9 @@ static void pxa_mask_muxed_gpio(unsigned int irq) __raw_writel(gfer, c->regbase + GFER_OFFSET); } -static void pxa_unmask_muxed_gpio(unsigned int irq) +static void pxa_unmask_muxed_gpio(struct irq_data *d) { - int gpio = irq_to_gpio(irq); + int gpio = irq_to_gpio(d->irq); struct pxa_gpio_chip *c = gpio_to_chip(gpio); c->irq_mask |= GPIO_bit(gpio); @@ -260,10 +260,10 @@ static void pxa_unmask_muxed_gpio(unsigned int irq) static struct irq_chip pxa_muxed_gpio_chip = { .name = "GPIO", - .ack = pxa_ack_muxed_gpio, - .mask = pxa_mask_muxed_gpio, - .unmask = pxa_unmask_muxed_gpio, - .set_type = pxa_gpio_irq_type, + .irq_ack = pxa_ack_muxed_gpio, + .irq_mask = pxa_mask_muxed_gpio, + .irq_unmask = pxa_unmask_muxed_gpio, + .irq_set_type = pxa_gpio_irq_type, }; void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn) @@ -291,7 +291,7 @@ void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn) /* Install handler for GPIO>=2 edge detect interrupts */ set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler); - pxa_muxed_gpio_chip.set_wake = fn; + pxa_muxed_gpio_chip.irq_set_wake = fn; } #ifdef CONFIG_PM diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h index 44248cb926a..1ddd2b97a72 100644 --- a/arch/arm/plat-pxa/include/plat/gpio.h +++ b/arch/arm/plat-pxa/include/plat/gpio.h @@ -1,6 +1,8 @@ #ifndef __PLAT_GPIO_H #define __PLAT_GPIO_H +struct irq_data; + /* * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with * one set of registers. The register offsets are organized below: @@ -56,7 +58,7 @@ static inline void gpio_set_value(unsigned gpio, int value) */ extern int pxa_last_gpio; -typedef int (*set_wake_t)(unsigned int irq, unsigned int on); +typedef int (*set_wake_t)(struct irq_data *d, unsigned int on); extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn); #endif /* __PLAT_GPIO_H */ diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 8a42bc48dbf..268f3ed0a10 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -194,7 +194,6 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_ memcpy(&s3c2410ts_info, hard_s3c2410ts_info, sizeof(struct s3c2410_ts_mach_info)); s3c_device_ts.dev.platform_data = &s3c2410ts_info; } -EXPORT_SYMBOL(s3c24xx_ts_set_platdata); /* USB Device (Gadget)*/ diff --git a/arch/arm/plat-s3c24xx/include/plat/irq.h b/arch/arm/plat-s3c24xx/include/plat/irq.h index 69e1be8bec3..ec087d6054b 100644 --- a/arch/arm/plat-s3c24xx/include/plat/irq.h +++ b/arch/arm/plat-s3c24xx/include/plat/irq.h @@ -107,9 +107,9 @@ s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group) /* exported for use in arch/arm/mach-s3c2410 */ #ifdef CONFIG_PM -extern int s3c_irq_wake(unsigned int irqno, unsigned int state); +extern int s3c_irq_wake(struct irq_data *data, unsigned int state); #else #define s3c_irq_wake NULL #endif -extern int s3c_irqext_type(unsigned int irq, unsigned int type); +extern int s3c_irqext_type(struct irq_data *d, unsigned int type); diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c index ea8dea3339a..c3624d89863 100644 --- a/arch/arm/plat-s3c24xx/irq-pm.c +++ b/arch/arm/plat-s3c24xx/irq-pm.c @@ -15,11 +15,14 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/sysdev.h> +#include <linux/irq.h> #include <plat/cpu.h> #include <plat/pm.h> #include <plat/irq.h> +#include <asm/irq.h> + /* state for IRQs over sleep */ /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources @@ -30,15 +33,15 @@ unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; unsigned long s3c_irqwake_eintallow = 0x0000fff0L; -int s3c_irq_wake(unsigned int irqno, unsigned int state) +int s3c_irq_wake(struct irq_data *data, unsigned int state) { - unsigned long irqbit = 1 << (irqno - IRQ_EINT0); + unsigned long irqbit = 1 << (data->irq - IRQ_EINT0); if (!(s3c_irqwake_intallow & irqbit)) return -ENOENT; printk(KERN_INFO "wake %s for irq %d\n", - state ? "enabled" : "disabled", irqno); + state ? "enabled" : "disabled", data->irq); if (!state) s3c_irqwake_intmask |= irqbit; diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index ad0d44ef1f9..4434cb56bd9 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c @@ -34,30 +34,29 @@ #include <plat/irq.h> static void -s3c_irq_mask(unsigned int irqno) +s3c_irq_mask(struct irq_data *data) { + unsigned int irqno = data->irq - IRQ_EINT0; unsigned long mask; - irqno -= IRQ_EINT0; - mask = __raw_readl(S3C2410_INTMSK); mask |= 1UL << irqno; __raw_writel(mask, S3C2410_INTMSK); } static inline void -s3c_irq_ack(unsigned int irqno) +s3c_irq_ack(struct irq_data *data) { - unsigned long bitval = 1UL << (irqno - IRQ_EINT0); + unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); __raw_writel(bitval, S3C2410_SRCPND); __raw_writel(bitval, S3C2410_INTPND); } static inline void -s3c_irq_maskack(unsigned int irqno) +s3c_irq_maskack(struct irq_data *data) { - unsigned long bitval = 1UL << (irqno - IRQ_EINT0); + unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); unsigned long mask; mask = __raw_readl(S3C2410_INTMSK); @@ -69,8 +68,9 @@ s3c_irq_maskack(unsigned int irqno) static void -s3c_irq_unmask(unsigned int irqno) +s3c_irq_unmask(struct irq_data *data) { + unsigned int irqno = data->irq; unsigned long mask; if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23) @@ -85,40 +85,39 @@ s3c_irq_unmask(unsigned int irqno) struct irq_chip s3c_irq_level_chip = { .name = "s3c-level", - .ack = s3c_irq_maskack, - .mask = s3c_irq_mask, - .unmask = s3c_irq_unmask, - .set_wake = s3c_irq_wake + .irq_ack = s3c_irq_maskack, + .irq_mask = s3c_irq_mask, + .irq_unmask = s3c_irq_unmask, + .irq_set_wake = s3c_irq_wake }; struct irq_chip s3c_irq_chip = { .name = "s3c", - .ack = s3c_irq_ack, - .mask = s3c_irq_mask, - .unmask = s3c_irq_unmask, - .set_wake = s3c_irq_wake + .irq_ack = s3c_irq_ack, + .irq_mask = s3c_irq_mask, + .irq_unmask = s3c_irq_unmask, + .irq_set_wake = s3c_irq_wake }; static void -s3c_irqext_mask(unsigned int irqno) +s3c_irqext_mask(struct irq_data *data) { + unsigned int irqno = data->irq - EXTINT_OFF; unsigned long mask; - irqno -= EXTINT_OFF; - mask = __raw_readl(S3C24XX_EINTMASK); mask |= ( 1UL << irqno); __raw_writel(mask, S3C24XX_EINTMASK); } static void -s3c_irqext_ack(unsigned int irqno) +s3c_irqext_ack(struct irq_data *data) { unsigned long req; unsigned long bit; unsigned long mask; - bit = 1UL << (irqno - EXTINT_OFF); + bit = 1UL << (data->irq - EXTINT_OFF); mask = __raw_readl(S3C24XX_EINTMASK); @@ -129,64 +128,57 @@ s3c_irqext_ack(unsigned int irqno) /* not sure if we should be acking the parent irq... */ - if (irqno <= IRQ_EINT7 ) { + if (data->irq <= IRQ_EINT7) { if ((req & 0xf0) == 0) - s3c_irq_ack(IRQ_EINT4t7); + s3c_irq_ack(irq_get_irq_data(IRQ_EINT4t7)); } else { if ((req >> 8) == 0) - s3c_irq_ack(IRQ_EINT8t23); + s3c_irq_ack(irq_get_irq_data(IRQ_EINT8t23)); } } static void -s3c_irqext_unmask(unsigned int irqno) +s3c_irqext_unmask(struct irq_data *data) { + unsigned int irqno = data->irq - EXTINT_OFF; unsigned long mask; - irqno -= EXTINT_OFF; - mask = __raw_readl(S3C24XX_EINTMASK); - mask &= ~( 1UL << irqno); + mask &= ~(1UL << irqno); __raw_writel(mask, S3C24XX_EINTMASK); } int -s3c_irqext_type(unsigned int irq, unsigned int type) +s3c_irqext_type(struct irq_data *data, unsigned int type) { void __iomem *extint_reg; void __iomem *gpcon_reg; unsigned long gpcon_offset, extint_offset; unsigned long newvalue = 0, value; - if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3)) - { + if ((data->irq >= IRQ_EINT0) && (data->irq <= IRQ_EINT3)) { gpcon_reg = S3C2410_GPFCON; extint_reg = S3C24XX_EXTINT0; - gpcon_offset = (irq - IRQ_EINT0) * 2; - extint_offset = (irq - IRQ_EINT0) * 4; - } - else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7)) - { + gpcon_offset = (data->irq - IRQ_EINT0) * 2; + extint_offset = (data->irq - IRQ_EINT0) * 4; + } else if ((data->irq >= IRQ_EINT4) && (data->irq <= IRQ_EINT7)) { gpcon_reg = S3C2410_GPFCON; extint_reg = S3C24XX_EXTINT0; - gpcon_offset = (irq - (EXTINT_OFF)) * 2; - extint_offset = (irq - (EXTINT_OFF)) * 4; - } - else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15)) - { + gpcon_offset = (data->irq - (EXTINT_OFF)) * 2; + extint_offset = (data->irq - (EXTINT_OFF)) * 4; + } else if ((data->irq >= IRQ_EINT8) && (data->irq <= IRQ_EINT15)) { gpcon_reg = S3C2410_GPGCON; extint_reg = S3C24XX_EXTINT1; - gpcon_offset = (irq - IRQ_EINT8) * 2; - extint_offset = (irq - IRQ_EINT8) * 4; - } - else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23)) - { + gpcon_offset = (data->irq - IRQ_EINT8) * 2; + extint_offset = (data->irq - IRQ_EINT8) * 4; + } else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) { gpcon_reg = S3C2410_GPGCON; extint_reg = S3C24XX_EXTINT2; - gpcon_offset = (irq - IRQ_EINT8) * 2; - extint_offset = (irq - IRQ_EINT16) * 4; - } else + gpcon_offset = (data->irq - IRQ_EINT8) * 2; + extint_offset = (data->irq - IRQ_EINT16) * 4; + } else { return -1; + } /* Set the GPIO to external interrupt mode */ value = __raw_readl(gpcon_reg); @@ -234,20 +226,20 @@ s3c_irqext_type(unsigned int irq, unsigned int type) static struct irq_chip s3c_irqext_chip = { .name = "s3c-ext", - .mask = s3c_irqext_mask, - .unmask = s3c_irqext_unmask, - .ack = s3c_irqext_ack, - .set_type = s3c_irqext_type, - .set_wake = s3c_irqext_wake + .irq_mask = s3c_irqext_mask, + .irq_unmask = s3c_irqext_unmask, + .irq_ack = s3c_irqext_ack, + .irq_set_type = s3c_irqext_type, + .irq_set_wake = s3c_irqext_wake }; static struct irq_chip s3c_irq_eint0t4 = { .name = "s3c-ext0", - .ack = s3c_irq_ack, - .mask = s3c_irq_mask, - .unmask = s3c_irq_unmask, - .set_wake = s3c_irq_wake, - .set_type = s3c_irqext_type, + .irq_ack = s3c_irq_ack, + .irq_mask = s3c_irq_mask, + .irq_unmask = s3c_irq_unmask, + .irq_set_wake = s3c_irq_wake, + .irq_set_type = s3c_irqext_type, }; /* mask values for the parent registers for each of the interrupt types */ @@ -261,109 +253,109 @@ static struct irq_chip s3c_irq_eint0t4 = { /* UART0 */ static void -s3c_irq_uart0_mask(unsigned int irqno) +s3c_irq_uart0_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_UART0, 7); + s3c_irqsub_mask(data->irq, INTMSK_UART0, 7); } static void -s3c_irq_uart0_unmask(unsigned int irqno) +s3c_irq_uart0_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_UART0); + s3c_irqsub_unmask(data->irq, INTMSK_UART0); } static void -s3c_irq_uart0_ack(unsigned int irqno) +s3c_irq_uart0_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_UART0, 7); + s3c_irqsub_maskack(data->irq, INTMSK_UART0, 7); } static struct irq_chip s3c_irq_uart0 = { .name = "s3c-uart0", - .mask = s3c_irq_uart0_mask, - .unmask = s3c_irq_uart0_unmask, - .ack = s3c_irq_uart0_ack, + .irq_mask = s3c_irq_uart0_mask, + .irq_unmask = s3c_irq_uart0_unmask, + .irq_ack = s3c_irq_uart0_ack, }; /* UART1 */ static void -s3c_irq_uart1_mask(unsigned int irqno) +s3c_irq_uart1_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3); + s3c_irqsub_mask(data->irq, INTMSK_UART1, 7 << 3); } static void -s3c_irq_uart1_unmask(unsigned int irqno) +s3c_irq_uart1_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_UART1); + s3c_irqsub_unmask(data->irq, INTMSK_UART1); } static void -s3c_irq_uart1_ack(unsigned int irqno) +s3c_irq_uart1_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3); + s3c_irqsub_maskack(data->irq, INTMSK_UART1, 7 << 3); } static struct irq_chip s3c_irq_uart1 = { .name = "s3c-uart1", - .mask = s3c_irq_uart1_mask, - .unmask = s3c_irq_uart1_unmask, - .ack = s3c_irq_uart1_ack, + .irq_mask = s3c_irq_uart1_mask, + .irq_unmask = s3c_irq_uart1_unmask, + .irq_ack = s3c_irq_uart1_ack, }; /* UART2 */ static void -s3c_irq_uart2_mask(unsigned int irqno) +s3c_irq_uart2_mask(struct irq_data *data) { - s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6); + s3c_irqsub_mask(data->irq, INTMSK_UART2, 7 << 6); } static void -s3c_irq_uart2_unmask(unsigned int irqno) +s3c_irq_uart2_unmask(struct irq_data *data) { - s3c_irqsub_unmask(irqno, INTMSK_UART2); + s3c_irqsub_unmask(data->irq, INTMSK_UART2); } static void -s3c_irq_uart2_ack(unsigned int irqno) +s3c_irq_uart2_ack(struct irq_data *data) { - s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6); + s3c_irqsub_maskack(data->irq, INTMSK_UART2, 7 << 6); } static struct irq_chip s3c_irq_uart2 = { .name = "s3c-uart2", - .mask = s3c_irq_uart2_mask, - .unmask = s3c_irq_uart2_unmask, - .ack = s3c_irq_uart2_ack, + .irq_mask = s3c_irq_uart2_mask, + .irq_unmask = s3c_irq_uart2_unmask, + .irq_ack = s3c_irq_uart2_ack, }; /* ADC and Touchscreen */ static void -s3c_irq_adc_mask(unsigned int irqno) +s3c_irq_adc_mask(struct irq_data *d) { - s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9); + s3c_irqsub_mask(d->irq, INTMSK_ADCPARENT, 3 << 9); } static void -s3c_irq_adc_unmask(unsigned int irqno) +s3c_irq_adc_unmask(struct irq_data *d) { - s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT); + s3c_irqsub_unmask(d->irq, INTMSK_ADCPARENT); } static void -s3c_irq_adc_ack(unsigned int irqno) +s3c_irq_adc_ack(struct irq_data *d) { - s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); + s3c_irqsub_ack(d->irq, INTMSK_ADCPARENT, 3 << 9); } static struct irq_chip s3c_irq_adc = { .name = "s3c-adc", - .mask = s3c_irq_adc_mask, - .unmask = s3c_irq_adc_unmask, - .ack = s3c_irq_adc_ack, + .irq_mask = s3c_irq_adc_mask, + .irq_unmask = s3c_irq_adc_unmask, + .irq_ack = s3c_irq_adc_ack, }; /* irq demux for adc */ diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 461f070eb62..82f2d4a3929 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -271,7 +271,7 @@ static struct clk init_clocks[] = { .ctrlbit = S3C2443_HCLKCON_DMA5, }, { .name = "hsmmc", - .id = 0, + .id = 1, .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_HSMMC, diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index 65dbfa8e0a8..deb39951a22 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -56,3 +56,29 @@ config S5P_DEV_ONENAND bool help Compile in platform device definition for OneNAND controller + +config S5P_DEV_CSIS0 + bool + help + Compile in platform device definitions for MIPI-CSIS channel 0 + +config S5P_DEV_CSIS1 + bool + help + Compile in platform device definitions for MIPI-CSIS channel 1 + +menuconfig S5P_SYSMMU + bool "SYSMMU support" + depends on ARCH_S5PV310 + help + This is a System MMU driver for Samsung ARM based Soc. + +if S5P_SYSMMU + +config S5P_SYSMMU_DEBUG + bool "Enables debug messages" + depends on S5P_SYSMMU + help + This enables SYSMMU driver debug massages. + +endif diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index de65238a7ae..92efe1adcfd 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile @@ -28,3 +28,6 @@ obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o +obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o +obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o +obj-$(CONFIG_S5P_SYSMMU) += sysmmu.o diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c index 74f7f5a5446..047d31c1bbd 100644 --- a/arch/arm/plat-s5p/cpu.c +++ b/arch/arm/plat-s5p/cpu.c @@ -108,6 +108,11 @@ static struct map_desc s5p_iodesc[] __initdata = { .pfn = __phys_to_pfn(S3C_PA_WDT), .length = SZ_4K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SROMC, + .pfn = __phys_to_pfn(S5P_PA_SROMC), + .length = SZ_4K, + .type = MT_DEVICE, }, }; diff --git a/arch/arm/plat-s5p/dev-csis0.c b/arch/arm/plat-s5p/dev-csis0.c new file mode 100644 index 00000000000..dfab1c85f54 --- /dev/null +++ b/arch/arm/plat-s5p/dev-csis0.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * + * S5P series device definition for MIPI-CSIS channel 0 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <mach/map.h> + +static struct resource s5p_mipi_csis0_resource[] = { + [0] = { + .start = S5P_PA_MIPI_CSIS0, + .end = S5P_PA_MIPI_CSIS0 + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MIPI_CSIS0, + .end = IRQ_MIPI_CSIS0, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device s5p_device_mipi_csis0 = { + .name = "s5p-mipi-csis", + .id = 0, + .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource), + .resource = s5p_mipi_csis0_resource, +}; diff --git a/arch/arm/plat-s5p/dev-csis1.c b/arch/arm/plat-s5p/dev-csis1.c new file mode 100644 index 00000000000..e3053f27fbb --- /dev/null +++ b/arch/arm/plat-s5p/dev-csis1.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * + * S5P series device definition for MIPI-CSIS channel 1 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <mach/map.h> + +static struct resource s5p_mipi_csis1_resource[] = { + [0] = { + .start = S5P_PA_MIPI_CSIS1, + .end = S5P_PA_MIPI_CSIS1 + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MIPI_CSIS1, + .end = IRQ_MIPI_CSIS1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s5p_device_mipi_csis1 = { + .name = "s5p-mipi-csis", + .id = 1, + .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource), + .resource = s5p_mipi_csis1_resource, +}; diff --git a/arch/arm/plat-s5p/include/plat/csis.h b/arch/arm/plat-s5p/include/plat/csis.h new file mode 100644 index 00000000000..51e308c7981 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/csis.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * + * S5P series MIPI CSI slave device support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef PLAT_S5P_CSIS_H_ +#define PLAT_S5P_CSIS_H_ __FILE__ + +/** + * struct s5p_platform_mipi_csis - platform data for MIPI-CSIS + * @clk_rate: bus clock frequency + * @lanes: number of data lanes used + * @alignment: data alignment in bits + * @hs_settle: HS-RX settle time + */ +struct s5p_platform_mipi_csis { + unsigned long clk_rate; + u8 lanes; + u8 alignment; + u8 hs_settle; +}; + +#endif /* PLAT_S5P_CSIS_H_ */ diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h index fef353d4451..d973d39666a 100644 --- a/arch/arm/plat-s5p/include/plat/map-s5p.h +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h @@ -15,6 +15,7 @@ #define S5P_VA_CHIPID S3C_ADDR(0x02000000) #define S5P_VA_CMU S3C_ADDR(0x02100000) +#define S5P_VA_PMU S3C_ADDR(0x02180000) #define S5P_VA_GPIO S3C_ADDR(0x02200000) #define S5P_VA_GPIO1 S5P_VA_GPIO #define S5P_VA_GPIO2 S3C_ADDR(0x02240000) diff --git a/arch/arm/plat-s5p/include/plat/regs-srom.h b/arch/arm/plat-s5p/include/plat/regs-srom.h new file mode 100644 index 00000000000..f121ab5e76c --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-srom.h @@ -0,0 +1,54 @@ +/* linux/arch/arm/plat-s5p/include/plat/regs-srom.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5P SROMC register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S5P_REGS_SROM_H +#define __ASM_PLAT_S5P_REGS_SROM_H __FILE__ + +#include <mach/map.h> + +#define S5P_SROMREG(x) (S5P_VA_SROMC + (x)) + +#define S5P_SROM_BW S5P_SROMREG(0x0) +#define S5P_SROM_BC0 S5P_SROMREG(0x4) +#define S5P_SROM_BC1 S5P_SROMREG(0x8) +#define S5P_SROM_BC2 S5P_SROMREG(0xc) +#define S5P_SROM_BC3 S5P_SROMREG(0x10) +#define S5P_SROM_BC4 S5P_SROMREG(0x14) +#define S5P_SROM_BC5 S5P_SROMREG(0x18) + +/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ + +#define S5P_SROM_BW__DATAWIDTH__SHIFT 0 +#define S5P_SROM_BW__ADDRMODE__SHIFT 1 +#define S5P_SROM_BW__WAITENABLE__SHIFT 2 +#define S5P_SROM_BW__BYTEENABLE__SHIFT 3 + +#define S5P_SROM_BW__CS_MASK 0xf + +#define S5P_SROM_BW__NCS0__SHIFT 0 +#define S5P_SROM_BW__NCS1__SHIFT 4 +#define S5P_SROM_BW__NCS2__SHIFT 8 +#define S5P_SROM_BW__NCS3__SHIFT 12 +#define S5P_SROM_BW__NCS4__SHIFT 16 +#define S5P_SROM_BW__NCS5__SHIFT 20 + +/* applies to same to BCS0 - BCS3 */ + +#define S5P_SROM_BCX__PMC__SHIFT 0 +#define S5P_SROM_BCX__TACP__SHIFT 4 +#define S5P_SROM_BCX__TCAH__SHIFT 8 +#define S5P_SROM_BCX__TCOH__SHIFT 12 +#define S5P_SROM_BCX__TACC__SHIFT 16 +#define S5P_SROM_BCX__TCOS__SHIFT 24 +#define S5P_SROM_BCX__TACS__SHIFT 28 + +#endif /* __ASM_PLAT_S5P_REGS_SROM_H */ diff --git a/arch/arm/plat-s5p/include/plat/sysmmu.h b/arch/arm/plat-s5p/include/plat/sysmmu.h new file mode 100644 index 00000000000..db298fc5438 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/sysmmu.h @@ -0,0 +1,23 @@ +/* linux/arch/arm/plat-s5p/include/plat/sysmmu.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Samsung sysmmu driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S5P_SYSMMU_H +#define __ASM_PLAT_S5P_SYSMMU_H __FILE__ + +/* debug macro */ +#ifdef CONFIG_S5P_SYSMMU_DEBUG +#define sysmmu_debug(fmt, arg...) printk(KERN_INFO "[%s] " fmt, __func__, ## arg) +#else +#define sysmmu_debug(fmt, arg...) do { } while (0) +#endif + +#endif /* __ASM_PLAT_S5P_SYSMMU_H */ diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c index 752f1a645f9..225aa25405d 100644 --- a/arch/arm/plat-s5p/irq-eint.c +++ b/arch/arm/plat-s5p/irq-eint.c @@ -28,39 +28,40 @@ #include <plat/gpio-cfg.h> #include <mach/regs-gpio.h> -static inline void s5p_irq_eint_mask(unsigned int irq) +static inline void s5p_irq_eint_mask(struct irq_data *data) { u32 mask; - mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); - mask |= eint_irq_to_bit(irq); - __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); + mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); + mask |= eint_irq_to_bit(data->irq); + __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); } -static void s5p_irq_eint_unmask(unsigned int irq) +static void s5p_irq_eint_unmask(struct irq_data *data) { u32 mask; - mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); - mask &= ~(eint_irq_to_bit(irq)); - __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); + mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); + mask &= ~(eint_irq_to_bit(data->irq)); + __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); } -static inline void s5p_irq_eint_ack(unsigned int irq) +static inline void s5p_irq_eint_ack(struct irq_data *data) { - __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); + __raw_writel(eint_irq_to_bit(data->irq), + S5P_EINT_PEND(EINT_REG_NR(data->irq))); } -static void s5p_irq_eint_maskack(unsigned int irq) +static void s5p_irq_eint_maskack(struct irq_data *data) { /* compiler should in-line these */ - s5p_irq_eint_mask(irq); - s5p_irq_eint_ack(irq); + s5p_irq_eint_mask(data); + s5p_irq_eint_ack(data); } -static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type) +static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type) { - int offs = EINT_OFFSET(irq); + int offs = EINT_OFFSET(data->irq); int shift; u32 ctrl, mask; u32 newvalue = 0; @@ -94,10 +95,10 @@ static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type) shift = (offs & 0x7) * 4; mask = 0x7 << shift; - ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq))); + ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq))); ctrl &= ~mask; ctrl |= newvalue << shift; - __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq))); + __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq))); if ((0 <= offs) && (offs < 8)) s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE); @@ -119,13 +120,13 @@ static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type) static struct irq_chip s5p_irq_eint = { .name = "s5p-eint", - .mask = s5p_irq_eint_mask, - .unmask = s5p_irq_eint_unmask, - .mask_ack = s5p_irq_eint_maskack, - .ack = s5p_irq_eint_ack, - .set_type = s5p_irq_eint_set_type, + .irq_mask = s5p_irq_eint_mask, + .irq_unmask = s5p_irq_eint_unmask, + .irq_mask_ack = s5p_irq_eint_maskack, + .irq_ack = s5p_irq_eint_ack, + .irq_set_type = s5p_irq_eint_set_type, #ifdef CONFIG_PM - .set_wake = s3c_irqext_wake, + .irq_set_wake = s3c_irqext_wake, #endif }; @@ -159,42 +160,43 @@ static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) s5p_irq_demux_eint(IRQ_EINT(24)); } -static inline void s5p_irq_vic_eint_mask(unsigned int irq) +static inline void s5p_irq_vic_eint_mask(struct irq_data *data) { - void __iomem *base = get_irq_chip_data(irq); + void __iomem *base = irq_data_get_irq_chip_data(data); - s5p_irq_eint_mask(irq); - writel(1 << EINT_OFFSET(irq), base + VIC_INT_ENABLE_CLEAR); + s5p_irq_eint_mask(data); + writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR); } -static void s5p_irq_vic_eint_unmask(unsigned int irq) +static void s5p_irq_vic_eint_unmask(struct irq_data *data) { - void __iomem *base = get_irq_chip_data(irq); + void __iomem *base = irq_data_get_irq_chip_data(data); - s5p_irq_eint_unmask(irq); - writel(1 << EINT_OFFSET(irq), base + VIC_INT_ENABLE); + s5p_irq_eint_unmask(data); + writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE); } -static inline void s5p_irq_vic_eint_ack(unsigned int irq) +static inline void s5p_irq_vic_eint_ack(struct irq_data *data) { - __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); + __raw_writel(eint_irq_to_bit(data->irq), + S5P_EINT_PEND(EINT_REG_NR(data->irq))); } -static void s5p_irq_vic_eint_maskack(unsigned int irq) +static void s5p_irq_vic_eint_maskack(struct irq_data *data) { - s5p_irq_vic_eint_mask(irq); - s5p_irq_vic_eint_ack(irq); + s5p_irq_vic_eint_mask(data); + s5p_irq_vic_eint_ack(data); } static struct irq_chip s5p_irq_vic_eint = { .name = "s5p_vic_eint", - .mask = s5p_irq_vic_eint_mask, - .unmask = s5p_irq_vic_eint_unmask, - .mask_ack = s5p_irq_vic_eint_maskack, - .ack = s5p_irq_vic_eint_ack, - .set_type = s5p_irq_eint_set_type, + .irq_mask = s5p_irq_vic_eint_mask, + .irq_unmask = s5p_irq_vic_eint_unmask, + .irq_mask_ack = s5p_irq_vic_eint_maskack, + .irq_ack = s5p_irq_vic_eint_ack, + .irq_set_type = s5p_irq_eint_set_type, #ifdef CONFIG_PM - .set_wake = s3c_irqext_wake, + .irq_set_wake = s3c_irqext_wake, #endif }; diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c index 0e5dc8cbf5e..3b6bf89d173 100644 --- a/arch/arm/plat-s5p/irq-gpioint.c +++ b/arch/arm/plat-s5p/irq-gpioint.c @@ -30,9 +30,9 @@ static struct s3c_gpio_chip *irq_chips[S5P_GPIOINT_GROUP_MAXNR]; -static int s5p_gpioint_get_group(unsigned int irq) +static int s5p_gpioint_get_group(struct irq_data *data) { - struct gpio_chip *chip = get_irq_data(irq); + struct gpio_chip *chip = irq_data_get_irq_data(data); struct s3c_gpio_chip *s3c_chip = container_of(chip, struct s3c_gpio_chip, chip); int group; @@ -44,22 +44,22 @@ static int s5p_gpioint_get_group(unsigned int irq) return group; } -static int s5p_gpioint_get_offset(unsigned int irq) +static int s5p_gpioint_get_offset(struct irq_data *data) { - struct gpio_chip *chip = get_irq_data(irq); + struct gpio_chip *chip = irq_data_get_irq_data(data); struct s3c_gpio_chip *s3c_chip = container_of(chip, struct s3c_gpio_chip, chip); - return irq - s3c_chip->irq_base; + return data->irq - s3c_chip->irq_base; } -static void s5p_gpioint_ack(unsigned int irq) +static void s5p_gpioint_ack(struct irq_data *data) { int group, offset, pend_offset; unsigned int value; - group = s5p_gpioint_get_group(irq); - offset = s5p_gpioint_get_offset(irq); + group = s5p_gpioint_get_group(data); + offset = s5p_gpioint_get_offset(data); pend_offset = group << 2; value = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset); @@ -67,13 +67,13 @@ static void s5p_gpioint_ack(unsigned int irq) __raw_writel(value, S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset); } -static void s5p_gpioint_mask(unsigned int irq) +static void s5p_gpioint_mask(struct irq_data *data) { int group, offset, mask_offset; unsigned int value; - group = s5p_gpioint_get_group(irq); - offset = s5p_gpioint_get_offset(irq); + group = s5p_gpioint_get_group(data); + offset = s5p_gpioint_get_offset(data); mask_offset = group << 2; value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); @@ -81,13 +81,13 @@ static void s5p_gpioint_mask(unsigned int irq) __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); } -static void s5p_gpioint_unmask(unsigned int irq) +static void s5p_gpioint_unmask(struct irq_data *data) { int group, offset, mask_offset; unsigned int value; - group = s5p_gpioint_get_group(irq); - offset = s5p_gpioint_get_offset(irq); + group = s5p_gpioint_get_group(data); + offset = s5p_gpioint_get_offset(data); mask_offset = group << 2; value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); @@ -95,19 +95,19 @@ static void s5p_gpioint_unmask(unsigned int irq) __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); } -static void s5p_gpioint_mask_ack(unsigned int irq) +static void s5p_gpioint_mask_ack(struct irq_data *data) { - s5p_gpioint_mask(irq); - s5p_gpioint_ack(irq); + s5p_gpioint_mask(data); + s5p_gpioint_ack(data); } -static int s5p_gpioint_set_type(unsigned int irq, unsigned int type) +static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type) { int group, offset, con_offset; unsigned int value; - group = s5p_gpioint_get_group(irq); - offset = s5p_gpioint_get_offset(irq); + group = s5p_gpioint_get_group(data); + offset = s5p_gpioint_get_offset(data); con_offset = group << 2; switch (type) { @@ -142,11 +142,11 @@ static int s5p_gpioint_set_type(unsigned int irq, unsigned int type) struct irq_chip s5p_gpioint = { .name = "s5p_gpioint", - .ack = s5p_gpioint_ack, - .mask = s5p_gpioint_mask, - .mask_ack = s5p_gpioint_mask_ack, - .unmask = s5p_gpioint_unmask, - .set_type = s5p_gpioint_set_type, + .irq_ack = s5p_gpioint_ack, + .irq_mask = s5p_gpioint_mask, + .irq_mask_ack = s5p_gpioint_mask_ack, + .irq_unmask = s5p_gpioint_unmask, + .irq_set_type = s5p_gpioint_set_type, }; static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c index dc33b9ecda4..5259ad458bc 100644 --- a/arch/arm/plat-s5p/irq-pm.c +++ b/arch/arm/plat-s5p/irq-pm.c @@ -37,14 +37,14 @@ unsigned long s3c_irqwake_intallow = 0x00000006L; unsigned long s3c_irqwake_eintallow = 0xffffffffL; -int s3c_irq_wake(unsigned int irqno, unsigned int state) +int s3c_irq_wake(struct irq_data *data, unsigned int state) { unsigned long irqbit; - switch (irqno) { + switch (data->irq) { case IRQ_RTC_TIC: case IRQ_RTC_ALARM: - irqbit = 1 << (irqno + 1 - IRQ_RTC_ALARM); + irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM); if (!state) s3c_irqwake_intmask |= irqbit; else diff --git a/arch/arm/plat-s5p/sysmmu.c b/arch/arm/plat-s5p/sysmmu.c new file mode 100644 index 00000000000..d804914dc2e --- /dev/null +++ b/arch/arm/plat-s5p/sysmmu.c @@ -0,0 +1,328 @@ +/* linux/arch/arm/plat-s5p/sysmmu.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/io.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> + +#include <mach/map.h> +#include <mach/regs-sysmmu.h> +#include <mach/sysmmu.h> + +#include <plat/sysmmu.h> + +struct sysmmu_controller s5p_sysmmu_cntlrs[S5P_SYSMMU_TOTAL_IPNUM]; + +void s5p_sysmmu_register(struct sysmmu_controller *sysmmuconp) +{ + unsigned int reg_mmu_ctrl; + unsigned int reg_mmu_status; + unsigned int reg_pt_base_addr; + unsigned int reg_int_status; + unsigned int reg_page_ft_addr; + + reg_int_status = __raw_readl(sysmmuconp->regs + S5P_INT_STATUS); + reg_mmu_ctrl = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL); + reg_mmu_status = __raw_readl(sysmmuconp->regs + S5P_MMU_STATUS); + reg_pt_base_addr = __raw_readl(sysmmuconp->regs + S5P_PT_BASE_ADDR); + reg_page_ft_addr = __raw_readl(sysmmuconp->regs + S5P_PAGE_FAULT_ADDR); + + printk(KERN_INFO "%s: ips:%s\n", __func__, sysmmuconp->name); + printk(KERN_INFO "%s: MMU_CTRL:0x%X, ", __func__, reg_mmu_ctrl); + printk(KERN_INFO "MMU_STATUS:0x%X, PT_BASE_ADDR:0x%X\n", reg_mmu_status, reg_pt_base_addr); + printk(KERN_INFO "%s: INT_STATUS:0x%X, PAGE_FAULT_ADDR:0x%X\n", __func__, reg_int_status, reg_page_ft_addr); + + switch (reg_int_status & 0xFF) { + case 0x1: + printk(KERN_INFO "%s: Page fault\n", __func__); + printk(KERN_INFO "%s: Virtual address causing last page fault or bus error : 0x%x\n", __func__ , reg_page_ft_addr); + break; + case 0x2: + printk(KERN_INFO "%s: AR multi-hit fault\n", __func__); + break; + case 0x4: + printk(KERN_INFO "%s: AW multi-hit fault\n", __func__); + break; + case 0x8: + printk(KERN_INFO "%s: Bus error\n", __func__); + break; + case 0x10: + printk(KERN_INFO "%s: AR Security protection fault\n", __func__); + break; + case 0x20: + printk(KERN_INFO "%s: AR Access protection fault\n", __func__); + break; + case 0x40: + printk(KERN_INFO "%s: AW Security protection fault\n", __func__); + break; + case 0x80: + printk(KERN_INFO "%s: AW Access protection fault\n", __func__); + break; + } +} + +static irqreturn_t s5p_sysmmu_irq(int irq, void *dev_id) +{ + unsigned int i; + unsigned int reg_int_status; + struct sysmmu_controller *sysmmuconp; + + for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) { + sysmmuconp = &s5p_sysmmu_cntlrs[i]; + + if (sysmmuconp->enable == true) { + reg_int_status = __raw_readl(sysmmuconp->regs + S5P_INT_STATUS); + + if (reg_int_status & 0xFF) + s5p_sysmmu_register(sysmmuconp); + } + } + return IRQ_HANDLED; +} + +int s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd) +{ + struct sysmmu_controller *sysmmuconp = NULL; + + sysmmuconp = &s5p_sysmmu_cntlrs[ips]; + + if (sysmmuconp == NULL) { + printk(KERN_ERR "failed to get ip's sysmmu info\n"); + return 1; + } + + /* Set sysmmu page table base address */ + __raw_writel(pgd, sysmmuconp->regs + S5P_PT_BASE_ADDR); + + if (s5p_sysmmu_tlb_invalidate(ips) != 0) + printk(KERN_ERR "failed s5p_sysmmu_tlb_invalidate\n"); + + return 0; +} + +static int s5p_sysmmu_set_tablebase(sysmmu_ips ips) +{ + unsigned int pg; + struct sysmmu_controller *sysmmuconp; + + sysmmuconp = &s5p_sysmmu_cntlrs[ips]; + + if (sysmmuconp == NULL) { + printk(KERN_ERR "failed to get ip's sysmmu info\n"); + return 1; + } + + __asm__("mrc p15, 0, %0, c2, c0, 0" \ + : "=r" (pg) : : "cc"); \ + pg &= ~0x3fff; + + sysmmu_debug("CP15 TTBR0 : 0x%x\n", pg); + + /* Set sysmmu page table base address */ + __raw_writel(pg, sysmmuconp->regs + S5P_PT_BASE_ADDR); + + return 0; +} + +int s5p_sysmmu_enable(sysmmu_ips ips) +{ + unsigned int reg; + + struct sysmmu_controller *sysmmuconp; + + sysmmuconp = &s5p_sysmmu_cntlrs[ips]; + + if (sysmmuconp == NULL) { + printk(KERN_ERR "failed to get ip's sysmmu info\n"); + return 1; + } + + s5p_sysmmu_set_tablebase(ips); + + /* replacement policy : LRU */ + reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CFG); + reg |= 0x1; + __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CFG); + + /* Enable interrupt, Enable MMU */ + reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL); + reg |= (0x1 << 2) | (0x1 << 0); + + __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL); + + sysmmuconp->enable = true; + + return 0; +} + +int s5p_sysmmu_disable(sysmmu_ips ips) +{ + unsigned int reg; + + struct sysmmu_controller *sysmmuconp = NULL; + + if (ips > S5P_SYSMMU_TOTAL_IPNUM) + printk(KERN_ERR "failed to get ips parameter\n"); + + sysmmuconp = &s5p_sysmmu_cntlrs[ips]; + + if (sysmmuconp == NULL) { + printk(KERN_ERR "failed to get ip's sysmmu info\n"); + return 1; + } + + reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CFG); + + /* replacement policy : LRU */ + reg |= 0x1; + __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CFG); + + reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL); + + /* Disable MMU */ + reg &= ~0x1; + __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL); + + sysmmuconp->enable = false; + + return 0; +} + +int s5p_sysmmu_tlb_invalidate(sysmmu_ips ips) +{ + unsigned int reg; + struct sysmmu_controller *sysmmuconp = NULL; + + sysmmuconp = &s5p_sysmmu_cntlrs[ips]; + + if (sysmmuconp == NULL) { + printk(KERN_ERR "failed to get ip's sysmmu info\n"); + return 1; + } + + /* set Block MMU for flush TLB */ + reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL); + reg |= 0x1 << 1; + __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL); + + /* flush all TLB entry */ + __raw_writel(0x1, sysmmuconp->regs + S5P_MMU_FLUSH); + + /* set Un-block MMU after flush TLB */ + reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL); + reg &= ~(0x1 << 1); + __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL); + + return 0; +} + +static int s5p_sysmmu_probe(struct platform_device *pdev) +{ + int i; + int ret; + struct resource *res; + struct sysmmu_controller *sysmmuconp; + sysmmu_ips ips; + + for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) { + sysmmuconp = &s5p_sysmmu_cntlrs[i]; + if (sysmmuconp == NULL) { + printk(KERN_ERR "failed to get ip's sysmmu info\n"); + ret = -ENOENT; + goto err_res; + } + + sysmmuconp->name = sysmmu_ips_name[i]; + + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + if (!res) { + printk(KERN_ERR "failed to get sysmmu resource\n"); + ret = -ENODEV; + goto err_res; + } + + sysmmuconp->mem = request_mem_region(res->start, + ((res->end) - (res->start)) + 1, pdev->name); + if (!sysmmuconp->mem) { + pr_err("failed to request sysmmu memory region\n"); + ret = -EBUSY; + goto err_res; + } + + sysmmuconp->regs = ioremap(res->start, res->end - res->start + 1); + if (!sysmmuconp->regs) { + pr_err("failed to sysmmu ioremap\n"); + ret = -ENXIO; + goto err_reg; + } + + sysmmuconp->irq = platform_get_irq(pdev, i); + if (sysmmuconp->irq <= 0) { + pr_err("failed to get sysmmu irq resource\n"); + ret = -ENOENT; + goto err_map; + } + + ret = request_irq(sysmmuconp->irq, s5p_sysmmu_irq, IRQF_DISABLED, pdev->name, sysmmuconp); + if (ret) { + pr_err("failed to request irq\n"); + ret = -ENOENT; + goto err_map; + } + + ips = (sysmmu_ips)i; + + sysmmuconp->ips = ips; + } + + return 0; + +err_reg: + release_mem_region((resource_size_t)sysmmuconp->mem, (resource_size_t)((res->end) - (res->start) + 1)); +err_map: + iounmap(sysmmuconp->regs); +err_res: + return ret; +} + +static int s5p_sysmmu_remove(struct platform_device *pdev) +{ + return 0; +} +int s5p_sysmmu_runtime_suspend(struct device *dev) +{ + return 0; +} + +int s5p_sysmmu_runtime_resume(struct device *dev) +{ + return 0; +} + +const struct dev_pm_ops s5p_sysmmu_pm_ops = { + .runtime_suspend = s5p_sysmmu_runtime_suspend, + .runtime_resume = s5p_sysmmu_runtime_resume, +}; + +static struct platform_driver s5p_sysmmu_driver = { + .probe = s5p_sysmmu_probe, + .remove = s5p_sysmmu_remove, + .driver = { + .owner = THIS_MODULE, + .name = "s5p-sysmmu", + .pm = &s5p_sysmmu_pm_ops, + } +}; + +static int __init s5p_sysmmu_init(void) +{ + return platform_driver_register(&s5p_sysmmu_driver); +} +arch_initcall(s5p_sysmmu_init); diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index dcd6eff4ee5..32be05cf82a 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -95,6 +95,12 @@ config S3C_GPIO_PULL_UPDOWN help Internal configuration to enable the correct GPIO pull helper +config S3C_GPIO_PULL_S3C2443 + bool + select S3C_GPIO_PULL_UPDOWN + help + Internal configuration to enable the correct GPIO pull helper for S3C2443-style GPIO + config S3C_GPIO_PULL_DOWN bool help @@ -333,4 +339,12 @@ config SAMSUNG_WAKEMASK and above. This code allows a set of interrupt to wakeup-mask mappings. See <plat/wakeup-mask.h> +comment "Power Domain" + +config SAMSUNG_PD + bool "Samsung Power Domain" + depends on PM_RUNTIME + help + Say Y here if you want to control Power Domain by Runtime PM. + endif diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 19d8a16c306..29932f88a8d 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -74,6 +74,10 @@ obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o +# PD support + +obj-$(CONFIG_SAMSUNG_PD) += pd.o + # PWM support obj-$(CONFIG_HAVE_PWM) += pwm.o diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index e8d20b0bc50..772892826ff 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -39,6 +39,9 @@ #include <linux/clk.h> #include <linux/spinlock.h> #include <linux/io.h> +#if defined(CONFIG_DEBUG_FS) +#include <linux/debugfs.h> +#endif #include <mach/hardware.h> #include <asm/irq.h> @@ -447,3 +450,92 @@ int __init s3c24xx_register_baseclocks(unsigned long xtal) return 0; } +#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) +/* debugfs support to trace clock tree hierarchy and attributes */ + +static struct dentry *clk_debugfs_root; + +static int clk_debugfs_register_one(struct clk *c) +{ + int err; + struct dentry *d, *child, *child_tmp; + struct clk *pa = c->parent; + char s[255]; + char *p = s; + + p += sprintf(p, "%s", c->name); + + if (c->id >= 0) + sprintf(p, ":%d", c->id); + + d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); + if (!d) + return -ENOMEM; + + c->dent = d; + + d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage); + if (!d) { + err = -ENOMEM; + goto err_out; + } + + d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate); + if (!d) { + err = -ENOMEM; + goto err_out; + } + return 0; + +err_out: + d = c->dent; + list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child) + debugfs_remove(child); + debugfs_remove(c->dent); + return err; +} + +static int clk_debugfs_register(struct clk *c) +{ + int err; + struct clk *pa = c->parent; + + if (pa && !pa->dent) { + err = clk_debugfs_register(pa); + if (err) + return err; + } + + if (!c->dent) { + err = clk_debugfs_register_one(c); + if (err) + return err; + } + return 0; +} + +static int __init clk_debugfs_init(void) +{ + struct clk *c; + struct dentry *d; + int err; + + d = debugfs_create_dir("clock", NULL); + if (!d) + return -ENOMEM; + clk_debugfs_root = d; + + list_for_each_entry(c, &clocks, list) { + err = clk_debugfs_register(c); + if (err) + goto err_out; + } + return 0; + +err_out: + debugfs_remove_recursive(clk_debugfs_root); + return err; +} +late_initcall(clk_debugfs_init); + +#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ diff --git a/arch/arm/plat-samsung/dev-nand.c b/arch/arm/plat-samsung/dev-nand.c index 3a7b8891ba4..6927ae8fd11 100644 --- a/arch/arm/plat-samsung/dev-nand.c +++ b/arch/arm/plat-samsung/dev-nand.c @@ -126,5 +126,3 @@ void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand) s3c_device_nand.dev.platform_data = npd; } - -EXPORT_SYMBOL_GPL(s3c_nand_set_platdata); diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c index 0aa32f242ee..1c0b0401594 100644 --- a/arch/arm/plat-samsung/gpio-config.c +++ b/arch/arm/plat-samsung/gpio-config.c @@ -278,6 +278,48 @@ s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, pup &= 0x3; return (__force s3c_gpio_pull_t)pup; } + +#ifdef CONFIG_S3C_GPIO_PULL_S3C2443 +int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip, + unsigned int off, s3c_gpio_pull_t pull) +{ + switch (pull) { + case S3C_GPIO_PULL_NONE: + pull = 0x01; + break; + case S3C_GPIO_PULL_UP: + pull = 0x00; + break; + case S3C_GPIO_PULL_DOWN: + pull = 0x02; + break; + } + return s3c_gpio_setpull_updown(chip, off, pull); +} + +s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip, + unsigned int off) +{ + s3c_gpio_pull_t pull; + + pull = s3c_gpio_getpull_updown(chip, off); + + switch (pull) { + case 0x00: + pull = S3C_GPIO_PULL_UP; + break; + case 0x01: + case 0x03: + pull = S3C_GPIO_PULL_NONE; + break; + case 0x02: + pull = S3C_GPIO_PULL_DOWN; + break; + } + + return pull; +} +#endif #endif #if defined(CONFIG_S3C_GPIO_PULL_UP) || defined(CONFIG_S3C_GPIO_PULL_DOWN) diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c index c354089254f..ea37c046178 100644 --- a/arch/arm/plat-samsung/gpiolib.c +++ b/arch/arm/plat-samsung/gpiolib.c @@ -197,3 +197,10 @@ void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, s3c_gpiolib_add(chip); } } + +void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip, + int nr_chips) +{ + for (; nr_chips > 0; nr_chips--, chip++) + s3c_gpiolib_add(chip); +} diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index 0fbcd0effd8..9a82b887491 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -47,6 +47,9 @@ struct clk { struct clk_ops *ops; int (*enable)(struct clk *, int enable); +#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) + struct dentry *dent; /* For visible tree hierarchy */ +#endif }; /* other clocks which may be registered by board support */ diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index e9e3b6e3ec7..b4d208b4295 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -104,6 +104,7 @@ extern struct platform_device s5pv310_device_i2s0; extern struct platform_device s5pv310_device_i2s1; extern struct platform_device s5pv310_device_i2s2; extern struct platform_device s5pv310_device_spdif; +extern struct platform_device s5pv310_device_pd[]; extern struct platform_device s5p6442_device_pcm0; extern struct platform_device s5p6442_device_pcm1; @@ -115,6 +116,8 @@ extern struct platform_device s5p6440_device_pcm; extern struct platform_device s5p6440_device_iis; extern struct platform_device s5p6450_device_iis0; +extern struct platform_device s5p6450_device_iis1; +extern struct platform_device s5p6450_device_iis2; extern struct platform_device s5p6450_device_pcm0; extern struct platform_device s5pc100_device_ac97; @@ -131,6 +134,11 @@ extern struct platform_device s5p_device_fimc0; extern struct platform_device s5p_device_fimc1; extern struct platform_device s5p_device_fimc2; +extern struct platform_device s5p_device_mipi_csis0; +extern struct platform_device s5p_device_mipi_csis1; + +extern struct platform_device s5pv310_device_sysmmu; + /* s3c2440 specific devices */ #ifdef CONFIG_CPU_S3C2440 diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h index 0d2c5703f1e..5603db0b79b 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h @@ -244,7 +244,7 @@ extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip, * This helper function reads the state of the pull-{up,down} resistor for the * given GPIO in the same case as s3c_gpio_setpull_upown. */ -extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip, +extern s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip, unsigned int off); #endif /* __PLAT_GPIO_CFG_HELPERS_H */ diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index 13a22b8861e..dac35d0a711 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -118,6 +118,8 @@ extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, int nr_chips); extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, int nr_chips); +extern void samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip, + int nr_chips); extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip); extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h new file mode 100644 index 00000000000..5f0ad85783d --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/pd.h @@ -0,0 +1,30 @@ +/* linux/arch/arm/plat-samsung/include/plat/pd.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_SAMSUNG_PD_H +#define __ASM_PLAT_SAMSUNG_PD_H __FILE__ + +struct samsung_pd_info { + int (*enable)(struct device *dev); + int (*disable)(struct device *dev); + void __iomem *base; +}; + +enum s5pv310_pd_block { + PD_MFC, + PD_G3D, + PD_LCD0, + PD_LCD1, + PD_TV, + PD_CAM, + PD_GPS +}; + +#endif /* __ASM_PLAT_SAMSUNG_PD_H */ diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index 245836d9193..d9025e37767 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -15,6 +15,8 @@ * management */ +#include <linux/irq.h> + #ifdef CONFIG_PM extern __init int s3c_pm_init(void); @@ -100,7 +102,7 @@ extern void s3c_pm_do_restore(struct sleep_save *ptr, int count); extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count); #ifdef CONFIG_PM -extern int s3c_irqext_wake(unsigned int irqno, unsigned int state); +extern int s3c_irqext_wake(struct irq_data *data, unsigned int state); extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state); extern int s3c24xx_irq_resume(struct sys_device *dev); #else diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 85853f8c4c5..5a41a0b69ee 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -107,6 +107,8 @@ extern struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata; /* Helper function availablity */ +extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w); +extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w); extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w); extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w); extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w); @@ -122,6 +124,39 @@ extern void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *, int w); extern void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *, int w); extern void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *, int w); +/* S3C2416 SDHCI setup */ + +#ifdef CONFIG_S3C2416_SETUP_SDHCI +extern char *s3c2416_hsmmc_clksrcs[4]; + +extern void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); + +static inline void s3c2416_default_sdhci0(void) +{ +#ifdef CONFIG_S3C_DEV_HSMMC + s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs; + s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card; +#endif /* CONFIG_S3C_DEV_HSMMC */ +} + +static inline void s3c2416_default_sdhci1(void) +{ +#ifdef CONFIG_S3C_DEV_HSMMC1 + s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs; + s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card; +#endif /* CONFIG_S3C_DEV_HSMMC1 */ +} + +#else +static inline void s3c2416_default_sdhci0(void) { } +static inline void s3c2416_default_sdhci1(void) { } + +#endif /* CONFIG_S3C2416_SETUP_SDHCI */ /* S3C64XX SDHCI setup */ #ifdef CONFIG_S3C64XX_SETUP_SDHCI diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c index 4f8c102674a..4e770355ccb 100644 --- a/arch/arm/plat-samsung/irq-uart.c +++ b/arch/arm/plat-samsung/irq-uart.c @@ -28,9 +28,9 @@ * are consecutive when looking up the interrupt in the demux routines. */ -static inline void __iomem *s3c_irq_uart_base(unsigned int irq) +static inline void __iomem *s3c_irq_uart_base(struct irq_data *data) { - struct s3c_uart_irq *uirq = get_irq_chip_data(irq); + struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data); return uirq->regs; } @@ -39,10 +39,10 @@ static inline unsigned int s3c_irq_uart_bit(unsigned int irq) return irq & 3; } -static void s3c_irq_uart_mask(unsigned int irq) +static void s3c_irq_uart_mask(struct irq_data *data) { - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); + void __iomem *regs = s3c_irq_uart_base(data); + unsigned int bit = s3c_irq_uart_bit(data->irq); u32 reg; reg = __raw_readl(regs + S3C64XX_UINTM); @@ -50,10 +50,10 @@ static void s3c_irq_uart_mask(unsigned int irq) __raw_writel(reg, regs + S3C64XX_UINTM); } -static void s3c_irq_uart_maskack(unsigned int irq) +static void s3c_irq_uart_maskack(struct irq_data *data) { - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); + void __iomem *regs = s3c_irq_uart_base(data); + unsigned int bit = s3c_irq_uart_bit(data->irq); u32 reg; reg = __raw_readl(regs + S3C64XX_UINTM); @@ -62,10 +62,10 @@ static void s3c_irq_uart_maskack(unsigned int irq) __raw_writel(1 << bit, regs + S3C64XX_UINTP); } -static void s3c_irq_uart_unmask(unsigned int irq) +static void s3c_irq_uart_unmask(struct irq_data *data) { - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); + void __iomem *regs = s3c_irq_uart_base(data); + unsigned int bit = s3c_irq_uart_bit(data->irq); u32 reg; reg = __raw_readl(regs + S3C64XX_UINTM); @@ -73,17 +73,17 @@ static void s3c_irq_uart_unmask(unsigned int irq) __raw_writel(reg, regs + S3C64XX_UINTM); } -static void s3c_irq_uart_ack(unsigned int irq) +static void s3c_irq_uart_ack(struct irq_data *data) { - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); + void __iomem *regs = s3c_irq_uart_base(data); + unsigned int bit = s3c_irq_uart_bit(data->irq); __raw_writel(1 << bit, regs + S3C64XX_UINTP); } static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) { - struct s3c_uart_irq *uirq = desc->handler_data; + struct s3c_uart_irq *uirq = desc->irq_data.handler_data; u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); int base = uirq->base_irq; @@ -99,10 +99,10 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) static struct irq_chip s3c_irq_uart = { .name = "s3c-uart", - .mask = s3c_irq_uart_mask, - .unmask = s3c_irq_uart_unmask, - .mask_ack = s3c_irq_uart_maskack, - .ack = s3c_irq_uart_ack, + .irq_mask = s3c_irq_uart_mask, + .irq_unmask = s3c_irq_uart_unmask, + .irq_mask_ack = s3c_irq_uart_maskack, + .irq_ack = s3c_irq_uart_ack, }; static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) @@ -124,7 +124,7 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) set_irq_flags(irq, IRQF_VALID); } - desc->handler_data = uirq; + desc->irq_data.handler_data = uirq; set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); } diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c index 0270519fcab..dd8692ae5c4 100644 --- a/arch/arm/plat-samsung/irq-vic-timer.c +++ b/arch/arm/plat-samsung/irq-vic-timer.c @@ -24,43 +24,46 @@ static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) { - generic_handle_irq((int)desc->handler_data); + generic_handle_irq((int)desc->irq_data.handler_data); } /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ -static void s3c_irq_timer_mask(unsigned int irq) +static void s3c_irq_timer_mask(struct irq_data *data) { u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); + u32 mask = (u32)data->chip_data; reg &= 0x1f; /* mask out pending interrupts */ - reg &= ~(1 << (irq - IRQ_TIMER0)); + reg &= ~mask; __raw_writel(reg, S3C64XX_TINT_CSTAT); } -static void s3c_irq_timer_unmask(unsigned int irq) +static void s3c_irq_timer_unmask(struct irq_data *data) { u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); + u32 mask = (u32)data->chip_data; reg &= 0x1f; /* mask out pending interrupts */ - reg |= 1 << (irq - IRQ_TIMER0); + reg |= mask; __raw_writel(reg, S3C64XX_TINT_CSTAT); } -static void s3c_irq_timer_ack(unsigned int irq) +static void s3c_irq_timer_ack(struct irq_data *data) { u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); + u32 mask = (u32)data->chip_data; reg &= 0x1f; - reg |= (1 << 5) << (irq - IRQ_TIMER0); + reg |= mask << 5; __raw_writel(reg, S3C64XX_TINT_CSTAT); } static struct irq_chip s3c_irq_timer = { .name = "s3c-timer", - .mask = s3c_irq_timer_mask, - .unmask = s3c_irq_timer_unmask, - .ack = s3c_irq_timer_ack, + .irq_mask = s3c_irq_timer_mask, + .irq_unmask = s3c_irq_timer_unmask, + .irq_ack = s3c_irq_timer_ack, }; /** @@ -79,8 +82,9 @@ void __init s3c_init_vic_timer_irq(unsigned int parent_irq, set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer); set_irq_chip(timer_irq, &s3c_irq_timer); + set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0))); set_irq_handler(timer_irq, handle_level_irq); set_irq_flags(timer_irq, IRQF_VALID); - desc->handler_data = (void *)timer_irq; + desc->irq_data.handler_data = (void *)timer_irq; } diff --git a/arch/arm/plat-samsung/pd.c b/arch/arm/plat-samsung/pd.c new file mode 100644 index 00000000000..efe1d564473 --- /dev/null +++ b/arch/arm/plat-samsung/pd.c @@ -0,0 +1,95 @@ +/* linux/arch/arm/plat-samsung/pd.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung Power domain support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/err.h> +#include <linux/pm_runtime.h> + +#include <plat/pd.h> + +static int samsung_pd_probe(struct platform_device *pdev) +{ + struct samsung_pd_info *pdata = pdev->dev.platform_data; + struct device *dev = &pdev->dev; + + if (!pdata) { + dev_err(dev, "no device data specified\n"); + return -ENOENT; + } + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + dev_info(dev, "power domain registered\n"); + return 0; +} + +static int __devexit samsung_pd_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + pm_runtime_disable(dev); + return 0; +} + +static int samsung_pd_runtime_suspend(struct device *dev) +{ + struct samsung_pd_info *pdata = dev->platform_data; + int ret = 0; + + if (pdata->disable) + ret = pdata->disable(dev); + + dev_dbg(dev, "suspended\n"); + return ret; +} + +static int samsung_pd_runtime_resume(struct device *dev) +{ + struct samsung_pd_info *pdata = dev->platform_data; + int ret = 0; + + if (pdata->enable) + ret = pdata->enable(dev); + + dev_dbg(dev, "resumed\n"); + return ret; +} + +static const struct dev_pm_ops samsung_pd_pm_ops = { + .runtime_suspend = samsung_pd_runtime_suspend, + .runtime_resume = samsung_pd_runtime_resume, +}; + +static struct platform_driver samsung_pd_driver = { + .driver = { + .name = "samsung-pd", + .owner = THIS_MODULE, + .pm = &samsung_pd_pm_ops, + }, + .probe = samsung_pd_probe, + .remove = __devexit_p(samsung_pd_remove), +}; + +static int __init samsung_pd_init(void) +{ + int ret; + + ret = platform_driver_register(&samsung_pd_driver); + if (ret) + printk(KERN_ERR "%s: failed to add PD driver\n", __func__); + + return ret; +} +arch_initcall(samsung_pd_init); diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 5bf3f2f09e7..02d531fb3f8 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -136,15 +136,15 @@ static void s3c_pm_restore_uarts(void) { } unsigned long s3c_irqwake_intmask = 0xffffffffL; unsigned long s3c_irqwake_eintmask = 0xffffffffL; -int s3c_irqext_wake(unsigned int irqno, unsigned int state) +int s3c_irqext_wake(struct irq_data *data, unsigned int state) { - unsigned long bit = 1L << IRQ_EINT_BIT(irqno); + unsigned long bit = 1L << IRQ_EINT_BIT(data->irq); if (!(s3c_irqwake_eintallow & bit)) return -ENOENT; printk(KERN_INFO "wake %s for irq %d\n", - state ? "enabled" : "disabled", irqno); + state ? "enabled" : "disabled", data->irq); if (!state) s3c_irqwake_eintmask |= bit; diff --git a/arch/arm/plat-spear/shirq.c b/arch/arm/plat-spear/shirq.c index 2172d6946ae..78189035e7f 100644 --- a/arch/arm/plat-spear/shirq.c +++ b/arch/arm/plat-spear/shirq.c @@ -20,10 +20,10 @@ struct spear_shirq *shirq; static DEFINE_SPINLOCK(lock); -static void shirq_irq_mask(unsigned irq) +static void shirq_irq_mask(struct irq_data *d) { - struct spear_shirq *shirq = get_irq_chip_data(irq); - u32 val, id = irq - shirq->dev_config[0].virq; + struct spear_shirq *shirq = irq_data_get_irq_chip_data(d); + u32 val, id = d->irq - shirq->dev_config[0].virq; unsigned long flags; if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1) @@ -39,10 +39,10 @@ static void shirq_irq_mask(unsigned irq) spin_unlock_irqrestore(&lock, flags); } -static void shirq_irq_unmask(unsigned irq) +static void shirq_irq_unmask(struct irq_data *d) { - struct spear_shirq *shirq = get_irq_chip_data(irq); - u32 val, id = irq - shirq->dev_config[0].virq; + struct spear_shirq *shirq = irq_data_get_irq_chip_data(d); + u32 val, id = d->irq - shirq->dev_config[0].virq; unsigned long flags; if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1) @@ -60,9 +60,9 @@ static void shirq_irq_unmask(unsigned irq) static struct irq_chip shirq_chip = { .name = "spear_shirq", - .ack = shirq_irq_mask, - .mask = shirq_irq_mask, - .unmask = shirq_irq_unmask, + .irq_ack = shirq_irq_mask, + .irq_mask = shirq_irq_mask, + .irq_unmask = shirq_irq_unmask, }; static void shirq_handler(unsigned irq, struct irq_desc *desc) @@ -70,7 +70,7 @@ static void shirq_handler(unsigned irq, struct irq_desc *desc) u32 i, val, mask; struct spear_shirq *shirq = get_irq_data(irq); - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); while ((val = readl(shirq->regs.base + shirq->regs.status_reg) & shirq->regs.status_reg_mask)) { for (i = 0; (i < shirq->dev_count) && val; i++) { @@ -92,7 +92,7 @@ static void shirq_handler(unsigned irq, struct irq_desc *desc) writel(mask, shirq->regs.base + shirq->regs.clear_reg); } } - desc->chip->unmask(irq); + desc->irq_data.chip->irq_unmask(&desc->irq_data); } int spear_shirq_register(struct spear_shirq *shirq) diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c index 20de4e0401e..aaa168683d4 100644 --- a/arch/arm/plat-stmp3xxx/irq.c +++ b/arch/arm/plat-stmp3xxx/irq.c @@ -34,7 +34,7 @@ void __init stmp3xxx_init_irq(struct irq_chip *chip) /* Disable all interrupts initially */ for (i = 0; i < NR_REAL_IRQS; i++) { - chip->mask(i); + chip->irq_mask(irq_get_irq_data(i)); set_irq_chip(i, chip); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c index 6d6b1a468ed..66d5bac3ace 100644 --- a/arch/arm/plat-stmp3xxx/pinmux.c +++ b/arch/arm/plat-stmp3xxx/pinmux.c @@ -351,27 +351,27 @@ void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label) } EXPORT_SYMBOL(stmp3xxx_release_pin_group); -static int stmp3xxx_irq_to_gpio(int irq, +static int stmp3xxx_irq_data_to_gpio(struct irq_data *d, struct stmp3xxx_pinmux_bank **bank, unsigned *gpio) { struct stmp3xxx_pinmux_bank *pm; for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++) - if (pm->virq <= irq && irq < pm->virq + 32) { + if (pm->virq <= d->irq && d->irq < pm->virq + 32) { *bank = pm; - *gpio = irq - pm->virq; + *gpio = d->irq - pm->virq; return 0; } return -ENOENT; } -static int stmp3xxx_set_irqtype(unsigned irq, unsigned type) +static int stmp3xxx_set_irqtype(struct irq_data *d, unsigned type) { struct stmp3xxx_pinmux_bank *pm; unsigned gpio; int l, p; - stmp3xxx_irq_to_gpio(irq, &pm, &gpio); + stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); switch (type) { case IRQ_TYPE_EDGE_RISING: l = 0; p = 1; break; @@ -398,33 +398,33 @@ static int stmp3xxx_set_irqtype(unsigned irq, unsigned type) return 0; } -static void stmp3xxx_pin_ack_irq(unsigned irq) +static void stmp3xxx_pin_ack_irq(struct irq_data *d) { u32 stat; struct stmp3xxx_pinmux_bank *pm; unsigned gpio; - stmp3xxx_irq_to_gpio(irq, &pm, &gpio); + stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); stat = __raw_readl(pm->irqstat) & (1 << gpio); stmp3xxx_clearl(stat, pm->irqstat); } -static void stmp3xxx_pin_mask_irq(unsigned irq) +static void stmp3xxx_pin_mask_irq(struct irq_data *d) { struct stmp3xxx_pinmux_bank *pm; unsigned gpio; - stmp3xxx_irq_to_gpio(irq, &pm, &gpio); + stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); stmp3xxx_clearl(1 << gpio, pm->irqen); stmp3xxx_clearl(1 << gpio, pm->pin2irq); } -static void stmp3xxx_pin_unmask_irq(unsigned irq) +static void stmp3xxx_pin_unmask_irq(struct irq_data *d) { struct stmp3xxx_pinmux_bank *pm; unsigned gpio; - stmp3xxx_irq_to_gpio(irq, &pm, &gpio); + stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); stmp3xxx_setl(1 << gpio, pm->irqen); stmp3xxx_setl(1 << gpio, pm->pin2irq); } @@ -503,10 +503,10 @@ static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc) } static struct irq_chip gpio_irq_chip = { - .ack = stmp3xxx_pin_ack_irq, - .mask = stmp3xxx_pin_mask_irq, - .unmask = stmp3xxx_pin_unmask_irq, - .set_type = stmp3xxx_set_irqtype, + .irq_ack = stmp3xxx_pin_ack_irq, + .irq_mask = stmp3xxx_pin_mask_irq, + .irq_unmask = stmp3xxx_pin_unmask_irq, + .irq_set_type = stmp3xxx_set_irqtype, }; int __init stmp3xxx_pinmux_init(int virtual_irq_start) @@ -533,7 +533,7 @@ int __init stmp3xxx_pinmux_init(int virtual_irq_start) pm->virq = virtual_irq_start + b * 32; for (virq = pm->virq; virq < pm->virq; virq++) { - gpio_irq_chip.mask(virq); + gpio_irq_chip.irq_mask(irq_get_irq_data(virq)); set_irq_chip(virq, &gpio_irq_chip); set_irq_handler(virq, handle_level_irq); set_irq_flags(virq, IRQF_VALID); diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index 313b13073c5..cd2062fe0f6 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig @@ -1,8 +1,8 @@ config AVR32 def_bool y - # With EMBEDDED=n, we get lots of stuff automatically selected + # With EXPERT=n, we get lots of stuff automatically selected # that we usually don't need on AVR32. - select EMBEDDED + select EXPERT select HAVE_CLK select HAVE_OPROFILE select HAVE_KPROBES diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 0a221d48152..c09577ddc3c 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -30,6 +30,9 @@ config BLACKFIN select HAVE_KERNEL_LZO if RAMKERNEL select HAVE_OPROFILE select ARCH_WANT_OPTIONAL_GPIOLIB + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE + select IRQ_PER_CPU if SMP config GENERIC_CSUM def_bool y @@ -44,15 +47,6 @@ config ZONE_DMA config GENERIC_FIND_NEXT_BIT def_bool y -config GENERIC_HARDIRQS - def_bool y - -config GENERIC_IRQ_PROBE - def_bool y - -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config GENERIC_GPIO def_bool y @@ -254,11 +248,6 @@ config HOTPLUG_CPU depends on SMP && HOTPLUG default y -config IRQ_PER_CPU - bool - depends on SMP - default y - config HAVE_LEGACY_PER_CPU_AREA def_bool y depends on SMP diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig index c0b988ee30d..db8d38a12a9 100644 --- a/arch/blackfin/configs/BF518F-EZBRD_defconfig +++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig index 864af5b6887..3e50d7857c2 100644 --- a/arch/blackfin/configs/BF526-EZBRD_defconfig +++ b/arch/blackfin/configs/BF526-EZBRD_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig index 7b6a3370dbe..362f59dd522 100644 --- a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig +++ b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_ELF_CORE is not set # CONFIG_AIO is not set CONFIG_SLAB=y diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig index 4faa6b46a35..023ff0df269 100644 --- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig index 9d893eb6824..4e5a121b3c5 100644 --- a/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/BF527-TLL6527M_defconfig b/arch/blackfin/configs/BF527-TLL6527M_defconfig index 97a2767c80f..cd0636bb24a 100644 --- a/arch/blackfin/configs/BF527-TLL6527M_defconfig +++ b/arch/blackfin/configs/BF527-TLL6527M_defconfig @@ -6,7 +6,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig index f84774360c5..9f8fc84e4ac 100644 --- a/arch/blackfin/configs/BF533-EZKIT_defconfig +++ b/arch/blackfin/configs/BF533-EZKIT_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig index 0e7262c04cc..ccc432b722a 100644 --- a/arch/blackfin/configs/BF533-STAMP_defconfig +++ b/arch/blackfin/configs/BF533-STAMP_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig index 4d14a002e7b..566695472a8 100644 --- a/arch/blackfin/configs/BF537-STAMP_defconfig +++ b/arch/blackfin/configs/BF537-STAMP_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig index fbee9d776f5..ac22124ccb6 100644 --- a/arch/blackfin/configs/BF538-EZKIT_defconfig +++ b/arch/blackfin/configs/BF538-EZKIT_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig index 05dd11db2f7..944404b6ff0 100644 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/BF561-ACVILON_defconfig b/arch/blackfin/configs/BF561-ACVILON_defconfig index bcb14d1c566..b7c8451f26a 100644 --- a/arch/blackfin/configs/BF561-ACVILON_defconfig +++ b/arch/blackfin/configs/BF561-ACVILON_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig index 4cf451024fd..7e67ba31e99 100644 --- a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig index 843aaa54a9e..141e5933e1a 100644 --- a/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig index dae7adf3b2a..97ebe09a737 100644 --- a/arch/blackfin/configs/BlackStamp_defconfig +++ b/arch/blackfin/configs/BlackStamp_defconfig @@ -6,7 +6,7 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig index f3414244bfe..c2457543e58 100644 --- a/arch/blackfin/configs/CM-BF527_defconfig +++ b/arch/blackfin/configs/CM-BF527_defconfig @@ -8,7 +8,7 @@ CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_GZIP is not set CONFIG_RD_LZMA=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig index 8c7e08f173d..baf1c1573e5 100644 --- a/arch/blackfin/configs/CM-BF533_defconfig +++ b/arch/blackfin/configs/CM-BF533_defconfig @@ -7,7 +7,7 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_GZIP is not set CONFIG_RD_LZMA=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig index bd3cb766d07..707cbf8a259 100644 --- a/arch/blackfin/configs/CM-BF537E_defconfig +++ b/arch/blackfin/configs/CM-BF537E_defconfig @@ -8,7 +8,7 @@ CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_GZIP is not set CONFIG_RD_LZMA=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig index 82224f37c04..4596935eada 100644 --- a/arch/blackfin/configs/CM-BF537U_defconfig +++ b/arch/blackfin/configs/CM-BF537U_defconfig @@ -8,7 +8,7 @@ CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_GZIP is not set CONFIG_RD_LZMA=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig index 433598c6e77..df267588efe 100644 --- a/arch/blackfin/configs/CM-BF548_defconfig +++ b/arch/blackfin/configs/CM-BF548_defconfig @@ -8,7 +8,7 @@ CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_GZIP is not set CONFIG_RD_LZMA=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig index ded7d845cb3..6c7b21585a4 100644 --- a/arch/blackfin/configs/CM-BF561_defconfig +++ b/arch/blackfin/configs/CM-BF561_defconfig @@ -8,7 +8,7 @@ CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_GZIP is not set CONFIG_RD_LZMA=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig index 0ebc7d9aa42..f50313657f3 100644 --- a/arch/blackfin/configs/DNP5370_defconfig +++ b/arch/blackfin/configs/DNP5370_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLOB=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_CFQ is not set diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig index 700fb701c12..7450127b645 100644 --- a/arch/blackfin/configs/H8606_defconfig +++ b/arch/blackfin/configs/H8606_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig index b40156d217e..5e797cf7204 100644 --- a/arch/blackfin/configs/IP0X_defconfig +++ b/arch/blackfin/configs/IP0X_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_HOTPLUG is not set # CONFIG_ELF_CORE is not set diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig index be866d95ed7..a566a2fe6b9 100644 --- a/arch/blackfin/configs/PNAV-10_defconfig +++ b/arch/blackfin/configs/PNAV-10_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig index b64bdf759b8..853809510ee 100644 --- a/arch/blackfin/configs/SRV1_defconfig +++ b/arch/blackfin/configs/SRV1_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS_ALL=y # CONFIG_ELF_CORE is not set diff --git a/arch/blackfin/configs/TCM-BF518_defconfig b/arch/blackfin/configs/TCM-BF518_defconfig index 1bccd9a5098..d496ae9a39b 100644 --- a/arch/blackfin/configs/TCM-BF518_defconfig +++ b/arch/blackfin/configs/TCM-BF518_defconfig @@ -7,7 +7,7 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_GZIP is not set CONFIG_RD_LZMA=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig index 00ce899e9e5..65f642167a5 100644 --- a/arch/blackfin/configs/TCM-BF537_defconfig +++ b/arch/blackfin/configs/TCM-BF537_defconfig @@ -8,7 +8,7 @@ CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_GZIP is not set CONFIG_RD_LZMA=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig index 613e62831c5..0a7a4c11d8b 100644 --- a/arch/cris/Kconfig +++ b/arch/cris/Kconfig @@ -54,6 +54,8 @@ config CRIS bool default y select HAVE_IDE + select HAVE_GENERIC_HARDIRQS + select GENERIC_HARDIRQS_NO_DEPRECATED config HZ int @@ -67,10 +69,6 @@ menu "General setup" source "fs/Kconfig.binfmt" -config GENERIC_HARDIRQS - bool - default y - config ETRAX_CMDLINE string "Kernel command line" default "root=/dev/mtdblock3" diff --git a/arch/cris/arch-v10/kernel/irq.c b/arch/cris/arch-v10/kernel/irq.c index a0c0df8be9c..7328a7cf744 100644 --- a/arch/cris/arch-v10/kernel/irq.c +++ b/arch/cris/arch-v10/kernel/irq.c @@ -104,43 +104,21 @@ static void (*interrupt[NR_IRQS])(void) = { IRQ31_interrupt }; -static void enable_crisv10_irq(unsigned int irq); - -static unsigned int startup_crisv10_irq(unsigned int irq) -{ - enable_crisv10_irq(irq); - return 0; -} - -#define shutdown_crisv10_irq disable_crisv10_irq - -static void enable_crisv10_irq(unsigned int irq) -{ - crisv10_unmask_irq(irq); -} - -static void disable_crisv10_irq(unsigned int irq) -{ - crisv10_mask_irq(irq); -} - -static void ack_crisv10_irq(unsigned int irq) +static void enable_crisv10_irq(struct irq_data *data) { + crisv10_unmask_irq(data->irq); } -static void end_crisv10_irq(unsigned int irq) +static void disable_crisv10_irq(struct irq_data *data) { + crisv10_mask_irq(data->irq); } static struct irq_chip crisv10_irq_type = { - .name = "CRISv10", - .startup = startup_crisv10_irq, - .shutdown = shutdown_crisv10_irq, - .enable = enable_crisv10_irq, - .disable = disable_crisv10_irq, - .ack = ack_crisv10_irq, - .end = end_crisv10_irq, - .set_affinity = NULL + .name = "CRISv10", + .irq_shutdown = disable_crisv10_irq, + .irq_enable = enable_crisv10_irq, + .irq_disable = disable_crisv10_irq, }; void weird_irq(void); @@ -221,7 +199,8 @@ init_IRQ(void) /* Initialize IRQ handler descriptors. */ for(i = 2; i < NR_IRQS; i++) { - irq_desc[i].chip = &crisv10_irq_type; + set_irq_desc_and_handler(i, &crisv10_irq_type, + handle_simple_irq); set_int_vector(i, interrupt[i]); } diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c index 2ed48ae3d31..0ad9db5126c 100644 --- a/arch/cris/arch-v32/kernel/irq.c +++ b/arch/cris/arch-v32/kernel/irq.c @@ -291,54 +291,33 @@ void crisv32_unmask_irq(int irq) } -static unsigned int startup_crisv32_irq(unsigned int irq) +static void enable_crisv32_irq(struct irq_data *data) { - crisv32_unmask_irq(irq); - return 0; -} - -static void shutdown_crisv32_irq(unsigned int irq) -{ - crisv32_mask_irq(irq); + crisv32_unmask_irq(data->irq); } -static void enable_crisv32_irq(unsigned int irq) +static void disable_crisv32_irq(struct irq_data *data) { - crisv32_unmask_irq(irq); + crisv32_mask_irq(data->irq); } -static void disable_crisv32_irq(unsigned int irq) -{ - crisv32_mask_irq(irq); -} - -static void ack_crisv32_irq(unsigned int irq) -{ -} - -static void end_crisv32_irq(unsigned int irq) -{ -} - -int set_affinity_crisv32_irq(unsigned int irq, const struct cpumask *dest) +static int set_affinity_crisv32_irq(struct irq_data *data, + const struct cpumask *dest, bool force) { unsigned long flags; + spin_lock_irqsave(&irq_lock, flags); - irq_allocations[irq - FIRST_IRQ].mask = *dest; + irq_allocations[data->irq - FIRST_IRQ].mask = *dest; spin_unlock_irqrestore(&irq_lock, flags); - return 0; } static struct irq_chip crisv32_irq_type = { - .name = "CRISv32", - .startup = startup_crisv32_irq, - .shutdown = shutdown_crisv32_irq, - .enable = enable_crisv32_irq, - .disable = disable_crisv32_irq, - .ack = ack_crisv32_irq, - .end = end_crisv32_irq, - .set_affinity = set_affinity_crisv32_irq + .name = "CRISv32", + .irq_shutdown = disable_crisv32_irq, + .irq_enable = enable_crisv32_irq, + .irq_disable = disable_crisv32_irq, + .irq_set_affinity = set_affinity_crisv32_irq, }; void @@ -472,7 +451,8 @@ init_IRQ(void) /* Point all IRQ's to bad handlers. */ for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) { - irq_desc[j].chip = &crisv32_irq_type; + set_irq_chip_and_handler(j, &crisv32_irq_type, + handle_simple_irq); set_exception_vector(i, interrupt[j]); } diff --git a/arch/cris/configs/artpec_3_defconfig b/arch/cris/configs/artpec_3_defconfig index 590f72c9455..71854d41c5a 100644 --- a/arch/cris/configs/artpec_3_defconfig +++ b/arch/cris/configs/artpec_3_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/cris/configs/etrax-100lx_v2_defconfig b/arch/cris/configs/etrax-100lx_v2_defconfig index 1b2853e3980..a85aabf92be 100644 --- a/arch/cris/configs/etrax-100lx_v2_defconfig +++ b/arch/cris/configs/etrax-100lx_v2_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/cris/configs/etraxfs_defconfig b/arch/cris/configs/etraxfs_defconfig index f73d38cc9c6..87c7227fecb 100644 --- a/arch/cris/configs/etraxfs_defconfig +++ b/arch/cris/configs/etraxfs_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/cris/kernel/irq.c b/arch/cris/kernel/irq.c index 469f7f9d62e..c346952f06d 100644 --- a/arch/cris/kernel/irq.c +++ b/arch/cris/kernel/irq.c @@ -62,7 +62,7 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->name); + seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) @@ -93,8 +93,8 @@ asmlinkage void do_IRQ(int irq, struct pt_regs * regs) printk("do_IRQ: stack overflow: %lX\n", sp); show_stack(NULL, (unsigned long *)sp); } - __do_IRQ(irq); - irq_exit(); + generic_handle_irq(irq); + irq_exit(); set_irq_regs(old_regs); } diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig index f6bcb039cd6..747499a1b31 100644 --- a/arch/frv/Kconfig +++ b/arch/frv/Kconfig @@ -5,6 +5,7 @@ config FRV select HAVE_ARCH_TRACEHOOK select HAVE_IRQ_WORK select HAVE_PERF_EVENTS + select HAVE_GENERIC_HARDIRQS config ZONE_DMA bool @@ -29,14 +30,6 @@ config GENERIC_CALIBRATE_DELAY bool default n -config GENERIC_HARDIRQS - bool - default y - -config GENERIC_HARDIRQS_NO__DO_IRQ - bool - default y - config TIME_LOW_RES bool default y diff --git a/arch/frv/defconfig b/arch/frv/defconfig index b8ebe9e8a49..b1b792610fd 100644 --- a/arch/frv/defconfig +++ b/arch/frv/defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_HOTPLUG is not set CONFIG_MMU=y CONFIG_FRV_OUTOFLINE_ATOMIC_OPS=y diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig index 65f897d8c1e..6df692d1475 100644 --- a/arch/h8300/Kconfig +++ b/arch/h8300/Kconfig @@ -2,6 +2,8 @@ config H8300 bool default y select HAVE_IDE + select HAVE_GENERIC_HARDIRQS + select GENERIC_HARDIRQS_NO_DEPRECATED config SYMBOL_PREFIX string @@ -47,10 +49,6 @@ config GENERIC_HWEIGHT bool default y -config GENERIC_HARDIRQS - bool - default y - config GENERIC_CALIBRATE_DELAY bool default y diff --git a/arch/h8300/defconfig b/arch/h8300/defconfig index 342f77765f0..042425a0264 100644 --- a/arch/h8300/defconfig +++ b/arch/h8300/defconfig @@ -1,7 +1,7 @@ CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_KALLSYMS is not set diff --git a/arch/h8300/kernel/irq.c b/arch/h8300/kernel/irq.c index c25dc2c2b1d..7643d39925d 100644 --- a/arch/h8300/kernel/irq.c +++ b/arch/h8300/kernel/irq.c @@ -38,34 +38,30 @@ static inline int is_ext_irq(unsigned int irq) return (irq >= EXT_IRQ0 && irq <= (EXT_IRQ0 + EXT_IRQS)); } -static void h8300_enable_irq(unsigned int irq) +static void h8300_enable_irq(struct irq_data *data) { - if (is_ext_irq(irq)) - IER_REGS |= 1 << (irq - EXT_IRQ0); + if (is_ext_irq(data->irq)) + IER_REGS |= 1 << (data->irq - EXT_IRQ0); } -static void h8300_disable_irq(unsigned int irq) +static void h8300_disable_irq(struct irq_data *data) { - if (is_ext_irq(irq)) - IER_REGS &= ~(1 << (irq - EXT_IRQ0)); + if (is_ext_irq(data->irq)) + IER_REGS &= ~(1 << (data->irq - EXT_IRQ0)); } -static void h8300_end_irq(unsigned int irq) +static unsigned int h8300_startup_irq(struct irq_data *data) { -} - -static unsigned int h8300_startup_irq(unsigned int irq) -{ - if (is_ext_irq(irq)) - return h8300_enable_irq_pin(irq); + if (is_ext_irq(data->irq)) + return h8300_enable_irq_pin(data->irq); else return 0; } -static void h8300_shutdown_irq(unsigned int irq) +static void h8300_shutdown_irq(struct irq_data *data) { - if (is_ext_irq(irq)) - h8300_disable_irq_pin(irq); + if (is_ext_irq(data->irq)) + h8300_disable_irq_pin(data->irq); } /* @@ -73,12 +69,10 @@ static void h8300_shutdown_irq(unsigned int irq) */ struct irq_chip h8300irq_chip = { .name = "H8300-INTC", - .startup = h8300_startup_irq, - .shutdown = h8300_shutdown_irq, - .enable = h8300_enable_irq, - .disable = h8300_disable_irq, - .ack = NULL, - .end = h8300_end_irq, + .irq_startup = h8300_startup_irq, + .irq_shutdown = h8300_shutdown_irq, + .irq_enable = h8300_enable_irq, + .irq_disable = h8300_disable_irq, }; #if defined(CONFIG_RAMKERNEL) @@ -160,18 +154,14 @@ void __init init_IRQ(void) setup_vector(); - for (c = 0; c < NR_IRQS; c++) { - irq_desc[c].status = IRQ_DISABLED; - irq_desc[c].action = NULL; - irq_desc[c].depth = 1; - irq_desc[c].chip = &h8300irq_chip; - } + for (c = 0; c < NR_IRQS; c++) + set_irq_chip_and_handler(c, &h8300irq_chip, handle_simple_irq); } asmlinkage void do_IRQ(int irq) { irq_enter(); - __do_IRQ(irq); + generic_handle_irq(irq); irq_exit(); } @@ -192,7 +182,7 @@ int show_interrupts(struct seq_file *p, void *v) goto unlock; seq_printf(p, "%3d: ",i); seq_printf(p, "%10u ", kstat_irqs(i)); - seq_printf(p, " %14s", irq_desc[i].chip->name); + seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name); seq_printf(p, "-%-8s", irq_desc[i].name); seq_printf(p, " %s", action->name); diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index e0f5b6d7f84..fcf3b437a2d 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -22,6 +22,10 @@ config IA64 select HAVE_KVM select HAVE_ARCH_TRACEHOOK select HAVE_DMA_API_DEBUG + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE + select GENERIC_PENDING_IRQ if SMP + select IRQ_PER_CPU default y help The Itanium Processor Family is Intel's 64-bit successor to @@ -678,28 +682,6 @@ source "arch/ia64/kvm/Kconfig" source "lib/Kconfig" -# -# Use the generic interrupt handling code in kernel/irq/: -# -config GENERIC_HARDIRQS - def_bool y - -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - -config GENERIC_IRQ_PROBE - bool - default y - -config GENERIC_PENDING_IRQ - bool - depends on GENERIC_HARDIRQS && SMP - default y - -config IRQ_PER_CPU - bool - default y - config IOMMU_HELPER def_bool (IA64_HP_ZX1 || IA64_HP_ZX1_SWIOTLB || IA64_GENERIC || SWIOTLB) diff --git a/arch/ia64/include/asm/io.h b/arch/ia64/include/asm/io.h index cc8335eb311..e5a6c3530c6 100644 --- a/arch/ia64/include/asm/io.h +++ b/arch/ia64/include/asm/io.h @@ -426,6 +426,11 @@ extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size) extern void iounmap (volatile void __iomem *addr); extern void __iomem * early_ioremap (unsigned long phys_addr, unsigned long size); extern void early_iounmap (volatile void __iomem *addr, unsigned long size); +static inline void __iomem * ioremap_cache (unsigned long phys_addr, unsigned long size) +{ + return ioremap(phys_addr, size); +} + /* * String version of IO memory access ops: diff --git a/arch/ia64/include/asm/page.h b/arch/ia64/include/asm/page.h index 41b6d31110f..961a16f43e6 100644 --- a/arch/ia64/include/asm/page.h +++ b/arch/ia64/include/asm/page.h @@ -189,6 +189,7 @@ get_order (unsigned long size) # define pgprot_val(x) ((x).pgprot) # define __pte(x) ((pte_t) { (x) } ) +# define __pmd(x) ((pmd_t) { (x) } ) # define __pgprot(x) ((pgprot_t) { (x) } ) #else /* !STRICT_MM_TYPECHECKS */ diff --git a/arch/ia64/include/asm/processor.h b/arch/ia64/include/asm/processor.h index 348e44d08ce..03afe797074 100644 --- a/arch/ia64/include/asm/processor.h +++ b/arch/ia64/include/asm/processor.h @@ -717,8 +717,9 @@ prefetchw (const void *x) #define spin_lock_prefetch(x) prefetchw(x) extern unsigned long boot_option_idle_override; -extern unsigned long idle_halt; -extern unsigned long idle_nomwait; + +enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT, + IDLE_NOMWAIT, IDLE_POLL}; #endif /* !__ASSEMBLY__ */ diff --git a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c index 16f1c7b04c6..6d33c5cc94f 100644 --- a/arch/ia64/kernel/process.c +++ b/arch/ia64/kernel/process.c @@ -53,12 +53,8 @@ void (*ia64_mark_idle)(int); -unsigned long boot_option_idle_override = 0; +unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; EXPORT_SYMBOL(boot_option_idle_override); -unsigned long idle_halt; -EXPORT_SYMBOL(idle_halt); -unsigned long idle_nomwait; -EXPORT_SYMBOL(idle_nomwait); void (*pm_idle) (void); EXPORT_SYMBOL(pm_idle); void (*pm_power_off) (void); diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig index 5c291d65196..ef4c1e442be 100644 --- a/arch/m32r/Kconfig +++ b/arch/m32r/Kconfig @@ -7,6 +7,9 @@ config M32R select HAVE_KERNEL_GZIP select HAVE_KERNEL_BZIP2 select HAVE_KERNEL_LZMA + select HAVE_GENERIC_HARDIRQS + select GENERIC_HARDIRQS_NO_DEPRECATED + select GENERIC_IRQ_PROBE config SBUS bool @@ -19,14 +22,6 @@ config ZONE_DMA bool default y -config GENERIC_HARDIRQS - bool - default y - -config GENERIC_IRQ_PROBE - bool - default y - config NO_IOPORT def_bool y diff --git a/arch/m32r/configs/m32700ut.smp_defconfig b/arch/m32r/configs/m32700ut.smp_defconfig index 816c3ecaa2a..a3d727ed6a1 100644 --- a/arch/m32r/configs/m32700ut.smp_defconfig +++ b/arch/m32r/configs/m32700ut.smp_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=15 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set diff --git a/arch/m32r/configs/m32700ut.up_defconfig b/arch/m32r/configs/m32700ut.up_defconfig index 84785686640..b8334163099 100644 --- a/arch/m32r/configs/m32700ut.up_defconfig +++ b/arch/m32r/configs/m32700ut.up_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set diff --git a/arch/m32r/configs/mappi.nommu_defconfig b/arch/m32r/configs/mappi.nommu_defconfig index 354a964d084..7c90ce2fc42 100644 --- a/arch/m32r/configs/mappi.nommu_defconfig +++ b/arch/m32r/configs/mappi.nommu_defconfig @@ -3,7 +3,7 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set diff --git a/arch/m32r/configs/mappi.smp_defconfig b/arch/m32r/configs/mappi.smp_defconfig index 9022307bd07..367d07cebcd 100644 --- a/arch/m32r/configs/mappi.smp_defconfig +++ b/arch/m32r/configs/mappi.smp_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=15 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set diff --git a/arch/m32r/configs/mappi.up_defconfig b/arch/m32r/configs/mappi.up_defconfig index 3726068721a..cb11384386c 100644 --- a/arch/m32r/configs/mappi.up_defconfig +++ b/arch/m32r/configs/mappi.up_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set diff --git a/arch/m32r/configs/mappi2.opsp_defconfig b/arch/m32r/configs/mappi2.opsp_defconfig index 6136fad048e..3bff779259b 100644 --- a/arch/m32r/configs/mappi2.opsp_defconfig +++ b/arch/m32r/configs/mappi2.opsp_defconfig @@ -4,7 +4,7 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set diff --git a/arch/m32r/configs/mappi2.vdec2_defconfig b/arch/m32r/configs/mappi2.vdec2_defconfig index dce1fc7d67e..75246c9c1af 100644 --- a/arch/m32r/configs/mappi2.vdec2_defconfig +++ b/arch/m32r/configs/mappi2.vdec2_defconfig @@ -4,7 +4,7 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set diff --git a/arch/m32r/configs/mappi3.smp_defconfig b/arch/m32r/configs/mappi3.smp_defconfig index b204e2ecd0f..27cefd41ac1 100644 --- a/arch/m32r/configs/mappi3.smp_defconfig +++ b/arch/m32r/configs/mappi3.smp_defconfig @@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=15 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set diff --git a/arch/m32r/configs/oaks32r_defconfig b/arch/m32r/configs/oaks32r_defconfig index 5aa4ea9ebb1..5087a510ca4 100644 --- a/arch/m32r/configs/oaks32r_defconfig +++ b/arch/m32r/configs/oaks32r_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set diff --git a/arch/m32r/configs/opsput_defconfig b/arch/m32r/configs/opsput_defconfig index 8494c6a276e..50c6f525db2 100644 --- a/arch/m32r/configs/opsput_defconfig +++ b/arch/m32r/configs/opsput_defconfig @@ -4,7 +4,7 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set diff --git a/arch/m32r/configs/usrv_defconfig b/arch/m32r/configs/usrv_defconfig index 1df293bc2ab..a3cfaaedab6 100644 --- a/arch/m32r/configs/usrv_defconfig +++ b/arch/m32r/configs/usrv_defconfig @@ -5,7 +5,7 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=15 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/m32r/kernel/irq.c b/arch/m32r/kernel/irq.c index 7db26f1f082..f745c1287f3 100644 --- a/arch/m32r/kernel/irq.c +++ b/arch/m32r/kernel/irq.c @@ -40,8 +40,10 @@ int show_interrupts(struct seq_file *p, void *v) } if (i < NR_IRQS) { - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; + struct irq_desc *desc = irq_to_desc(i); + + raw_spin_lock_irqsave(&desc->lock, flags); + action = desc->action; if (!action) goto skip; seq_printf(p, "%3d: ",i); @@ -51,7 +53,7 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->name); + seq_printf(p, " %14s", desc->irq_data.chip->name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) @@ -59,7 +61,7 @@ int show_interrupts(struct seq_file *p, void *v) seq_putc(p, '\n'); skip: - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); + raw_spin_unlock_irqrestore(&desc->lock, flags); } return 0; } diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c index 402a59d7219..4a693d02c1e 100644 --- a/arch/m32r/platforms/m32104ut/setup.c +++ b/arch/m32r/platforms/m32104ut/setup.c @@ -39,39 +39,30 @@ static void enable_m32104ut_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_m32104ut(unsigned int irq) +static void mask_m32104ut_irq(struct irq_data *data) { - disable_m32104ut_irq(irq); + disable_m32104ut_irq(data->irq); } -static void end_m32104ut_irq(unsigned int irq) +static void unmask_m32104ut_irq(struct irq_data *data) { - enable_m32104ut_irq(irq); + enable_m32104ut_irq(data->irq); } -static unsigned int startup_m32104ut_irq(unsigned int irq) +static void shutdown_m32104ut_irq(struct irq_data *data) { - enable_m32104ut_irq(irq); - return (0); -} - -static void shutdown_m32104ut_irq(unsigned int irq) -{ - unsigned long port; + unsigned int irq = data->irq; + unsigned long port = irq2port(irq); - port = irq2port(irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip m32104ut_irq_type = { - .name = "M32104UT-IRQ", - .startup = startup_m32104ut_irq, - .shutdown = shutdown_m32104ut_irq, - .enable = enable_m32104ut_irq, - .disable = disable_m32104ut_irq, - .ack = mask_and_ack_m32104ut, - .end = end_m32104ut_irq + .name = "M32104UT-IRQ", + .irq_shutdown = shutdown_m32104ut_irq, + .irq_unmask = unmask_m32104ut_irq, + .irq_mask = mask_m32104ut_irq, }; void __init init_IRQ(void) @@ -85,36 +76,29 @@ void __init init_IRQ(void) #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ - irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT0].chip = &m32104ut_irq_type; - irq_desc[M32R_IRQ_INT0].action = 0; - irq_desc[M32R_IRQ_INT0].depth = 1; - icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */ + set_irq_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type, + handle_level_irq); + /* "H" level sense */ + cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; disable_m32104ut_irq(M32R_IRQ_INT0); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &m32104ut_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &m32104ut_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &m32104ut_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_SIO0_S); #endif /* CONFIG_SERIAL_M32R_SIO */ diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c index 80b1a026795..2074bcc841e 100644 --- a/arch/m32r/platforms/m32700ut/setup.c +++ b/arch/m32r/platforms/m32700ut/setup.c @@ -45,39 +45,30 @@ static void enable_m32700ut_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_m32700ut(unsigned int irq) +static void mask_m32700ut(struct irq_data *data) { - disable_m32700ut_irq(irq); + disable_m32700ut_irq(data->irq); } -static void end_m32700ut_irq(unsigned int irq) +static void unmask_m32700ut(struct irq_data *data) { - enable_m32700ut_irq(irq); + enable_m32700ut_irq(data->irq); } -static unsigned int startup_m32700ut_irq(unsigned int irq) -{ - enable_m32700ut_irq(irq); - return (0); -} - -static void shutdown_m32700ut_irq(unsigned int irq) +static void shutdown_m32700ut(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip m32700ut_irq_type = { - .name = "M32700UT-IRQ", - .startup = startup_m32700ut_irq, - .shutdown = shutdown_m32700ut_irq, - .enable = enable_m32700ut_irq, - .disable = disable_m32700ut_irq, - .ack = mask_and_ack_m32700ut, - .end = end_m32700ut_irq + .name = "M32700UT-IRQ", + .irq_shutdown = shutdown_m32700ut, + .irq_mask = mask_m32700ut, + .irq_unmask = unmask_m32700ut }; /* @@ -99,7 +90,6 @@ static void disable_m32700ut_pld_irq(unsigned int irq) unsigned int pldirq; pldirq = irq2pldirq(irq); -// disable_m32700ut_irq(M32R_IRQ_INT1); port = pldirq2port(pldirq); data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; outw(data, port); @@ -111,50 +101,38 @@ static void enable_m32700ut_pld_irq(unsigned int irq) unsigned int pldirq; pldirq = irq2pldirq(irq); -// enable_m32700ut_irq(M32R_IRQ_INT1); port = pldirq2port(pldirq); data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; outw(data, port); } -static void mask_and_ack_m32700ut_pld(unsigned int irq) -{ - disable_m32700ut_pld_irq(irq); -// mask_and_ack_m32700ut(M32R_IRQ_INT1); -} - -static void end_m32700ut_pld_irq(unsigned int irq) +static void mask_m32700ut_pld(struct irq_data *data) { - enable_m32700ut_pld_irq(irq); - end_m32700ut_irq(M32R_IRQ_INT1); + disable_m32700ut_pld_irq(data->irq); } -static unsigned int startup_m32700ut_pld_irq(unsigned int irq) +static void unmask_m32700ut_pld(struct irq_data *data) { - enable_m32700ut_pld_irq(irq); - return (0); + enable_m32700ut_pld_irq(data->irq); + enable_m32700ut_irq(M32R_IRQ_INT1); } -static void shutdown_m32700ut_pld_irq(unsigned int irq) +static void shutdown_m32700ut_pld_irq(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2pldirq(irq); -// shutdown_m32700ut_irq(M32R_IRQ_INT1); + pldirq = irq2pldirq(data->irq); port = pldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } static struct irq_chip m32700ut_pld_irq_type = { - .name = "M32700UT-PLD-IRQ", - .startup = startup_m32700ut_pld_irq, - .shutdown = shutdown_m32700ut_pld_irq, - .enable = enable_m32700ut_pld_irq, - .disable = disable_m32700ut_pld_irq, - .ack = mask_and_ack_m32700ut_pld, - .end = end_m32700ut_pld_irq + .name = "M32700UT-PLD-IRQ", + .irq_shutdown = shutdown_m32700ut_pld_irq, + .irq_mask = mask_m32700ut_pld, + .irq_unmask = unmask_m32700ut_pld, }; /* @@ -188,42 +166,33 @@ static void enable_m32700ut_lanpld_irq(unsigned int irq) outw(data, port); } -static void mask_and_ack_m32700ut_lanpld(unsigned int irq) +static void mask_m32700ut_lanpld(struct irq_data *data) { - disable_m32700ut_lanpld_irq(irq); + disable_m32700ut_lanpld_irq(data->irq); } -static void end_m32700ut_lanpld_irq(unsigned int irq) +static void unmask_m32700ut_lanpld(struct irq_data *data) { - enable_m32700ut_lanpld_irq(irq); - end_m32700ut_irq(M32R_IRQ_INT0); -} - -static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq) -{ - enable_m32700ut_lanpld_irq(irq); - return (0); + enable_m32700ut_lanpld_irq(data->irq); + enable_m32700ut_irq(M32R_IRQ_INT0); } -static void shutdown_m32700ut_lanpld_irq(unsigned int irq) +static void shutdown_m32700ut_lanpld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2lanpldirq(irq); + pldirq = irq2lanpldirq(data->irq); port = lanpldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } static struct irq_chip m32700ut_lanpld_irq_type = { - .name = "M32700UT-PLD-LAN-IRQ", - .startup = startup_m32700ut_lanpld_irq, - .shutdown = shutdown_m32700ut_lanpld_irq, - .enable = enable_m32700ut_lanpld_irq, - .disable = disable_m32700ut_lanpld_irq, - .ack = mask_and_ack_m32700ut_lanpld, - .end = end_m32700ut_lanpld_irq + .name = "M32700UT-PLD-LAN-IRQ", + .irq_shutdown = shutdown_m32700ut_lanpld, + .irq_mask = mask_m32700ut_lanpld, + .irq_unmask = unmask_m32700ut_lanpld, }; /* @@ -257,143 +226,110 @@ static void enable_m32700ut_lcdpld_irq(unsigned int irq) outw(data, port); } -static void mask_and_ack_m32700ut_lcdpld(unsigned int irq) +static void mask_m32700ut_lcdpld(struct irq_data *data) { - disable_m32700ut_lcdpld_irq(irq); + disable_m32700ut_lcdpld_irq(data->irq); } -static void end_m32700ut_lcdpld_irq(unsigned int irq) +static void unmask_m32700ut_lcdpld(struct irq_data *data) { - enable_m32700ut_lcdpld_irq(irq); - end_m32700ut_irq(M32R_IRQ_INT2); -} - -static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq) -{ - enable_m32700ut_lcdpld_irq(irq); - return (0); + enable_m32700ut_lcdpld_irq(data->irq); + enable_m32700ut_irq(M32R_IRQ_INT2); } -static void shutdown_m32700ut_lcdpld_irq(unsigned int irq) +static void shutdown_m32700ut_lcdpld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2lcdpldirq(irq); + pldirq = irq2lcdpldirq(data->irq); port = lcdpldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } static struct irq_chip m32700ut_lcdpld_irq_type = { - .name = "M32700UT-PLD-LCD-IRQ", - .startup = startup_m32700ut_lcdpld_irq, - .shutdown = shutdown_m32700ut_lcdpld_irq, - .enable = enable_m32700ut_lcdpld_irq, - .disable = disable_m32700ut_lcdpld_irq, - .ack = mask_and_ack_m32700ut_lcdpld, - .end = end_m32700ut_lcdpld_irq + .name = "M32700UT-PLD-LCD-IRQ", + .irq_shutdown = shutdown_m32700ut_lcdpld, + .irq_mask = mask_m32700ut_lcdpld, + .irq_unmask = unmask_m32700ut_lcdpld, }; void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ - irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED; - irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type; - irq_desc[M32700UT_LAN_IRQ_LAN].action = 0; - irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(M32700UT_LAN_IRQ_LAN, + &m32700ut_lanpld_irq_type, handle_level_irq); lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_m32700ut_irq(M32R_IRQ_MFT2); /* SIO0 : receive */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO0_R); /* SIO0 : send */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO0_S); /* SIO1 : receive */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = 0; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO1_R); /* SIO1 : send */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = 0; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO1_S); /* DMA1 : */ - irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type; - irq_desc[M32R_IRQ_DMA1].action = 0; - irq_desc[M32R_IRQ_DMA1].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_DMA1].icucr = 0; disable_m32700ut_irq(M32R_IRQ_DMA1); #ifdef CONFIG_SERIAL_M32R_PLDSIO /* INT#1: SIO0 Receive on PLD */ - irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_SIO0_RCV].action = 0; - irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); /* INT#1: SIO0 Send on PLD */ - irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_SIO0_SND].action = 0; - irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); #endif /* CONFIG_SERIAL_M32R_PLDSIO */ /* INT#1: CFC IREQ on PLD */ - irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_CFIREQ].action = 0; - irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); /* INT#1: CFC Insert on PLD */ - irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_CFC_INSERT].action = 0; - irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); /* INT#1: CFC Eject on PLD */ - irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_CFC_EJECT].action = 0; - irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); @@ -413,13 +349,11 @@ void __init init_IRQ(void) #if defined(CONFIG_USB) outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ + set_irq_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1, + &m32700ut_lcdpld_irq_type, handle_level_irq); - irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; - irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type; - irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0; - irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1; - lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ - disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1); + lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ + disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1); #endif /* * INT2# is used for BAT, USB, AUDIO @@ -432,10 +366,8 @@ void __init init_IRQ(void) /* * INT3# is used for AR */ - irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type; - irq_desc[M32R_IRQ_INT3].action = 0; - irq_desc[M32R_IRQ_INT3].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_m32700ut_irq(M32R_IRQ_INT3); #endif /* CONFIG_VIDEO_M32R_AR */ diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c index ea00c84d6b1..cdd8c457402 100644 --- a/arch/m32r/platforms/mappi/setup.c +++ b/arch/m32r/platforms/mappi/setup.c @@ -38,40 +38,30 @@ static void enable_mappi_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_mappi(unsigned int irq) +static void mask_mappi(struct irq_data *data) { - disable_mappi_irq(irq); + disable_mappi_irq(data->irq); } -static void end_mappi_irq(unsigned int irq) +static void unmask_mappi(struct irq_data *data) { - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - enable_mappi_irq(irq); + enable_mappi_irq(data->irq); } -static unsigned int startup_mappi_irq(unsigned int irq) -{ - enable_mappi_irq(irq); - return (0); -} - -static void shutdown_mappi_irq(unsigned int irq) +static void shutdown_mappi(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip mappi_irq_type = { - .name = "MAPPI-IRQ", - .startup = startup_mappi_irq, - .shutdown = shutdown_mappi_irq, - .enable = enable_mappi_irq, - .disable = disable_mappi_irq, - .ack = mask_and_ack_mappi, - .end = end_mappi_irq + .name = "MAPPI-IRQ", + .irq_shutdown = shutdown_mappi, + .irq_mask = mask_mappi, + .irq_unmask = unmask_mappi, }; void __init init_IRQ(void) @@ -85,70 +75,54 @@ void __init init_IRQ(void) #ifdef CONFIG_NE2000 /* INT0 : LAN controller (RTL8019AS) */ - irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_INT0].action = NULL; - irq_desc[M32R_IRQ_INT0].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; disable_mappi_irq(M32R_IRQ_INT0); #endif /* CONFIG_M32R_NE2000 */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_MFT2].action = NULL; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = NULL; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = NULL; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = NULL; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = NULL; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_SERIAL_M32R_SIO */ #if defined(CONFIG_M32R_PCC) /* INT1 : pccard0 interrupt */ - irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_INT1].action = NULL; - irq_desc[M32R_IRQ_INT1].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; disable_mappi_irq(M32R_IRQ_INT1); /* INT2 : pccard1 interrupt */ - irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_INT2].action = NULL; - irq_desc[M32R_IRQ_INT2].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; disable_mappi_irq(M32R_IRQ_INT2); #endif /* CONFIG_M32RPCC */ diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c index c049376d027..9117c30ea36 100644 --- a/arch/m32r/platforms/mappi2/setup.c +++ b/arch/m32r/platforms/mappi2/setup.c @@ -46,126 +46,97 @@ static void enable_mappi2_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_mappi2(unsigned int irq) +static void mask_mappi2(struct irq_data *data) { - disable_mappi2_irq(irq); + disable_mappi2_irq(data->irq); } -static void end_mappi2_irq(unsigned int irq) +static void unmask_mappi2(struct irq_data *data) { - enable_mappi2_irq(irq); + enable_mappi2_irq(data->irq); } -static unsigned int startup_mappi2_irq(unsigned int irq) -{ - enable_mappi2_irq(irq); - return (0); -} - -static void shutdown_mappi2_irq(unsigned int irq) +static void shutdown_mappi2(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip mappi2_irq_type = { - .name = "MAPPI2-IRQ", - .startup = startup_mappi2_irq, - .shutdown = shutdown_mappi2_irq, - .enable = enable_mappi2_irq, - .disable = disable_mappi2_irq, - .ack = mask_and_ack_mappi2, - .end = end_mappi2_irq + .name = "MAPPI2-IRQ", + .irq_shutdown = shutdown_mappi2, + .irq_mask = mask_mappi2, + .irq_unmask = unmask_mappi2, }; void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT0 : LAN controller (SMC91111) */ - irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT0].chip = &mappi2_irq_type; - irq_desc[M32R_IRQ_INT0].action = 0; - irq_desc[M32R_IRQ_INT0].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi2_irq(M32R_IRQ_INT0); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &mappi2_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi2_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &mappi2_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &mappi2_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &mappi2_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = 0; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &mappi2_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = 0; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_M32R_USE_DBG_CONSOLE */ #if defined(CONFIG_USB) /* INT1 : USB Host controller interrupt */ - irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT1].chip = &mappi2_irq_type; - irq_desc[M32R_IRQ_INT1].action = 0; - irq_desc[M32R_IRQ_INT1].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; disable_mappi2_irq(M32R_IRQ_INT1); #endif /* CONFIG_USB */ /* ICUCR40: CFC IREQ */ - irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFIREQ].chip = &mappi2_irq_type; - irq_desc[PLD_IRQ_CFIREQ].action = 0; - irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type, + handle_level_irq); icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; disable_mappi2_irq(PLD_IRQ_CFIREQ); #if defined(CONFIG_M32R_CFC) /* ICUCR41: CFC Insert */ - irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi2_irq_type; - irq_desc[PLD_IRQ_CFC_INSERT].action = 0; - irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type, + handle_level_irq); icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; disable_mappi2_irq(PLD_IRQ_CFC_INSERT); /* ICUCR42: CFC Eject */ - irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_EJECT].chip = &mappi2_irq_type; - irq_desc[PLD_IRQ_CFC_EJECT].action = 0; - irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type, + handle_level_irq); icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi2_irq(PLD_IRQ_CFC_EJECT); #endif /* CONFIG_MAPPI2_CFC */ diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c index 882de25c6e8..b44f5ded2bb 100644 --- a/arch/m32r/platforms/mappi3/setup.c +++ b/arch/m32r/platforms/mappi3/setup.c @@ -46,128 +46,98 @@ static void enable_mappi3_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_mappi3(unsigned int irq) +static void mask_mappi3(struct irq_data *data) { - disable_mappi3_irq(irq); + disable_mappi3_irq(data->irq); } -static void end_mappi3_irq(unsigned int irq) +static void unmask_mappi3(struct irq_data *data) { - enable_mappi3_irq(irq); + enable_mappi3_irq(data->irq); } -static unsigned int startup_mappi3_irq(unsigned int irq) -{ - enable_mappi3_irq(irq); - return (0); -} - -static void shutdown_mappi3_irq(unsigned int irq) +static void shutdown_mappi3(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } -static struct irq_chip mappi3_irq_type = -{ - .name = "MAPPI3-IRQ", - .startup = startup_mappi3_irq, - .shutdown = shutdown_mappi3_irq, - .enable = enable_mappi3_irq, - .disable = disable_mappi3_irq, - .ack = mask_and_ack_mappi3, - .end = end_mappi3_irq +static struct irq_chip mappi3_irq_type = { + .name = "MAPPI3-IRQ", + .irq_shutdown = shutdown_mappi3, + .irq_mask = mask_mappi3, + .irq_unmask = unmask_mappi3, }; void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT0 : LAN controller (SMC91111) */ - irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type; - irq_desc[M32R_IRQ_INT0].action = 0; - irq_desc[M32R_IRQ_INT0].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi3_irq(M32R_IRQ_INT0); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi3_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = 0; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = 0; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_M32R_USE_DBG_CONSOLE */ #if defined(CONFIG_USB) /* INT1 : USB Host controller interrupt */ - irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type; - irq_desc[M32R_IRQ_INT1].action = 0; - irq_desc[M32R_IRQ_INT1].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; disable_mappi3_irq(M32R_IRQ_INT1); #endif /* CONFIG_USB */ /* CFC IREQ */ - irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type; - irq_desc[PLD_IRQ_CFIREQ].action = 0; - irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type, + handle_level_irq); icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; disable_mappi3_irq(PLD_IRQ_CFIREQ); #if defined(CONFIG_M32R_CFC) /* ICUCR41: CFC Insert & eject */ - irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type; - irq_desc[PLD_IRQ_CFC_INSERT].action = 0; - irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type, + handle_level_irq); icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; disable_mappi3_irq(PLD_IRQ_CFC_INSERT); #endif /* CONFIG_M32R_CFC */ /* IDE IREQ */ - irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type; - irq_desc[PLD_IRQ_IDEIREQ].action = 0; - irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type, + handle_level_irq); icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi3_irq(PLD_IRQ_IDEIREQ); diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c index d11d93bf74f..19a02db7b81 100644 --- a/arch/m32r/platforms/oaks32r/setup.c +++ b/arch/m32r/platforms/oaks32r/setup.c @@ -37,39 +37,30 @@ static void enable_oaks32r_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_mappi(unsigned int irq) +static void mask_oaks32r(struct irq_data *data) { - disable_oaks32r_irq(irq); + disable_oaks32r_irq(data->irq); } -static void end_oaks32r_irq(unsigned int irq) +static void unmask_oaks32r(struct irq_data *data) { - enable_oaks32r_irq(irq); + enable_oaks32r_irq(data->irq); } -static unsigned int startup_oaks32r_irq(unsigned int irq) -{ - enable_oaks32r_irq(irq); - return (0); -} - -static void shutdown_oaks32r_irq(unsigned int irq) +static void shutdown_oaks32r(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip oaks32r_irq_type = { - .name = "OAKS32R-IRQ", - .startup = startup_oaks32r_irq, - .shutdown = shutdown_oaks32r_irq, - .enable = enable_oaks32r_irq, - .disable = disable_oaks32r_irq, - .ack = mask_and_ack_mappi, - .end = end_oaks32r_irq + .name = "OAKS32R-IRQ", + .irq_shutdown = shutdown_oaks32r, + .irq_mask = mask_oaks32r, + .irq_unmask = unmask_oaks32r, }; void __init init_IRQ(void) @@ -83,52 +74,40 @@ void __init init_IRQ(void) #ifdef CONFIG_NE2000 /* INT3 : LAN controller (RTL8019AS) */ - irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type; - irq_desc[M32R_IRQ_INT3].action = 0; - irq_desc[M32R_IRQ_INT3].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_oaks32r_irq(M32R_IRQ_INT3); #endif /* CONFIG_M32R_NE2000 */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_oaks32r_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = 0; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = 0; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_SERIAL_M32R_SIO */ diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index 5f3402a2fba..12731547e8b 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c @@ -46,39 +46,30 @@ static void enable_opsput_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_opsput(unsigned int irq) +static void mask_opsput(struct irq_data *data) { - disable_opsput_irq(irq); + disable_opsput_irq(data->irq); } -static void end_opsput_irq(unsigned int irq) +static void unmask_opsput(struct irq_data *data) { - enable_opsput_irq(irq); + enable_opsput_irq(data->irq); } -static unsigned int startup_opsput_irq(unsigned int irq) -{ - enable_opsput_irq(irq); - return (0); -} - -static void shutdown_opsput_irq(unsigned int irq) +static void shutdown_opsput(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip opsput_irq_type = { - .name = "OPSPUT-IRQ", - .startup = startup_opsput_irq, - .shutdown = shutdown_opsput_irq, - .enable = enable_opsput_irq, - .disable = disable_opsput_irq, - .ack = mask_and_ack_opsput, - .end = end_opsput_irq + .name = "OPSPUT-IRQ", + .irq_shutdown = shutdown_opsput, + .irq_mask = mask_opsput, + .irq_unmask = unmask_opsput, }; /* @@ -100,7 +91,6 @@ static void disable_opsput_pld_irq(unsigned int irq) unsigned int pldirq; pldirq = irq2pldirq(irq); -// disable_opsput_irq(M32R_IRQ_INT1); port = pldirq2port(pldirq); data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; outw(data, port); @@ -112,50 +102,38 @@ static void enable_opsput_pld_irq(unsigned int irq) unsigned int pldirq; pldirq = irq2pldirq(irq); -// enable_opsput_irq(M32R_IRQ_INT1); port = pldirq2port(pldirq); data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; outw(data, port); } -static void mask_and_ack_opsput_pld(unsigned int irq) -{ - disable_opsput_pld_irq(irq); -// mask_and_ack_opsput(M32R_IRQ_INT1); -} - -static void end_opsput_pld_irq(unsigned int irq) +static void mask_opsput_pld(struct irq_data *data) { - enable_opsput_pld_irq(irq); - end_opsput_irq(M32R_IRQ_INT1); + disable_opsput_pld_irq(data->irq); } -static unsigned int startup_opsput_pld_irq(unsigned int irq) +static void unmask_opsput_pld(struct irq_data *data) { - enable_opsput_pld_irq(irq); - return (0); + enable_opsput_pld_irq(data->irq); + enable_opsput_irq(M32R_IRQ_INT1); } -static void shutdown_opsput_pld_irq(unsigned int irq) +static void shutdown_opsput_pld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2pldirq(irq); -// shutdown_opsput_irq(M32R_IRQ_INT1); + pldirq = irq2pldirq(data->irq); port = pldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } static struct irq_chip opsput_pld_irq_type = { - .name = "OPSPUT-PLD-IRQ", - .startup = startup_opsput_pld_irq, - .shutdown = shutdown_opsput_pld_irq, - .enable = enable_opsput_pld_irq, - .disable = disable_opsput_pld_irq, - .ack = mask_and_ack_opsput_pld, - .end = end_opsput_pld_irq + .name = "OPSPUT-PLD-IRQ", + .irq_shutdown = shutdown_opsput_pld, + .irq_mask = mask_opsput_pld, + .irq_unmask = unmask_opsput_pld, }; /* @@ -189,42 +167,33 @@ static void enable_opsput_lanpld_irq(unsigned int irq) outw(data, port); } -static void mask_and_ack_opsput_lanpld(unsigned int irq) -{ - disable_opsput_lanpld_irq(irq); -} - -static void end_opsput_lanpld_irq(unsigned int irq) +static void mask_opsput_lanpld(struct irq_data *data) { - enable_opsput_lanpld_irq(irq); - end_opsput_irq(M32R_IRQ_INT0); + disable_opsput_lanpld_irq(data->irq); } -static unsigned int startup_opsput_lanpld_irq(unsigned int irq) +static void unmask_opsput_lanpld(struct irq_data *data) { - enable_opsput_lanpld_irq(irq); - return (0); + enable_opsput_lanpld_irq(data->irq); + enable_opsput_irq(M32R_IRQ_INT0); } -static void shutdown_opsput_lanpld_irq(unsigned int irq) +static void shutdown_opsput_lanpld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2lanpldirq(irq); + pldirq = irq2lanpldirq(data->irq); port = lanpldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } static struct irq_chip opsput_lanpld_irq_type = { - .name = "OPSPUT-PLD-LAN-IRQ", - .startup = startup_opsput_lanpld_irq, - .shutdown = shutdown_opsput_lanpld_irq, - .enable = enable_opsput_lanpld_irq, - .disable = disable_opsput_lanpld_irq, - .ack = mask_and_ack_opsput_lanpld, - .end = end_opsput_lanpld_irq + .name = "OPSPUT-PLD-LAN-IRQ", + .irq_shutdown = shutdown_opsput_lanpld, + .irq_mask = mask_opsput_lanpld, + .irq_unmask = unmask_opsput_lanpld, }; /* @@ -258,143 +227,109 @@ static void enable_opsput_lcdpld_irq(unsigned int irq) outw(data, port); } -static void mask_and_ack_opsput_lcdpld(unsigned int irq) -{ - disable_opsput_lcdpld_irq(irq); -} - -static void end_opsput_lcdpld_irq(unsigned int irq) +static void mask_opsput_lcdpld(struct irq_data *data) { - enable_opsput_lcdpld_irq(irq); - end_opsput_irq(M32R_IRQ_INT2); + disable_opsput_lcdpld_irq(data->irq); } -static unsigned int startup_opsput_lcdpld_irq(unsigned int irq) +static void unmask_opsput_lcdpld(struct irq_data *data) { - enable_opsput_lcdpld_irq(irq); - return (0); + enable_opsput_lcdpld_irq(data->irq); + enable_opsput_irq(M32R_IRQ_INT2); } -static void shutdown_opsput_lcdpld_irq(unsigned int irq) +static void shutdown_opsput_lcdpld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2lcdpldirq(irq); + pldirq = irq2lcdpldirq(data->irq); port = lcdpldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } -static struct irq_chip opsput_lcdpld_irq_type = -{ - "OPSPUT-PLD-LCD-IRQ", - startup_opsput_lcdpld_irq, - shutdown_opsput_lcdpld_irq, - enable_opsput_lcdpld_irq, - disable_opsput_lcdpld_irq, - mask_and_ack_opsput_lcdpld, - end_opsput_lcdpld_irq +static struct irq_chip opsput_lcdpld_irq_type = { + .name = "OPSPUT-PLD-LCD-IRQ", + .irq_shutdown = shutdown_opsput_lcdpld, + .irq_mask = mask_opsput_lcdpld, + .irq_unmask = unmask_opsput_lcdpld, }; void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ - irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED; - irq_desc[OPSPUT_LAN_IRQ_LAN].chip = &opsput_lanpld_irq_type; - irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0; - irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type, + handle_level_irq); lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_opsput_irq(M32R_IRQ_MFT2); /* SIO0 : receive */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO0_R); /* SIO0 : send */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO0_S); /* SIO1 : receive */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = 0; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO1_R); /* SIO1 : send */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = 0; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO1_S); /* DMA1 : */ - irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_DMA1].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_DMA1].action = 0; - irq_desc[M32R_IRQ_DMA1].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_DMA1].icucr = 0; disable_opsput_irq(M32R_IRQ_DMA1); #ifdef CONFIG_SERIAL_M32R_PLDSIO /* INT#1: SIO0 Receive on PLD */ - irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_SIO0_RCV].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_SIO0_RCV].action = 0; - irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); /* INT#1: SIO0 Send on PLD */ - irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_SIO0_SND].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_SIO0_SND].action = 0; - irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); #endif /* CONFIG_SERIAL_M32R_PLDSIO */ /* INT#1: CFC IREQ on PLD */ - irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFIREQ].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_CFIREQ].action = 0; - irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_opsput_pld_irq(PLD_IRQ_CFIREQ); /* INT#1: CFC Insert on PLD */ - irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_INSERT].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_CFC_INSERT].action = 0; - irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); /* INT#1: CFC Eject on PLD */ - irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_EJECT].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_CFC_EJECT].action = 0; - irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); @@ -413,14 +348,11 @@ void __init init_IRQ(void) enable_opsput_irq(M32R_IRQ_INT1); #if defined(CONFIG_USB) - outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ - - irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; - irq_desc[OPSPUT_LCD_IRQ_USB_INT1].chip = &opsput_lcdpld_irq_type; - irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0; - irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1; - lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ - disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); + outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ + set_irq_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1, + &opsput_lcdpld_irq_type, handle_level_irq); + lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ + disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); #endif /* * INT2# is used for BAT, USB, AUDIO @@ -433,10 +365,8 @@ void __init init_IRQ(void) /* * INT3# is used for AR */ - irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT3].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_INT3].action = 0; - irq_desc[M32R_IRQ_INT3].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_opsput_irq(M32R_IRQ_INT3); #endif /* CONFIG_VIDEO_M32R_AR */ diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c index 1beac7a51ed..f3cff26d6e7 100644 --- a/arch/m32r/platforms/usrv/setup.c +++ b/arch/m32r/platforms/usrv/setup.c @@ -37,39 +37,30 @@ static void enable_mappi_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_mappi(unsigned int irq) +static void mask_mappi(struct irq_data *data) { - disable_mappi_irq(irq); + disable_mappi_irq(data->irq); } -static void end_mappi_irq(unsigned int irq) +static void unmask_mappi(struct irq_data *data) { - enable_mappi_irq(irq); + enable_mappi_irq(data->irq); } -static unsigned int startup_mappi_irq(unsigned int irq) -{ - enable_mappi_irq(irq); - return 0; -} - -static void shutdown_mappi_irq(unsigned int irq) +static void shutdown_mappi(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip mappi_irq_type = { - .name = "M32700-IRQ", - .startup = startup_mappi_irq, - .shutdown = shutdown_mappi_irq, - .enable = enable_mappi_irq, - .disable = disable_mappi_irq, - .ack = mask_and_ack_mappi, - .end = end_mappi_irq + .name = "M32700-IRQ", + .irq_shutdown = shutdown_mappi, + .irq_mask = mask_mappi, + .irq_unmask = unmask_mappi, }; /* @@ -107,42 +98,33 @@ static void enable_m32700ut_pld_irq(unsigned int irq) outw(data, port); } -static void mask_and_ack_m32700ut_pld(unsigned int irq) +static void mask_m32700ut_pld(struct irq_data *data) { - disable_m32700ut_pld_irq(irq); + disable_m32700ut_pld_irq(data->irq); } -static void end_m32700ut_pld_irq(unsigned int irq) +static void unmask_m32700ut_pld(struct irq_data *data) { - enable_m32700ut_pld_irq(irq); - end_mappi_irq(M32R_IRQ_INT1); -} - -static unsigned int startup_m32700ut_pld_irq(unsigned int irq) -{ - enable_m32700ut_pld_irq(irq); - return 0; + enable_m32700ut_pld_irq(data->irq); + enable_mappi_irq(M32R_IRQ_INT1); } -static void shutdown_m32700ut_pld_irq(unsigned int irq) +static void shutdown_m32700ut_pld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2pldirq(irq); + pldirq = irq2pldirq(data->irq); port = pldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } static struct irq_chip m32700ut_pld_irq_type = { - .name = "USRV-PLD-IRQ", - .startup = startup_m32700ut_pld_irq, - .shutdown = shutdown_m32700ut_pld_irq, - .enable = enable_m32700ut_pld_irq, - .disable = disable_m32700ut_pld_irq, - .ack = mask_and_ack_m32700ut_pld, - .end = end_m32700ut_pld_irq + .name = "USRV-PLD-IRQ", + .irq_shutdown = shutdown_m32700ut_pld, + .irq_mask = mask_m32700ut_pld, + .irq_unmask = unmask_m32700ut_pld, }; void __init init_IRQ(void) @@ -156,53 +138,42 @@ void __init init_IRQ(void) once++; /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi_irq(M32R_IRQ_MFT2); #if defined(CONFIG_SERIAL_M32R_SIO) /* SIO0_R : uart receive data */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = 0; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = 0; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_SERIAL_M32R_SIO */ /* INT#67-#71: CFC#0 IREQ on PLD */ for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { - irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_CF0 + i].action = 0; - irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_CF0 + i, + &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr = PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i); @@ -210,19 +181,15 @@ void __init init_IRQ(void) #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) /* INT#76: 16552D#0 IREQ on PLD */ - irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_UART0].action = 0; - irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr = PLD_ICUCR_ISMOD03; /* 'H' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_UART0); /* INT#77: 16552D#1 IREQ on PLD */ - irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_UART1].action = 0; - irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr = PLD_ICUCR_ISMOD03; /* 'H' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_UART1); @@ -230,10 +197,8 @@ void __init init_IRQ(void) #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) /* INT#80: AK4524 IREQ on PLD */ - irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_SNDINT].action = 0; - irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */ + set_irq_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr = PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_SNDINT); diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index 7085bd51668..cb88aa96c4f 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -2,21 +2,22 @@ #define _M68KNOMMU_CACHEFLUSH_H /* - * (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com> + * (C) Copyright 2000-2010, Greg Ungerer <gerg@snapgear.com> */ #include <linux/mm.h> +#include <asm/mcfsim.h> #define flush_cache_all() __flush_cache_all() #define flush_cache_mm(mm) do { } while (0) #define flush_cache_dup_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) __flush_cache_all() +#define flush_cache_range(vma, start, end) do { } while (0) #define flush_cache_page(vma, vmaddr) do { } while (0) -#define flush_dcache_range(start,len) __flush_cache_all() +#define flush_dcache_range(start, len) __flush_dcache_all() #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 #define flush_dcache_page(page) do { } while (0) #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) -#define flush_icache_range(start,len) __flush_cache_all() +#define flush_icache_range(start, len) __flush_icache_all() #define flush_icache_page(vma,pg) do { } while (0) #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) #define flush_cache_vmap(start, end) do { } while (0) @@ -27,66 +28,52 @@ #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ memcpy(dst, src, len) +void mcf_cache_push(void); + static inline void __flush_cache_all(void) { -#if defined(CONFIG_M5407) || defined(CONFIG_M548x) - /* - * Use cpushl to push and invalidate all cache lines. - * Gas doesn't seem to know how to generate the ColdFire - * cpushl instruction... Oh well, bit stuff it for now. - */ - __asm__ __volatile__ ( - "nop\n\t" - "clrl %%d0\n\t" - "1:\n\t" - "movel %%d0,%%a0\n\t" - "2:\n\t" - ".word 0xf468\n\t" - "addl #0x10,%%a0\n\t" - "cmpl #0x00000800,%%a0\n\t" - "blt 2b\n\t" - "addql #1,%%d0\n\t" - "cmpil #4,%%d0\n\t" - "bne 1b\n\t" - "movel #0xb6088500,%%d0\n\t" - "movec %%d0,%%CACR\n\t" - : : : "d0", "a0" ); -#endif /* CONFIG_M5407 */ -#if defined(CONFIG_M523x) || defined(CONFIG_M527x) - __asm__ __volatile__ ( - "movel #0x81400100, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M523x || CONFIG_M527x */ -#if defined(CONFIG_M528x) - __asm__ __volatile__ ( - "movel #0x81000200, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M528x */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272) +#ifdef CACHE_PUSH + mcf_cache_push(); +#endif +#ifdef CACHE_INVALIDATE __asm__ __volatile__ ( - "movel #0x81000100, %%d0\n\t" + "movel %0, %%d0\n\t" "movec %%d0, %%CACR\n\t" "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ -#ifdef CONFIG_M5249 + : : "i" (CACHE_INVALIDATE) : "d0" ); +#endif +} + +/* + * Some ColdFire parts implement separate instruction and data caches, + * on those we should just flush the appropriate cache. If we don't need + * to do any specific flushing then this will be optimized away. + */ +static inline void __flush_icache_all(void) +{ +#ifdef CACHE_INVALIDATEI __asm__ __volatile__ ( - "movel #0xa1000200, %%d0\n\t" + "movel %0, %%d0\n\t" "movec %%d0, %%CACR\n\t" "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M5249 */ -#ifdef CONFIG_M532x + : : "i" (CACHE_INVALIDATEI) : "d0" ); +#endif +} + +static inline void __flush_dcache_all(void) +{ +#ifdef CACHE_PUSH + mcf_cache_push(); +#endif +#ifdef CACHE_INVALIDATED __asm__ __volatile__ ( - "movel #0x81000200, %%d0\n\t" + "movel %0, %%d0\n\t" "movec %%d0, %%CACR\n\t" "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M532x */ + : : "i" (CACHE_INVALIDATED) : "d0" ); +#else + /* Flush the wrtite buffer */ + __asm__ __volatile__ ( "nop" ); +#endif } - #endif /* _M68KNOMMU_CACHEFLUSH_H */ diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h index 3b0a34d0fe3..213028cbe11 100644 --- a/arch/m68k/include/asm/coldfire.h +++ b/arch/m68k/include/asm/coldfire.h @@ -32,7 +32,7 @@ */ #define MCF_MBAR 0x10000000 #define MCF_MBAR2 0x80000000 -#if defined(CONFIG_M548x) +#if defined(CONFIG_M54xx) #define MCF_IPSBAR MCF_MBAR #elif defined(CONFIG_M520x) #define MCF_IPSBAR 0xFC000000 diff --git a/arch/m68k/include/asm/entry_no.h b/arch/m68k/include/asm/entry_no.h index 26be277394f..627d69bacc5 100644 --- a/arch/m68k/include/asm/entry_no.h +++ b/arch/m68k/include/asm/entry_no.h @@ -42,12 +42,16 @@ */ #ifdef CONFIG_COLDFIRE +#ifdef CONFIG_COLDFIRE_SW_A7 /* - * This is made a little more tricky on the ColdFire. There is no - * separate kernel and user stack pointers. Need to artificially + * This is made a little more tricky on older ColdFires. There is no + * separate supervisor and user stack pointers. Need to artificially * construct a usp in software... When doing this we need to disable - * interrupts, otherwise bad things could happen. + * interrupts, otherwise bad things will happen. */ +.globl sw_usp +.globl sw_ksp + .macro SAVE_ALL move #0x2700,%sr /* disable intrs */ btst #5,%sp@(2) /* from user? */ @@ -74,9 +78,7 @@ 7: .endm -.macro RESTORE_ALL - btst #5,%sp@(PT_SR) /* going user? */ - bnes 8f /* no, skip */ +.macro RESTORE_USER move #0x2700,%sr /* disable intrs */ movel sw_usp,%a0 /* get usp */ movel %sp@(PT_OFF_PC),%a0@- /* copy exception program counter */ @@ -91,19 +93,22 @@ subql #8,sw_usp /* set exception */ movel sw_usp,%sp /* restore usp */ rte - 8: - moveml %sp@,%d1-%d5/%a0-%a2 - lea %sp@(32),%sp /* space for 8 regs */ - movel %sp@+,%d0 - addql #4,%sp /* orig d0 */ - addl %sp@+,%sp /* stkadj */ - rte .endm +.macro RDUSP + movel sw_usp,%a2 +.endm + +.macro WRUSP + movel %a0,sw_usp +.endm + +#else /* !CONFIG_COLDFIRE_SW_A7 */ /* - * Quick exception save, use current stack only. + * Modern ColdFire parts have separate supervisor and user stack + * pointers. Simple load and restore macros for this case. */ -.macro SAVE_LOCAL +.macro SAVE_ALL move #0x2700,%sr /* disable intrs */ clrl %sp@- /* stkadj */ movel %d0,%sp@- /* orig d0 */ @@ -112,7 +117,7 @@ moveml %d1-%d5/%a0-%a2,%sp@ .endm -.macro RESTORE_LOCAL +.macro RESTORE_USER moveml %sp@,%d1-%d5/%a0-%a2 lea %sp@(32),%sp /* space for 8 regs */ movel %sp@+,%d0 @@ -121,6 +126,18 @@ rte .endm +.macro RDUSP + /*move %usp,%a2*/ + .word 0x4e6a +.endm + +.macro WRUSP + /*move %a0,%usp*/ + .word 0x4e60 +.endm + +#endif /* !CONFIG_COLDFIRE_SW_A7 */ + .macro SAVE_SWITCH_STACK lea %sp@(-24),%sp /* 6 regs */ moveml %a3-%a6/%d6-%d7,%sp@ @@ -131,14 +148,6 @@ lea %sp@(24),%sp /* 6 regs */ .endm -/* - * Software copy of the user and kernel stack pointers... Ugh... - * Need these to get around ColdFire not having separate kernel - * and user stack pointers. - */ -.globl sw_usp -.globl sw_ksp - #else /* !CONFIG_COLDFIRE */ /* @@ -167,6 +176,6 @@ moveml %sp@+,%a3-%a6/%d6-%d7 .endm -#endif /* !CONFIG_COLDFIRE */ +#endif /* !COLDFIRE_SW_A7 */ #endif /* __ASSEMBLY__ */ #endif /* __M68KNOMMU_ENTRY_H */ diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h index 1b57adbafad..c64c7b74cf8 100644 --- a/arch/m68k/include/asm/gpio.h +++ b/arch/m68k/include/asm/gpio.h @@ -37,7 +37,7 @@ #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M532x) || defined(CONFIG_M548x) + defined(CONFIG_M532x) || defined(CONFIG_M54xx) /* These parts have GPIO organized by 8 bit ports */ diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h index 6e2413e518c..cf20f3097af 100644 --- a/arch/m68k/include/asm/io_no.h +++ b/arch/m68k/include/asm/io_no.h @@ -145,7 +145,6 @@ static inline void io_insl(unsigned int addr, void *buf, int len) #define IOMAP_WRITETHROUGH 3 extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag); -extern void __iounmap(void *addr, unsigned long size); static inline void *ioremap(unsigned long physaddr, unsigned long size) { diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index 9c384e294af..561b03b5ddf 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h @@ -12,6 +12,10 @@ #define m5206sim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m5206)" +#define CPU_INSTR_PER_JIFFY 3 + +#include <asm/m52xxacr.h> /* * Define the 5206 SIM register set addresses. @@ -88,6 +92,14 @@ #define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */ #define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */ +#if defined(CONFIG_NETtel) +#define MCFUART_BASE1 0x180 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ +#else +#define MCFUART_BASE1 0x140 /* Base address of UART1 */ +#define MCFUART_BASE2 0x180 /* Base address of UART2 */ +#endif + /* * Define system peripheral IRQ usage. */ @@ -95,7 +107,7 @@ #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ /* - * Generic GPIO + * Generic GPIO */ #define MCFGPIO_PIN_MAX 8 #define MCFGPIO_IRQ_VECBASE -1 diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index db824a4b136..88ed8239fe4 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -11,6 +11,11 @@ #define m520xsim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m520x)" +#define CPU_INSTR_PER_JIFFY 3 + +#include <asm/m52xxacr.h> + /* * Define the 520x SIM register set addresses. */ @@ -54,6 +59,9 @@ #define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ #define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ +/* + * EPORT and GPIO registers. + */ #define MCFEPORT_EPDDR 0xFC088002 #define MCFEPORT_EPDR 0xFC088004 #define MCFEPORT_EPPDR 0xFC088005 @@ -97,6 +105,7 @@ #define MCFGPIO_PCLRR_UART 0xFC0A402A #define MCFGPIO_PCLRR_FECH 0xFC0A402B #define MCFGPIO_PCLRR_FECL 0xFC0A402C + /* * Generic GPIO support */ @@ -109,7 +118,6 @@ #define MCFGPIO_PIN_MAX 80 #define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE -/****************************************************************************/ #define MCF_GPIO_PAR_UART (0xA4036) #define MCF_GPIO_PAR_FECI2C (0xA4033) @@ -126,6 +134,13 @@ #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) /* + * UART module. + */ +#define MCFUART_BASE1 0x60000 /* Base address of UART1 */ +#define MCFUART_BASE2 0x64000 /* Base address of UART2 */ +#define MCFUART_BASE3 0x68000 /* Base address of UART2 */ + +/* * Reset Controll Unit. */ #define MCF_RCR 0xFC0A0000 diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index e8d06b24a48..4ad7a00257a 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h @@ -11,6 +11,10 @@ #define m523xsim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m523x)" +#define CPU_INSTR_PER_JIFFY 3 + +#include <asm/m52xxacr.h> /* * Define the 523x SIM register set addresses. @@ -50,6 +54,13 @@ #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ +/* + * UART module. + */ +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x240 /* Base address of UART2 */ +#define MCFUART_BASE3 0x280 /* Base address of UART3 */ + #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 79b7b402f3c..4908b118f2f 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -11,6 +11,11 @@ #define m5249sim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m5249)" +#define CPU_INSTR_PER_JIFFY 3 + +#include <asm/m52xxacr.h> + /* * Define the 5249 SIM register set addresses. */ @@ -56,6 +61,11 @@ #define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ #define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ +/* + * UART module. + */ +#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ +#define MCFUART_BASE2 0x200 /* Base address of UART2 */ /* * Some symbol defines for the above... diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index df3332c2317..b7cc50abc83 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -12,6 +12,11 @@ #define m5272sim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m5272)" +#define CPU_INSTR_PER_JIFFY 3 + +#include <asm/m52xxacr.h> + /* * Define the 5272 SIM register set addresses. */ @@ -62,6 +67,9 @@ #define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ #define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ +#define MCFUART_BASE1 0x100 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ + #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ #define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ #define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 1feb46f108c..e8042e8bc00 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -11,6 +11,10 @@ #define m527xsim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m527x)" +#define CPU_INSTR_PER_JIFFY 3 + +#include <asm/m52xxacr.h> /* * Define the 5270/5271 SIM register set addresses. @@ -55,6 +59,12 @@ #define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ #endif +/* + * UART module. + */ +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x240 /* Base address of UART2 */ +#define MCFUART_BASE3 0x280 /* Base address of UART3 */ #ifdef CONFIG_M5271 #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index 891cbedad97..a6d2f4d9aaa 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -11,6 +11,10 @@ #define m528xsim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m528x)" +#define CPU_INSTR_PER_JIFFY 3 + +#include <asm/m52xxacr.h> /* * Define the 5280/5282 SIM register set addresses. @@ -42,6 +46,13 @@ #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ /* + * UART module. + */ +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x240 /* Base address of UART2 */ +#define MCFUART_BASE3 0x280 /* Base address of UART3 */ + +/* * GPIO registers */ #define MCFGPIO_PORTA (MCF_IPSBAR + 0x00100000) diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h new file mode 100644 index 00000000000..abc391a9ae8 --- /dev/null +++ b/arch/m68k/include/asm/m52xxacr.h @@ -0,0 +1,94 @@ +/****************************************************************************/ + +/* + * m52xxacr.h -- ColdFire version 2 core cache support + * + * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com> + */ + +/****************************************************************************/ +#ifndef m52xxacr_h +#define m52xxacr_h +/****************************************************************************/ + +/* + * All varients of the ColdFire using version 2 cores have a similar + * cache setup. Although not absolutely identical the cache register + * definitions are compatible for all of them. Mostly they support a + * configurable cache memory that can be instruction only, data only, + * or split instruction and data. The exception is the very old version 2 + * core based parts, like the 5206(e), 5249 and 5272, which are instruction + * cache only. Cache size varies from 2k up to 16k. + */ + +/* + * Define the Cache Control register flags. + */ +#define CACR_CENB 0x80000000 /* Enable cache */ +#define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */ +#define CACR_CFRZ 0x08000000 /* Cache freeze mode */ +#define CACR_CINV 0x01000000 /* Invalidate cache */ +#define CACR_DISI 0x00800000 /* Disable instruction cache */ +#define CACR_DISD 0x00400000 /* Disable data cache */ +#define CACR_INVI 0x00200000 /* Invalidate instruction cache */ +#define CACR_INVD 0x00100000 /* Invalidate data cache */ +#define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */ +#define CACR_DCM 0x00000200 /* Default cache mode */ +#define CACR_DBWE 0x00000100 /* Buffered write enable */ +#define CACR_DWP 0x00000020 /* Write protection */ +#define CACR_EUSP 0x00000010 /* Enable separate user a7 */ + +/* + * Define the Access Control register flags. + */ +#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */ +#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */ +#define ACR_ENABLE 0x00008000 /* Enable this ACR */ +#define ACR_USER 0x00000000 /* Allow only user accesses */ +#define ACR_SUPER 0x00002000 /* Allow supervisor access only */ +#define ACR_ANY 0x00004000 /* Allow any access type */ +#define ACR_CENB 0x00000000 /* Caching of region enabled */ +#define ACR_CDIS 0x00000040 /* Caching of region disabled */ +#define ACR_BWE 0x00000020 /* Write buffer enabled */ +#define ACR_WPROTECT 0x00000004 /* Write protect region */ + +/* + * Set the cache controller settings we will use. On the cores that support + * a split cache configuration we allow all the combinations at Kconfig + * time. For those cores that only have an instruction cache we just set + * that as on. + */ +#if defined(CONFIG_CACHE_I) +#define CACHE_TYPE (CACR_DISD + CACR_EUSP) +#define CACHE_INVTYPEI 0 +#elif defined(CONFIG_CACHE_D) +#define CACHE_TYPE (CACR_DISI + CACR_EUSP) +#define CACHE_INVTYPED 0 +#elif defined(CONFIG_CACHE_BOTH) +#define CACHE_TYPE CACR_EUSP +#define CACHE_INVTYPEI CACR_INVI +#define CACHE_INVTYPED CACR_INVD +#else +/* This is the instruction cache only devices (no split cache, no eusp) */ +#define CACHE_TYPE 0 +#define CACHE_INVTYPEI 0 +#endif + +#define CACHE_INIT (CACR_CINV + CACHE_TYPE) +#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM) + +#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) +#if defined(CACHE_INVTYPEI) +#define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI) +#endif +#if defined(CACHE_INVTYPED) +#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED) +#endif + +#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ + (0x000f0000) + \ + (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE)) +#define ACR1_MODE 0 + +/****************************************************************************/ +#endif /* m52xxsim_h */ diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index c6830e5b54c..0bf57397e7a 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -14,6 +14,11 @@ #define m5307sim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m5307)" +#define CPU_INSTR_PER_JIFFY 3 + +#include <asm/m53xxacr.h> + /* * Define the 5307 SIM register set addresses. */ @@ -94,6 +99,17 @@ #define MCFSIM_PADAT (MCF_MBAR + 0x248) /* + * UART module. + */ +#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ +#else +#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ +#define MCFUART_BASE2 0x200 /* Base address of UART2 */ +#endif + +/* * Generic GPIO support */ #define MCFGPIO_PIN_MAX 16 @@ -146,32 +162,5 @@ #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ -/* - * Define the Cache register flags. - */ -#define CACR_EC (1<<31) -#define CACR_ESB (1<<29) -#define CACR_DPI (1<<28) -#define CACR_HLCK (1<<27) -#define CACR_CINVA (1<<24) -#define CACR_DNFB (1<<10) -#define CACR_DCM_WTHRU (0<<8) -#define CACR_DCM_WBACK (1<<8) -#define CACR_DCM_OFF_PRE (2<<8) -#define CACR_DCM_OFF_IMP (3<<8) -#define CACR_DW (1<<5) - -#define ACR_BASE_POS 24 -#define ACR_MASK_POS 16 -#define ACR_ENABLE (1<<15) -#define ACR_USER (0<<13) -#define ACR_SUPER (1<<13) -#define ACR_ANY (2<<13) -#define ACR_CM_WTHRU (0<<5) -#define ACR_CM_WBACK (1<<5) -#define ACR_CM_OFF_PRE (2<<5) -#define ACR_CM_OFF_IMP (3<<5) -#define ACR_WPROTECT (1<<2) - /****************************************************************************/ #endif /* m5307sim_h */ diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index c4bf1c81e3c..e6470f8ca32 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -9,6 +9,11 @@ #define m532xsim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m532x)" +#define CPU_INSTR_PER_JIFFY 3 + +#include <asm/m53xxacr.h> + #define MCF_REG32(x) (*(volatile unsigned long *)(x)) #define MCF_REG16(x) (*(volatile unsigned short *)(x)) #define MCF_REG08(x) (*(volatile unsigned char *)(x)) @@ -74,31 +79,11 @@ #define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */ /* - * Define the Cache register flags. + * UART module. */ -#define CACR_EC (1<<31) -#define CACR_ESB (1<<29) -#define CACR_DPI (1<<28) -#define CACR_HLCK (1<<27) -#define CACR_CINVA (1<<24) -#define CACR_DNFB (1<<10) -#define CACR_DCM_WTHRU (0<<8) -#define CACR_DCM_WBACK (1<<8) -#define CACR_DCM_OFF_PRE (2<<8) -#define CACR_DCM_OFF_IMP (3<<8) -#define CACR_DW (1<<5) - -#define ACR_BASE_POS 24 -#define ACR_MASK_POS 16 -#define ACR_ENABLE (1<<15) -#define ACR_USER (0<<13) -#define ACR_SUPER (1<<13) -#define ACR_ANY (2<<13) -#define ACR_CM_WTHRU (0<<5) -#define ACR_CM_WBACK (1<<5) -#define ACR_CM_OFF_PRE (2<<5) -#define ACR_CM_OFF_IMP (3<<5) -#define ACR_WPROTECT (1<<2) +#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */ +#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ +#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */ /********************************************************************* * diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h new file mode 100644 index 00000000000..cd952b0a8bd --- /dev/null +++ b/arch/m68k/include/asm/m53xxacr.h @@ -0,0 +1,101 @@ +/****************************************************************************/ + +/* + * m53xxacr.h -- ColdFire version 3 core cache support + * + * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com> + */ + +/****************************************************************************/ +#ifndef m53xxacr_h +#define m53xxacr_h +/****************************************************************************/ + +/* + * All varients of the ColdFire using version 3 cores have a similar + * cache setup. They have a unified instruction and data cache, with + * configurable write-through or copy-back operation. + */ + +/* + * Define the Cache Control register flags. + */ +#define CACR_EC 0x80000000 /* Enable cache */ +#define CACR_ESB 0x20000000 /* Enable store buffer */ +#define CACR_DPI 0x10000000 /* Disable invalidation by CPUSHL */ +#define CACR_HLCK 0x08000000 /* Half cache lock mode */ +#define CACR_CINVA 0x01000000 /* Invalidate cache */ +#define CACR_DNFB 0x00000400 /* Inhibited fill buffer */ +#define CACR_DCM_WT 0x00000000 /* Cacheable write-through */ +#define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */ +#define CACR_DCM_PRE 0x00000200 /* Cache inhibited, precise */ +#define CACR_DCM_IMPRE 0x00000300 /* Cache inhibited, imprecise */ +#define CACR_WPROTECT 0x00000020 /* Write protect*/ +#define CACR_EUSP 0x00000010 /* Eanble separate user a7 */ + +/* + * Define the Access Control register flags. + */ +#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */ +#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */ +#define ACR_ENABLE 0x00008000 /* Enable this ACR */ +#define ACR_USER 0x00000000 /* Allow only user accesses */ +#define ACR_SUPER 0x00002000 /* Allow supervisor access only */ +#define ACR_ANY 0x00004000 /* Allow any access type */ +#define ACR_CM_WT 0x00000000 /* Cacheable, write-through */ +#define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */ +#define ACR_CM_PRE 0x00000040 /* Cache inhibited, precise */ +#define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */ +#define ACR_WPROTECT 0x00000004 /* Write protect region */ + +/* + * Define the cache type and arrangement (needed for pushes). + */ +#if defined(CONFIG_M5307) +#define CACHE_SIZE 0x2000 /* 8k of unified cache */ +#define ICACHE_SIZE CACHE_SIZE +#define DCACHE_SIZE CACHE_SIZE +#elif defined(CONFIG_M532x) +#define CACHE_SIZE 0x4000 /* 32k of unified cache */ +#define ICACHE_SIZE CACHE_SIZE +#define DCACHE_SIZE CACHE_SIZE +#endif + +#define CACHE_LINE_SIZE 16 /* 16 byte line size */ +#define CACHE_WAYS 4 /* 4 ways - set associative */ + +/* + * Set the cache controller settings we will use. This default in the + * CACR is cache inhibited, we use the ACR register to set cacheing + * enabled on the regions we want (eg RAM). + */ +#if defined(CONFIG_CACHE_COPYBACK) +#define CACHE_TYPE ACR_CM_CB +#define CACHE_PUSH +#else +#define CACHE_TYPE ACR_CM_WT +#endif + +#ifdef CONFIG_COLDFIRE_SW_A7 +#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE) +#else +#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP) +#endif + +/* + * Unified cache means we will never need to flush for coherency of + * instruction fetch. We will need to flush to maintain memory/DMA + * coherency though in all cases. And for copyback caches we will need + * to push cached data as well. + */ +#define CACHE_INIT CACR_CINVA +#define CACHE_INVALIDATE CACR_CINVA +#define CACHE_INVALIDATED CACR_CINVA + +#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ + (0x000f0000) + \ + (ACR_ENABLE + ACR_ANY + CACHE_TYPE)) +#define ACR1_MODE 0 + +/****************************************************************************/ +#endif /* m53xxsim_h */ diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index c399abbf953..75f5c28a551 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -14,6 +14,11 @@ #define m5407sim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m5407)" +#define CPU_INSTR_PER_JIFFY 3 + +#include <asm/m54xxacr.h> + /* * Define the 5407 SIM register set addresses. */ @@ -73,6 +78,9 @@ #define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ #define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ +#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ +#define MCFUART_BASE2 0x200 /* Base address of UART2 */ + #define MCFSIM_PADDR (MCF_MBAR + 0x244) #define MCFSIM_PADAT (MCF_MBAR + 0x248) @@ -117,39 +125,5 @@ #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ -/* - * Define the Cache register flags. - */ -#define CACR_DEC 0x80000000 /* Enable data cache */ -#define CACR_DWP 0x40000000 /* Data write protection */ -#define CACR_DESB 0x20000000 /* Enable data store buffer */ -#define CACR_DDPI 0x10000000 /* Disable CPUSHL */ -#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ -#define CACR_DDCM_WT 0x00000000 /* Write through cache*/ -#define CACR_DDCM_CP 0x02000000 /* Copyback cache */ -#define CACR_DDCM_P 0x04000000 /* No cache, precise */ -#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ -#define CACR_DCINVA 0x01000000 /* Invalidate data cache */ -#define CACR_BEC 0x00080000 /* Enable branch cache */ -#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ -#define CACR_IEC 0x00008000 /* Enable instruction cache */ -#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ -#define CACR_IDPI 0x00001000 /* Disable CPUSHL */ -#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ -#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ -#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ - -#define ACR_BASE_POS 24 /* Address Base */ -#define ACR_MASK_POS 16 /* Address Mask */ -#define ACR_ENABLE 0x00008000 /* Enable address */ -#define ACR_USER 0x00000000 /* User mode access only */ -#define ACR_SUPER 0x00002000 /* Supervisor mode only */ -#define ACR_ANY 0x00004000 /* Match any access mode */ -#define ACR_CM_WT 0x00000000 /* Write through mode */ -#define ACR_CM_CP 0x00000020 /* Copyback mode */ -#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ -#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ -#define ACR_WPROTECT 0x00000004 /* Write protect */ - /****************************************************************************/ #endif /* m5407sim_h */ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h new file mode 100644 index 00000000000..16a1835f9b2 --- /dev/null +++ b/arch/m68k/include/asm/m54xxacr.h @@ -0,0 +1,97 @@ +/* + * Bit definitions for the MCF54xx ACR and CACR registers. + */ + +#ifndef m54xxacr_h +#define m54xxacr_h + +/* + * Define the Cache register flags. + */ +#define CACR_DEC 0x80000000 /* Enable data cache */ +#define CACR_DWP 0x40000000 /* Data write protection */ +#define CACR_DESB 0x20000000 /* Enable data store buffer */ +#define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */ +#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ +#define CACR_DDCM_WT 0x00000000 /* Write through cache*/ +#define CACR_DDCM_CP 0x02000000 /* Copyback cache */ +#define CACR_DDCM_P 0x04000000 /* No cache, precise */ +#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ +#define CACR_DCINVA 0x01000000 /* Invalidate data cache */ +#define CACR_BEC 0x00080000 /* Enable branch cache */ +#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ +#define CACR_IEC 0x00008000 /* Enable instruction cache */ +#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ +#define CACR_IDPI 0x00001000 /* Disable CPUSHL */ +#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ +#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ +#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ +#define CACR_EUSP 0x00000020 /* Enable separate user a7 */ + +#define ACR_BASE_POS 24 /* Address Base */ +#define ACR_MASK_POS 16 /* Address Mask */ +#define ACR_ENABLE 0x00008000 /* Enable address */ +#define ACR_USER 0x00000000 /* User mode access only */ +#define ACR_SUPER 0x00002000 /* Supervisor mode only */ +#define ACR_ANY 0x00004000 /* Match any access mode */ +#define ACR_CM_WT 0x00000000 /* Write through mode */ +#define ACR_CM_CP 0x00000020 /* Copyback mode */ +#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ +#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ +#define ACR_CM 0x00000060 /* Cache mode mask */ +#define ACR_WPROTECT 0x00000004 /* Write protect */ + +#if defined(CONFIG_M5407) + +#define ICACHE_SIZE 0x4000 /* instruction - 16k */ +#define DCACHE_SIZE 0x2000 /* data - 8k */ + +#elif defined(CONFIG_M54xx) + +#define ICACHE_SIZE 0x8000 /* instruction - 32k */ +#define DCACHE_SIZE 0x8000 /* data - 32k */ + +#endif + +#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ +#define CACHE_WAYS 4 /* 4 ways */ + +/* + * Version 4 cores have a true harvard style separate instruction + * and data cache. Enable data and instruction caches, also enable write + * buffers and branch accelerator. + */ +/* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */ +/* use '+' instead of '|' for assembler's sake */ + + /* Enable data cache */ + /* Enable data store buffer */ + /* outside ACRs : No cache, precise */ + /* Enable instruction+branch caches */ +#if defined(CONFIG_M5407) +#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC) +#else +#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) +#endif +#if defined(CONFIG_CACHE_COPYBACK) +#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP) +#else +#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) +#endif +#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) + +#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA) +#define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) +#define ACR1_MODE 0 +#define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) +#define ACR3_MODE 0 + +#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) +/* Copyback cache mode must push dirty cache lines first */ +#define CACHE_PUSH +#endif + +#endif /* m54xxacr_h */ diff --git a/arch/m68k/include/asm/m548xgpt.h b/arch/m68k/include/asm/m54xxgpt.h index 33b2eef90f0..df75dd87ae7 100644 --- a/arch/m68k/include/asm/m548xgpt.h +++ b/arch/m68k/include/asm/m54xxgpt.h @@ -1,13 +1,13 @@ /* - * File: m548xgpt.h - * Purpose: Register and bit definitions for the MCF548X + * File: m54xxgpt.h + * Purpose: Register and bit definitions for the MCF54XX * * Notes: * */ -#ifndef m548xgpt_h -#define m548xgpt_h +#ifndef m54xxgpt_h +#define m54xxgpt_h /********************************************************************* * @@ -87,4 +87,4 @@ /********************************************************************/ -#endif /* m548xgpt_h */ +#endif /* m54xxgpt_h */ diff --git a/arch/m68k/include/asm/m548xsim.h b/arch/m68k/include/asm/m54xxsim.h index 149135ef30d..462ae532844 100644 --- a/arch/m68k/include/asm/m548xsim.h +++ b/arch/m68k/include/asm/m54xxsim.h @@ -1,11 +1,16 @@ /* - * m548xsim.h -- ColdFire 547x/548x System Integration Unit support. + * m54xxsim.h -- ColdFire 547x/548x System Integration Unit support. */ -#ifndef m548xsim_h -#define m548xsim_h +#ifndef m54xxsim_h +#define m54xxsim_h -#define MCFINT_VECBASE 64 +#define CPU_NAME "COLDFIRE(m54xx)" +#define CPU_INSTR_PER_JIFFY 2 + +#include <asm/m54xxacr.h> + +#define MCFINT_VECBASE 64 /* * Interrupt Controller Registers @@ -22,6 +27,14 @@ #define MCFINTC_ICR0 0x40 /* Base ICR register */ /* + * UART module. + */ +#define MCFUART_BASE1 0x8600 /* Base address of UART1 */ +#define MCFUART_BASE2 0x8700 /* Base address of UART2 */ +#define MCFUART_BASE3 0x8800 /* Base address of UART3 */ +#define MCFUART_BASE4 0x8900 /* Base address of UART4 */ + +/* * Define system peripheral IRQ usage. */ #define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */ @@ -52,4 +65,4 @@ #define MCF_PAR_PSC_RTS_RTS (0x30) #define MCF_PAR_PSC_CANRX (0x40) -#endif /* m548xsim_h */ +#endif /* m54xxsim_h */ diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h deleted file mode 100644 index f49dfc09f70..00000000000 --- a/arch/m68k/include/asm/mcfcache.h +++ /dev/null @@ -1,150 +0,0 @@ -/****************************************************************************/ - -/* - * mcfcache.h -- ColdFire CPU cache support code - * - * (C) Copyright 2004, Greg Ungerer <gerg@snapgear.com> - */ - -/****************************************************************************/ -#ifndef __M68KNOMMU_MCFCACHE_H -#define __M68KNOMMU_MCFCACHE_H -/****************************************************************************/ - - -/* - * The different ColdFire families have different cache arrangments. - * Everything from a small instruction only cache, to configurable - * data and/or instruction cache, to unified instruction/data, to - * harvard style separate instruction and data caches. - */ - -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272) -/* - * Simple version 2 core cache. These have instruction cache only, - * we just need to invalidate it and enable it. - */ -.macro CACHE_ENABLE - movel #0x01000000,%d0 /* invalidate cache cmd */ - movec %d0,%CACR /* do invalidate cache */ - movel #0x80000100,%d0 /* setup cache mask */ - movec %d0,%CACR /* enable cache */ -.endm -#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ - -#if defined(CONFIG_M523x) || defined(CONFIG_M527x) -/* - * New version 2 cores have a configurable split cache arrangement. - * For now I am just enabling instruction cache - but ultimately I - * think a split instruction/data cache would be better. - */ -.macro CACHE_ENABLE - movel #0x01400000,%d0 - movec %d0,%CACR /* invalidate cache */ - nop - movel #0x0000c000,%d0 /* set SDRAM cached only */ - movec %d0,%ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - movel #0x80400100,%d0 /* configure cache */ - movec %d0,%CACR /* enable cache */ - nop -.endm -#endif /* CONFIG_M523x || CONFIG_M527x */ - -#if defined(CONFIG_M528x) -.macro CACHE_ENABLE - nop - movel #0x01000000, %d0 - movec %d0, %CACR /* Invalidate cache */ - nop - movel #0x0000c020, %d0 /* Set SDRAM cached only */ - movec %d0, %ACR0 - movel #0x00000000, %d0 /* No other regions cached */ - movec %d0, %ACR1 - movel #0x80000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop -.endm -#endif /* CONFIG_M528x */ - -#if defined(CONFIG_M5249) || defined(CONFIG_M5307) -/* - * The version 3 core cache. Oddly enough the version 2 core 5249 - * has the same SDRAM and cache setup as the version 3 cores. - * This is a single unified instruction/data cache. - */ -.macro CACHE_ENABLE - movel #0x01000000,%d0 /* invalidate whole cache */ - movec %d0,%CACR - nop -#if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3) - movel #0x0000c000,%d0 /* set SDRAM cached (write-thru) */ -#else - movel #0x0000c020,%d0 /* set SDRAM cached (copyback) */ -#endif - movec %d0,%ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - movel #0xa0000200,%d0 /* enable cache */ - movec %d0,%CACR - nop -.endm -#endif /* CONFIG_M5249 || CONFIG_M5307 */ - -#if defined(CONFIG_M532x) -.macro CACHE_ENABLE - movel #0x01000000,%d0 /* invalidate cache cmd */ - movec %d0,%CACR /* do invalidate cache */ - nop - movel #0x4001C000,%d0 /* set SDRAM cached (write-thru) */ - movec %d0,%ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - movel #0x80000200,%d0 /* setup cache mask */ - movec %d0,%CACR /* enable cache */ - nop -.endm -#endif /* CONFIG_M532x */ - -#if defined(CONFIG_M5407) || defined(CONFIG_M548x) -/* - * Version 4 cores have a true harvard style separate instruction - * and data cache. Invalidate and enable cache, also enable write - * buffers and branch accelerator. - */ -.macro CACHE_ENABLE - movel #0x01040100,%d0 /* invalidate whole cache */ - movec %d0,%CACR - nop - movel #0x000fc000,%d0 /* set SDRAM cached only */ - movec %d0, %ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0, %ACR1 - movel #0x000fc000,%d0 /* set SDRAM cached only */ - movec %d0, %ACR2 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0, %ACR3 - movel #0xb6088400,%d0 /* enable caches */ - movec %d0,%CACR - nop -.endm -#endif /* CONFIG_M5407 */ - -#if defined(CONFIG_M520x) -.macro CACHE_ENABLE - move.l #0x01000000,%d0 /* invalidate whole cache */ - movec %d0,%CACR - nop - move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */ - movec %d0,%ACR0 - move.l #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - move.l #0x80400000,%d0 /* enable 8K instruction cache */ - movec %d0,%CACR - nop -.endm -#endif /* CONFIG_M520x */ - -/****************************************************************************/ -#endif /* __M68KNOMMU_MCFCACHE_H */ diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h index 6901fd68165..ebd0304054a 100644 --- a/arch/m68k/include/asm/mcfsim.h +++ b/arch/m68k/include/asm/mcfsim.h @@ -41,8 +41,8 @@ #elif defined(CONFIG_M5407) #include <asm/m5407sim.h> #include <asm/mcfintc.h> -#elif defined(CONFIG_M548x) -#include <asm/m548xsim.h> +#elif defined(CONFIG_M54xx) +#include <asm/m54xxsim.h> #endif /****************************************************************************/ diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h index db72e2b889c..2abedff0a69 100644 --- a/arch/m68k/include/asm/mcfuart.h +++ b/arch/m68k/include/asm/mcfuart.h @@ -12,49 +12,6 @@ #define mcfuart_h /****************************************************************************/ -/* - * Define the base address of the UARTS within the MBAR address - * space. - */ -#if defined(CONFIG_M5272) -#define MCFUART_BASE1 0x100 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ -#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#if defined(CONFIG_NETtel) -#define MCFUART_BASE1 0x180 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ -#else -#define MCFUART_BASE1 0x140 /* Base address of UART1 */ -#define MCFUART_BASE2 0x180 /* Base address of UART2 */ -#endif -#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x240 /* Base address of UART2 */ -#define MCFUART_BASE3 0x280 /* Base address of UART3 */ -#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ -#else -#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ -#define MCFUART_BASE2 0x200 /* Base address of UART2 */ -#endif -#elif defined(CONFIG_M520x) -#define MCFUART_BASE1 0x60000 /* Base address of UART1 */ -#define MCFUART_BASE2 0x64000 /* Base address of UART2 */ -#define MCFUART_BASE3 0x68000 /* Base address of UART2 */ -#elif defined(CONFIG_M532x) -#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ -#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ -#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ -#elif defined(CONFIG_M548x) -#define MCFUART_BASE1 0x8600 /* on M548x */ -#define MCFUART_BASE2 0x8700 /* on M548x */ -#define MCFUART_BASE3 0x8800 /* on M548x */ -#define MCFUART_BASE4 0x8900 /* on M548x */ -#endif - - #include <linux/serial_core.h> #include <linux/platform_device.h> @@ -217,7 +174,7 @@ struct mcf_platform_uart { #define MCFUART_URF_RXS 0xc0 /* Receiver status */ #endif -#if defined(CONFIG_M548x) +#if defined(CONFIG_M54xx) #define MCFUART_TXFIFOSIZE 512 #elif defined(CONFIG_M5272) #define MCFUART_TXFIFOSIZE 25 diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h index 7a6a7590cc0..278c69bad57 100644 --- a/arch/m68k/include/asm/processor.h +++ b/arch/m68k/include/asm/processor.h @@ -20,23 +20,26 @@ static inline unsigned long rdusp(void) { -#ifdef CONFIG_COLDFIRE +#ifdef CONFIG_COLDFIRE_SW_A7 extern unsigned int sw_usp; return sw_usp; #else - unsigned long usp; - __asm__ __volatile__("move %/usp,%0" : "=a" (usp)); + register unsigned long usp __asm__("a0"); + /* move %usp,%a0 */ + __asm__ __volatile__(".word 0x4e68" : "=a" (usp)); return usp; #endif } static inline void wrusp(unsigned long usp) { -#ifdef CONFIG_COLDFIRE +#ifdef CONFIG_COLDFIRE_SW_A7 extern unsigned int sw_usp; sw_usp = usp; #else - __asm__ __volatile__("move %0,%/usp" : : "a" (usp)); + register unsigned long a0 __asm__("a0") = usp; + /* move %a0,%usp */ + __asm__ __volatile__(".word 0x4e60" : : "a" (a0) ); #endif } diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index fa9f746cf4a..8b9dacaa0f6 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -2,6 +2,7 @@ config M68K bool default y select HAVE_IDE + select HAVE_GENERIC_HARDIRQS config MMU bool @@ -48,14 +49,6 @@ config GENERIC_HWEIGHT bool default y -config GENERIC_HARDIRQS - bool - default y - -config GENERIC_HARDIRQS_NO__DO_IRQ - bool - default y - config GENERIC_CALIBRATE_DELAY bool default y @@ -75,6 +68,16 @@ config GENERIC_CLOCKEVENTS config NO_IOPORT def_bool y +config COLDFIRE_SW_A7 + bool + default n + +config HAVE_CACHE_SPLIT + bool + +config HAVE_CACHE_CB + bool + source "init/Kconfig" source "kernel/Kconfig.freezer" @@ -107,69 +110,90 @@ config M68360 config M5206 bool "MCF5206" + select COLDFIRE_SW_A7 help Motorola ColdFire 5206 processor support. config M5206e bool "MCF5206e" + select COLDFIRE_SW_A7 help Motorola ColdFire 5206e processor support. config M520x bool "MCF520x" select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT help Freescale Coldfire 5207/5208 processor support. config M523x bool "MCF523x" select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT help Freescale Coldfire 5230/1/2/4/5 processor support config M5249 bool "MCF5249" + select COLDFIRE_SW_A7 help Motorola ColdFire 5249 processor support. config M5271 bool "MCF5271" + select HAVE_CACHE_SPLIT help Freescale (Motorola) ColdFire 5270/5271 processor support. config M5272 bool "MCF5272" + select COLDFIRE_SW_A7 help Motorola ColdFire 5272 processor support. config M5275 bool "MCF5275" + select HAVE_CACHE_SPLIT help Freescale (Motorola) ColdFire 5274/5275 processor support. config M528x bool "MCF528x" select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT help Motorola ColdFire 5280/5282 processor support. config M5307 bool "MCF5307" + select COLDFIRE_SW_A7 + select HAVE_CACHE_CB help Motorola ColdFire 5307 processor support. config M532x bool "MCF532x" + select HAVE_CACHE_CB help Freescale (Motorola) ColdFire 532x processor support. config M5407 bool "MCF5407" + select COLDFIRE_SW_A7 + select HAVE_CACHE_CB help Motorola ColdFire 5407 processor support. +config M547x + bool "MCF547x" + select HAVE_CACHE_CB + help + Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support. + config M548x bool "MCF548x" + select HAVE_CACHE_CB help Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support. @@ -181,9 +205,14 @@ config M527x select GENERIC_CLOCKEVENTS default y +config M54xx + bool + depends on (M548x || M547x) + default y + config COLDFIRE bool - depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M548x) + depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M54xx) select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB default y @@ -230,6 +259,46 @@ config OLDMASK Build support for the older revision ColdFire 5307 silicon. Specifically this is the 1H55J mask revision. +if HAVE_CACHE_SPLIT +choice + prompt "Split Cache Configuration" + default CACHE_I + +config CACHE_I + bool "Instruction" + help + Use all of the ColdFire CPU cache memory as an instruction cache. + +config CACHE_D + bool "Data" + help + Use all of the ColdFire CPU cache memory as a data cache. + +config CACHE_BOTH + bool "Both" + help + Split the ColdFire CPU cache, and use half as an instruction cache + and half as a data cache. +endchoice +endif + +if HAVE_CACHE_CB +choice + prompt "Data cache mode" + default CACHE_WRITETHRU + +config CACHE_WRITETHRU + bool "Write-through" + help + The ColdFire CPU cache is set into Write-through mode. + +config CACHE_COPYBACK + bool "Copy-back" + help + The ColdFire CPU cache is set into Copy-back mode. +endchoice +endif + comment "Platform" config PILOT3 @@ -245,16 +314,16 @@ config XCOPILOT_BUGS Support the bugs of Xcopilot. config UC5272 - bool 'Arcturus Networks uC5272 dimm board support' - depends on M5272 - help - Support for the Arcturus Networks uC5272 dimm board. + bool 'Arcturus Networks uC5272 dimm board support' + depends on M5272 + help + Support for the Arcturus Networks uC5272 dimm board. config UC5282 - bool "Arcturus Networks uC5282 board support" - depends on M528x - help - Support for the Arcturus Networks uC5282 dimm board. + bool "Arcturus Networks uC5282 board support" + depends on M528x + help + Support for the Arcturus Networks uC5282 dimm board. config UCSIMM bool "uCsimm module support" @@ -279,7 +348,7 @@ config DIRECT_IO_ACCESS depends on (UCSIMM || UCDIMM || DRAGEN2) help Disable the CPU internal registers protection in user mode, - to allow a user application to read/write them. + to allow a user application to read/write them. config INIT_LCD bool "Initialize LCD" @@ -517,7 +586,7 @@ config EMAC_INC depends on (SOM5282EM) config SNEHA - bool + bool default y depends on CPU16B diff --git a/arch/m68knommu/Makefile b/arch/m68knommu/Makefile index 026ef16fa68..589613fed31 100644 --- a/arch/m68knommu/Makefile +++ b/arch/m68knommu/Makefile @@ -25,7 +25,7 @@ platform-$(CONFIG_M528x) := 528x platform-$(CONFIG_M5307) := 5307 platform-$(CONFIG_M532x) := 532x platform-$(CONFIG_M5407) := 5407 -platform-$(CONFIG_M548x) := 548x +platform-$(CONFIG_M54xx) := 54xx PLATFORM := $(platform-y) board-$(CONFIG_PILOT) := pilot @@ -74,7 +74,7 @@ cpuclass-$(CONFIG_M528x) := coldfire cpuclass-$(CONFIG_M5307) := coldfire cpuclass-$(CONFIG_M532x) := coldfire cpuclass-$(CONFIG_M5407) := coldfire -cpuclass-$(CONFIG_M548x) := coldfire +cpuclass-$(CONFIG_M54xx) := coldfire cpuclass-$(CONFIG_M68328) := 68328 cpuclass-$(CONFIG_M68EZ328) := 68328 cpuclass-$(CONFIG_M68VZ328) := 68328 @@ -91,18 +91,18 @@ export PLATFORM BOARD MODEL CPUCLASS # Some CFLAG additions based on specific CPU type. # cflags-$(CONFIG_M5206) := $(call cc-option,-mcpu=5206,-m5200) -cflags-$(CONFIG_M5206e) := $(call cc-option,-m5206e,-m5200) +cflags-$(CONFIG_M5206e) := $(call cc-option,-mcpu=5206e,-m5200) cflags-$(CONFIG_M520x) := $(call cc-option,-mcpu=5208,-m5200) cflags-$(CONFIG_M523x) := $(call cc-option,-mcpu=523x,-m5307) cflags-$(CONFIG_M5249) := $(call cc-option,-mcpu=5249,-m5200) cflags-$(CONFIG_M5271) := $(call cc-option,-mcpu=5271,-m5307) cflags-$(CONFIG_M5272) := $(call cc-option,-mcpu=5272,-m5307) cflags-$(CONFIG_M5275) := $(call cc-option,-mcpu=5275,-m5307) -cflags-$(CONFIG_M528x) := $(call cc-option,-m528x,-m5307) -cflags-$(CONFIG_M5307) := $(call cc-option,-m5307,-m5200) +cflags-$(CONFIG_M528x) := $(call cc-option,-mcpu=528x,-m5307) +cflags-$(CONFIG_M5307) := $(call cc-option,-mcpu=5307,-m5200) cflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307) -cflags-$(CONFIG_M5407) := $(call cc-option,-m5407,-m5200) -cflags-$(CONFIG_M548x) := $(call cc-option,-m5407,-m5200) +cflags-$(CONFIG_M5407) := $(call cc-option,-mcpu=5407,-m5200) +cflags-$(CONFIG_M54xx) := $(call cc-option,-mcpu=5475,-m5200) cflags-$(CONFIG_M68328) := -m68000 cflags-$(CONFIG_M68EZ328) := -m68000 cflags-$(CONFIG_M68VZ328) := -m68000 diff --git a/arch/m68knommu/configs/m5208evb_defconfig b/arch/m68knommu/configs/m5208evb_defconfig index 6ac2981a2cd..2f5655c577a 100644 --- a/arch/m68knommu/configs/m5208evb_defconfig +++ b/arch/m68knommu/configs/m5208evb_defconfig @@ -1,7 +1,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_FUTEX is not set diff --git a/arch/m68knommu/configs/m5249evb_defconfig b/arch/m68knommu/configs/m5249evb_defconfig index 14934ff8d5c..16df72bfbd4 100644 --- a/arch/m68knommu/configs/m5249evb_defconfig +++ b/arch/m68knommu/configs/m5249evb_defconfig @@ -1,7 +1,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_FUTEX is not set diff --git a/arch/m68knommu/configs/m5272c3_defconfig b/arch/m68knommu/configs/m5272c3_defconfig index 5985a3b593d..4e6ea50c7f3 100644 --- a/arch/m68knommu/configs/m5272c3_defconfig +++ b/arch/m68knommu/configs/m5272c3_defconfig @@ -1,7 +1,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_FUTEX is not set diff --git a/arch/m68knommu/configs/m5275evb_defconfig b/arch/m68knommu/configs/m5275evb_defconfig index 5a7857efb45..f3dd74115a3 100644 --- a/arch/m68knommu/configs/m5275evb_defconfig +++ b/arch/m68knommu/configs/m5275evb_defconfig @@ -1,7 +1,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_FUTEX is not set diff --git a/arch/m68knommu/configs/m5307c3_defconfig b/arch/m68knommu/configs/m5307c3_defconfig index e8102018c8d..bce0a20c373 100644 --- a/arch/m68knommu/configs/m5307c3_defconfig +++ b/arch/m68knommu/configs/m5307c3_defconfig @@ -1,7 +1,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_FUTEX is not set diff --git a/arch/m68knommu/configs/m5407c3_defconfig b/arch/m68knommu/configs/m5407c3_defconfig index 5c124a7ba2a..618cc32691f 100644 --- a/arch/m68knommu/configs/m5407c3_defconfig +++ b/arch/m68knommu/configs/m5407c3_defconfig @@ -1,7 +1,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_FUTEX is not set diff --git a/arch/m68knommu/defconfig b/arch/m68knommu/defconfig index 6ac2981a2cd..2f5655c577a 100644 --- a/arch/m68knommu/defconfig +++ b/arch/m68knommu/defconfig @@ -1,7 +1,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_FUTEX is not set diff --git a/arch/m68knommu/kernel/setup.c b/arch/m68knommu/kernel/setup.c index c684adf5dc4..16b2de7f510 100644 --- a/arch/m68knommu/kernel/setup.c +++ b/arch/m68knommu/kernel/setup.c @@ -55,55 +55,29 @@ void (*mach_halt)(void); void (*mach_power_off)(void); #ifdef CONFIG_M68328 - #define CPU "MC68328" +#define CPU_NAME "MC68328" #endif #ifdef CONFIG_M68EZ328 - #define CPU "MC68EZ328" +#define CPU_NAME "MC68EZ328" #endif #ifdef CONFIG_M68VZ328 - #define CPU "MC68VZ328" +#define CPU_NAME "MC68VZ328" #endif #ifdef CONFIG_M68360 - #define CPU "MC68360" +#define CPU_NAME "MC68360" #endif -#if defined(CONFIG_M5206) - #define CPU "COLDFIRE(m5206)" +#ifndef CPU_NAME +#define CPU_NAME "UNKNOWN" #endif -#if defined(CONFIG_M5206e) - #define CPU "COLDFIRE(m5206e)" -#endif -#if defined(CONFIG_M520x) - #define CPU "COLDFIRE(m520x)" -#endif -#if defined(CONFIG_M523x) - #define CPU "COLDFIRE(m523x)" -#endif -#if defined(CONFIG_M5249) - #define CPU "COLDFIRE(m5249)" -#endif -#if defined(CONFIG_M5271) - #define CPU "COLDFIRE(m5270/5271)" -#endif -#if defined(CONFIG_M5272) - #define CPU "COLDFIRE(m5272)" -#endif -#if defined(CONFIG_M5275) - #define CPU "COLDFIRE(m5274/5275)" -#endif -#if defined(CONFIG_M528x) - #define CPU "COLDFIRE(m5280/5282)" -#endif -#if defined(CONFIG_M5307) - #define CPU "COLDFIRE(m5307)" -#endif -#if defined(CONFIG_M532x) - #define CPU "COLDFIRE(m532x)" -#endif -#if defined(CONFIG_M5407) - #define CPU "COLDFIRE(m5407)" -#endif -#ifndef CPU - #define CPU "UNKNOWN" + +/* + * Different cores have different instruction execution timings. + * The old/traditional 68000 cores are basically all the same, at 16. + * The ColdFire cores vary a little, their values are defined in their + * headers. We default to the standard 68000 value here. + */ +#ifndef CPU_INSTR_PER_JIFFY +#define CPU_INSTR_PER_JIFFY 16 #endif extern int _stext, _etext, _sdata, _edata, _sbss, _ebss, _end; @@ -208,7 +182,7 @@ void __init setup_arch(char **cmdline_p) command_line[sizeof(command_line) - 1] = 0; #endif /* CONFIG_UBOOT */ - printk(KERN_INFO "\x0F\r\n\nuClinux/" CPU "\n"); + printk(KERN_INFO "\x0F\r\n\nuClinux/" CPU_NAME "\n"); #ifdef CONFIG_UCDIMM printk(KERN_INFO "uCdimm by Lineo, Inc. <www.lineo.com>\n"); @@ -257,11 +231,6 @@ void __init setup_arch(char **cmdline_p) memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); boot_command_line[COMMAND_LINE_SIZE-1] = 0; -#ifdef DEBUG - if (strlen(*cmdline_p)) - printk(KERN_DEBUG "Command line: '%s'\n", *cmdline_p); -#endif - #if defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_DUMMY_CONSOLE) conswitchp = &dummy_con; #endif @@ -303,15 +272,10 @@ static int show_cpuinfo(struct seq_file *m, void *v) char *cpu, *mmu, *fpu; u_long clockfreq; - cpu = CPU; + cpu = CPU_NAME; mmu = "none"; fpu = "none"; - -#ifdef CONFIG_COLDFIRE - clockfreq = (loops_per_jiffy * HZ) * 3; -#else - clockfreq = (loops_per_jiffy * HZ) * 16; -#endif + clockfreq = (loops_per_jiffy * HZ) * CPU_INSTR_PER_JIFFY; seq_printf(m, "CPU:\t\t%s\n" "MMU:\t\t%s\n" diff --git a/arch/m68knommu/mm/Makefile b/arch/m68knommu/mm/Makefile index fc91f254f51..b54ab6b4b52 100644 --- a/arch/m68knommu/mm/Makefile +++ b/arch/m68knommu/mm/Makefile @@ -2,4 +2,4 @@ # Makefile for the linux m68knommu specific parts of the memory manager. # -obj-y += init.o fault.o memory.o kmap.o +obj-y += init.o kmap.o diff --git a/arch/m68knommu/mm/fault.c b/arch/m68knommu/mm/fault.c deleted file mode 100644 index bc05cf74d9c..00000000000 --- a/arch/m68knommu/mm/fault.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * linux/arch/m68knommu/mm/fault.c - * - * Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>, - * Copyright (C) 2000 Lineo, Inc. (www.lineo.com) - * - * Based on: - * - * linux/arch/m68k/mm/fault.c - * - * Copyright (C) 1995 Hamish Macdonald - */ - -#include <linux/mman.h> -#include <linux/mm.h> -#include <linux/kernel.h> -#include <linux/ptrace.h> - -#include <asm/system.h> -#include <asm/pgtable.h> - -extern void die_if_kernel(char *, struct pt_regs *, long); - -/* - * This routine handles page faults. It determines the problem, and - * then passes it off to one of the appropriate routines. - * - * error_code: - * bit 0 == 0 means no page found, 1 means protection fault - * bit 1 == 0 means read, 1 means write - * - * If this routine detects a bad access, it returns 1, otherwise it - * returns 0. - */ -asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address, - unsigned long error_code) -{ -#ifdef DEBUG - printk(KERN_DEBUG "regs->sr=%#x, regs->pc=%#lx, address=%#lx, %ld\n", - regs->sr, regs->pc, address, error_code); -#endif - - /* - * Oops. The kernel tried to access some bad page. We'll have to - * terminate things with extreme prejudice. - */ - if ((unsigned long) address < PAGE_SIZE) - printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference"); - else - printk(KERN_ALERT "Unable to handle kernel access"); - printk(KERN_ALERT " at virtual address %08lx\n", address); - die_if_kernel("Oops", regs, error_code); - do_exit(SIGKILL); - - return 1; -} - diff --git a/arch/m68knommu/mm/kmap.c b/arch/m68knommu/mm/kmap.c index 902c1dfda9e..ece8d5ad4e6 100644 --- a/arch/m68knommu/mm/kmap.c +++ b/arch/m68knommu/mm/kmap.c @@ -36,15 +36,6 @@ void iounmap(void *addr) } /* - * __iounmap unmaps nearly everything, so be careful - * it doesn't free currently pointer/page tables anymore but it - * wans't used anyway and might be added later. - */ -void __iounmap(void *addr, unsigned long size) -{ -} - -/* * Set new cache mode for some kernel address space. * The caller must push data for that range itself, if such data may already * be in the cache. diff --git a/arch/m68knommu/mm/memory.c b/arch/m68knommu/mm/memory.c deleted file mode 100644 index 8f7949e786d..00000000000 --- a/arch/m68knommu/mm/memory.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * linux/arch/m68knommu/mm/memory.c - * - * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>, - * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) - * - * Based on: - * - * linux/arch/m68k/mm/memory.c - * - * Copyright (C) 1995 Hamish Macdonald - */ - -#include <linux/mm.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/types.h> - -#include <asm/segment.h> -#include <asm/page.h> -#include <asm/pgtable.h> -#include <asm/system.h> - -/* - * Map some physical address range into the kernel address space. - */ - -unsigned long kernel_map(unsigned long paddr, unsigned long size, - int nocacheflag, unsigned long *memavailp ) -{ - return paddr; -} - diff --git a/arch/m68knommu/platform/548x/Makefile b/arch/m68knommu/platform/54xx/Makefile index e6035e7a2d3..e6035e7a2d3 100644 --- a/arch/m68knommu/platform/548x/Makefile +++ b/arch/m68knommu/platform/54xx/Makefile diff --git a/arch/m68knommu/platform/548x/config.c b/arch/m68knommu/platform/54xx/config.c index 9888846bd1c..78130984db9 100644 --- a/arch/m68knommu/platform/548x/config.c +++ b/arch/m68knommu/platform/54xx/config.c @@ -1,7 +1,7 @@ /***************************************************************************/ /* - * linux/arch/m68knommu/platform/548x/config.c + * linux/arch/m68knommu/platform/54xx/config.c * * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be> */ @@ -15,13 +15,13 @@ #include <linux/io.h> #include <asm/machdep.h> #include <asm/coldfire.h> -#include <asm/m548xsim.h> +#include <asm/m54xxsim.h> #include <asm/mcfuart.h> -#include <asm/m548xgpt.h> +#include <asm/m54xxgpt.h> /***************************************************************************/ -static struct mcf_platform_uart m548x_uart_platform[] = { +static struct mcf_platform_uart m54xx_uart_platform[] = { { .mapbase = MCF_MBAR + MCFUART_BASE1, .irq = 64 + 35, @@ -40,20 +40,20 @@ static struct mcf_platform_uart m548x_uart_platform[] = { }, }; -static struct platform_device m548x_uart = { +static struct platform_device m54xx_uart = { .name = "mcfuart", .id = 0, - .dev.platform_data = m548x_uart_platform, + .dev.platform_data = m54xx_uart_platform, }; -static struct platform_device *m548x_devices[] __initdata = { - &m548x_uart, +static struct platform_device *m54xx_devices[] __initdata = { + &m54xx_uart, }; /***************************************************************************/ -static void __init m548x_uart_init_line(int line, int irq) +static void __init m54xx_uart_init_line(int line, int irq) { int rts_cts; @@ -72,18 +72,18 @@ static void __init m548x_uart_init_line(int line, int irq) MCF_MBAR + MCF_PAR_PSC(line)); } -static void __init m548x_uarts_init(void) +static void __init m54xx_uarts_init(void) { - const int nrlines = ARRAY_SIZE(m548x_uart_platform); + const int nrlines = ARRAY_SIZE(m54xx_uart_platform); int line; for (line = 0; (line < nrlines); line++) - m548x_uart_init_line(line, m548x_uart_platform[line].irq); + m54xx_uart_init_line(line, m54xx_uart_platform[line].irq); } /***************************************************************************/ -static void mcf548x_reset(void) +static void mcf54xx_reset(void) { /* disable interrupts and enable the watchdog */ asm("movew #0x2700, %sr\n"); @@ -97,8 +97,8 @@ static void mcf548x_reset(void) void __init config_BSP(char *commandp, int size) { - mach_reset = mcf548x_reset; - m548x_uarts_init(); + mach_reset = mcf54xx_reset; + m54xx_uarts_init(); } /***************************************************************************/ @@ -106,7 +106,7 @@ void __init config_BSP(char *commandp, int size) static int __init init_BSP(void) { - platform_add_devices(m548x_devices, ARRAY_SIZE(m548x_devices)); + platform_add_devices(m54xx_devices, ARRAY_SIZE(m54xx_devices)); return 0; } diff --git a/arch/m68knommu/platform/68328/ints.c b/arch/m68knommu/platform/68328/ints.c index 865852806a1..2a3af193ccd 100644 --- a/arch/m68knommu/platform/68328/ints.c +++ b/arch/m68knommu/platform/68328/ints.c @@ -179,8 +179,8 @@ void __init init_IRQ(void) IMR = ~0; for (i = 0; (i < NR_IRQS); i++) { - set_irq_chip(irq, &intc_irq_chip); - set_irq_handler(irq, handle_level_irq); + set_irq_chip(i, &intc_irq_chip); + set_irq_handler(i, handle_level_irq); } } diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile index 45f501fa452..a8967baabd7 100644 --- a/arch/m68knommu/platform/coldfire/Makefile +++ b/arch/m68knommu/platform/coldfire/Makefile @@ -14,7 +14,7 @@ asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 -obj-$(CONFIG_COLDFIRE) += clk.o dma.o entry.o vectors.o +obj-$(CONFIG_COLDFIRE) += cache.o clk.o dma.o entry.o vectors.o obj-$(CONFIG_M5206) += timers.o intc.o obj-$(CONFIG_M5206e) += timers.o intc.o obj-$(CONFIG_M520x) += pit.o intc-simr.o @@ -26,7 +26,7 @@ obj-$(CONFIG_M528x) += pit.o intc-2.o obj-$(CONFIG_M5307) += timers.o intc.o obj-$(CONFIG_M532x) += timers.o intc-simr.o obj-$(CONFIG_M5407) += timers.o intc.o -obj-$(CONFIG_M548x) += sltimers.o intc-2.o +obj-$(CONFIG_M54xx) += sltimers.o intc-2.o obj-y += pinmux.o gpio.o extra-y := head.o diff --git a/arch/m68knommu/platform/coldfire/cache.c b/arch/m68knommu/platform/coldfire/cache.c new file mode 100644 index 00000000000..235d3c4f4f0 --- /dev/null +++ b/arch/m68knommu/platform/coldfire/cache.c @@ -0,0 +1,48 @@ +/***************************************************************************/ + +/* + * cache.c -- general ColdFire Cache maintainence code + * + * Copyright (C) 2010, Greg Ungerer (gerg@snapgear.com) + */ + +/***************************************************************************/ + +#include <linux/kernel.h> +#include <asm/coldfire.h> +#include <asm/mcfsim.h> + +/***************************************************************************/ +#ifdef CACHE_PUSH +/***************************************************************************/ + +/* + * Use cpushl to push all dirty cache lines back to memory. + * Older versions of GAS don't seem to know how to generate the + * ColdFire cpushl instruction... Oh well, bit stuff it for now. + */ + +void mcf_cache_push(void) +{ + __asm__ __volatile__ ( + "clrl %%d0\n\t" + "1:\n\t" + "movel %%d0,%%a0\n\t" + "2:\n\t" + ".word 0xf468\n\t" + "addl %0,%%a0\n\t" + "cmpl %1,%%a0\n\t" + "blt 2b\n\t" + "addql #1,%%d0\n\t" + "cmpil %2,%%d0\n\t" + "bne 1b\n\t" + : /* No output */ + : "i" (CACHE_LINE_SIZE), + "i" (DCACHE_SIZE / CACHE_WAYS), + "i" (CACHE_WAYS) + : "d0", "a0" ); +} + +/***************************************************************************/ +#endif /* CACHE_PUSH */ +/***************************************************************************/ diff --git a/arch/m68knommu/platform/coldfire/entry.S b/arch/m68knommu/platform/coldfire/entry.S index e1debc8285e..4ddfc3da70d 100644 --- a/arch/m68knommu/platform/coldfire/entry.S +++ b/arch/m68knommu/platform/coldfire/entry.S @@ -36,13 +36,16 @@ #include <asm/asm-offsets.h> #include <asm/entry.h> +#ifdef CONFIG_COLDFIRE_SW_A7 +/* + * Define software copies of the supervisor and user stack pointers. + */ .bss - sw_ksp: .long 0 - sw_usp: .long 0 +#endif /* CONFIG_COLDFIRE_SW_A7 */ .text @@ -51,7 +54,6 @@ sw_usp: .globl ret_from_exception .globl ret_from_signal .globl sys_call_table -.globl ret_from_interrupt .globl inthandler .globl fasthandler @@ -140,20 +142,7 @@ Luser_return: jne Lwork_to_do /* still work to do */ Lreturn: - move #0x2700,%sr /* disable intrs */ - movel sw_usp,%a0 /* get usp */ - movel %sp@(PT_OFF_PC),%a0@- /* copy exception program counter */ - movel %sp@(PT_OFF_FORMATVEC),%a0@- /* copy exception format/vector/sr */ - moveml %sp@,%d1-%d5/%a0-%a2 - lea %sp@(32),%sp /* space for 8 regs */ - movel %sp@+,%d0 - addql #4,%sp /* orig d0 */ - addl %sp@+,%sp /* stk adj */ - addql #8,%sp /* remove exception */ - movel %sp,sw_ksp /* save ksp */ - subql #8,sw_usp /* set exception */ - movel sw_usp,%sp /* restore usp */ - rte + RESTORE_USER Lwork_to_do: movel %a0@(TI_FLAGS),%d1 /* get thread_info->flags */ @@ -191,31 +180,7 @@ ENTRY(inthandler) jbsr do_IRQ /* call high level irq handler */ lea %sp@(8),%sp /* pop args off stack */ - bra ret_from_interrupt /* this was fallthrough */ - -/* - * This is the fast interrupt handler (for certain hardware interrupt - * sources). Unlike the normal interrupt handler it just uses the - * current stack (doesn't care if it is user or kernel). It also - * doesn't bother doing the bottom half handlers. - */ -ENTRY(fasthandler) - SAVE_LOCAL - - movew %sp@(PT_OFF_FORMATVEC),%d0 - andl #0x03fc,%d0 /* mask out vector only */ - - movel %sp,%sp@- /* push regs arg */ - lsrl #2,%d0 /* calculate real vector # */ - movel %d0,%sp@- /* push vector number */ - jbsr do_IRQ /* call high level irq handler */ - lea %sp@(8),%sp /* pop args off stack */ - - RESTORE_LOCAL - -ENTRY(ret_from_interrupt) - /* the fasthandler is confusing me, haven't seen any user */ - jmp ret_from_exception + bra ret_from_exception /* * Beware - when entering resume, prev (the current task) is @@ -226,9 +191,8 @@ ENTRY(ret_from_interrupt) */ ENTRY(resume) movel %a0, %d1 /* get prev thread in d1 */ - - movel sw_usp,%d0 /* save usp */ - movel %d0,%a0@(TASK_THREAD+THREAD_USP) + RDUSP + movel %a2,%a0@(TASK_THREAD+THREAD_USP) SAVE_SWITCH_STACK movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack pointer */ @@ -236,5 +200,5 @@ ENTRY(resume) RESTORE_SWITCH_STACK movel %a1@(TASK_THREAD+THREAD_USP),%a0 /* restore thread user stack */ - movel %a0, sw_usp + WRUSP rts diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S index 0b2d7c7adf7..d5977909ae5 100644 --- a/arch/m68knommu/platform/coldfire/head.S +++ b/arch/m68knommu/platform/coldfire/head.S @@ -3,7 +3,7 @@ /* * head.S -- common startup code for ColdFire CPUs. * - * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>. + * (C) Copyright 1999-2010, Greg Ungerer <gerg@snapgear.com>. */ /*****************************************************************************/ @@ -13,7 +13,6 @@ #include <linux/init.h> #include <asm/asm-offsets.h> #include <asm/coldfire.h> -#include <asm/mcfcache.h> #include <asm/mcfsim.h> #include <asm/thread_info.h> @@ -173,10 +172,27 @@ _start: /* * Now that we know what the memory is, lets enable cache - * and get things moving. This is Coldfire CPU specific. + * and get things moving. This is Coldfire CPU specific. Not + * all version cores have identical cache register setup. But + * it is very similar. Define the exact settings in the headers + * then the code here is the same for all. */ - CACHE_ENABLE /* enable CPU cache */ - + movel #CACHE_INIT,%d0 /* invalidate whole cache */ + movec %d0,%CACR + nop + movel #ACR0_MODE,%d0 /* set RAM region for caching */ + movec %d0,%ACR0 + movel #ACR1_MODE,%d0 /* anything else to cache? */ + movec %d0,%ACR1 +#ifdef ACR2_MODE + movel #ACR2_MODE,%d0 + movec %d0,%ACR2 + movel #ACR3_MODE,%d0 + movec %d0,%ACR3 +#endif + movel #CACHE_MODE,%d0 /* enable cache */ + movec %d0,%CACR + nop #ifdef CONFIG_ROMFS_FS /* diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 5f5018a71a3..31680032053 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -15,6 +15,8 @@ config MICROBLAZE select TRACING_SUPPORT select OF select OF_EARLY_FLATTREE + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE config SWAP def_bool n @@ -37,12 +39,6 @@ config GENERIC_FIND_NEXT_BIT config GENERIC_HWEIGHT def_bool y -config GENERIC_HARDIRQS - def_bool y - -config GENERIC_IRQ_PROBE - def_bool y - config GENERIC_CALIBRATE_DELAY def_bool y @@ -52,9 +48,6 @@ config GENERIC_TIME_VSYSCALL config GENERIC_CLOCKEVENTS def_bool y -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config GENERIC_GPIO def_bool y diff --git a/arch/microblaze/configs/mmu_defconfig b/arch/microblaze/configs/mmu_defconfig index ab8fbe7ad90..b3f5eecff2a 100644 --- a/arch/microblaze/configs/mmu_defconfig +++ b/arch/microblaze/configs/mmu_defconfig @@ -7,7 +7,7 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="rootfs.cpio" CONFIG_INITRAMFS_COMPRESSION_GZIP=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y # CONFIG_HOTPLUG is not set diff --git a/arch/microblaze/configs/nommu_defconfig b/arch/microblaze/configs/nommu_defconfig index ebc143c5368..0249e4b7e1d 100644 --- a/arch/microblaze/configs/nommu_defconfig +++ b/arch/microblaze/configs/nommu_defconfig @@ -6,7 +6,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y # CONFIG_HOTPLUG is not set diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h index cae268c22ba..b23f6807587 100644 --- a/arch/microblaze/include/asm/pgtable.h +++ b/arch/microblaze/include/asm/pgtable.h @@ -444,8 +444,9 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, *ptep = pte; } -static inline int ptep_test_and_clear_young(struct mm_struct *mm, - unsigned long addr, pte_t *ptep) +#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG +static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, + unsigned long address, pte_t *ptep) { return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0; } @@ -457,6 +458,7 @@ static inline int ptep_test_and_clear_dirty(struct mm_struct *mm, (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0; } +#define __HAVE_ARCH_PTEP_GET_AND_CLEAR static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { diff --git a/arch/microblaze/include/asm/tlb.h b/arch/microblaze/include/asm/tlb.h index e8abd4a0349..8aa97817cc8 100644 --- a/arch/microblaze/include/asm/tlb.h +++ b/arch/microblaze/include/asm/tlb.h @@ -13,6 +13,7 @@ #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) +#include <linux/pagemap.h> #include <asm-generic/tlb.h> #ifdef CONFIG_MMU diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c index c881393f07f..bceaa5543e3 100644 --- a/arch/microblaze/kernel/prom.c +++ b/arch/microblaze/kernel/prom.c @@ -47,9 +47,9 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size) memblock_add(base, size); } -u64 __init early_init_dt_alloc_memory_arch(u64 size, u64 align) +void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) { - return memblock_alloc(size, align); + return __va(memblock_alloc(size, align)); } #ifdef CONFIG_EARLY_PRINTK diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 78439b8a83c..7ff9b549204 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -2,6 +2,7 @@ platforms += alchemy platforms += ar7 +platforms += ath79 platforms += bcm47xx platforms += bcm63xx platforms += cavium-octeon diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f489ec30e07..f5ecc0566bc 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -21,6 +21,7 @@ config MIPS select HAVE_DMA_API_DEBUG select HAVE_GENERIC_HARDIRQS select GENERIC_IRQ_PROBE + select HAVE_ARCH_JUMP_LABEL menu "Machine selection" @@ -65,6 +66,22 @@ config AR7 Support for the Texas Instruments AR7 System-on-a-Chip family: TNETD7100, 7200 and 7300. +config ATH79 + bool "Atheros AR71XX/AR724X/AR913X based boards" + select ARCH_REQUIRE_GPIOLIB + select BOOT_RAW + select CEVT_R4K + select CSRC_R4K + select DMA_NONCOHERENT + select IRQ_CPU + select MIPS_MACHINE + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + help + Support for the Atheros AR71XX/AR724X/AR913X SoCs. + config BCM47XX bool "Broadcom BCM47XX based boards" select CEVT_R4K @@ -717,6 +734,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD endchoice source "arch/mips/alchemy/Kconfig" +source "arch/mips/ath79/Kconfig" source "arch/mips/bcm63xx/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/jz4740/Kconfig" @@ -775,9 +793,6 @@ config SCHED_OMIT_FRAME_POINTER bool default y -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - # # Select some configuration options automatically based on user selections. # @@ -883,6 +898,9 @@ config MIPS_DISABLE_OBSOLETE_IDE config SYNC_R4K bool +config MIPS_MACHINE + def_bool n + config NO_IOPORT def_bool n @@ -2400,4 +2418,20 @@ source "security/Kconfig" source "crypto/Kconfig" +menuconfig VIRTUALIZATION + bool "Virtualization" + default n + ---help--- + Say Y here to get to see options for using your Linux host to run other + operating systems inside virtual machines (guests). + This option alone does not add any kernel code. + + If you say N, all options in this submenu will be skipped and disabled. + +if VIRTUALIZATION + +source drivers/virtio/Kconfig + +endif # VIRTUALIZATION + source "lib/Kconfig" diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index f437cd1fafb..5358f90b4dd 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -7,7 +7,7 @@ config TRACE_IRQFLAGS_SUPPORT source "lib/Kconfig.debug" config EARLY_PRINTK - bool "Early printk" if EMBEDDED + bool "Early printk" if EXPERT depends on SYS_HAS_EARLY_PRINTK default y help diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig new file mode 100644 index 00000000000..b05828260f7 --- /dev/null +++ b/arch/mips/ath79/Kconfig @@ -0,0 +1,50 @@ +if ATH79 + +menu "Atheros AR71XX/AR724X/AR913X machine selection" + +config ATH79_MACH_AP81 + bool "Atheros AP81 reference board" + select SOC_AR913X + select ATH79_DEV_AR913X_WMAC + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_SPI + help + Say 'Y' here if you want your kernel to support the + Atheros AP81 reference board. + +config ATH79_MACH_PB44 + bool "Atheros PB44 reference board" + select SOC_AR71XX + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_SPI + help + Say 'Y' here if you want your kernel to support the + Atheros PB44 reference board. + +endmenu + +config SOC_AR71XX + def_bool n + +config SOC_AR724X + def_bool n + +config SOC_AR913X + def_bool n + +config ATH79_DEV_AR913X_WMAC + depends on SOC_AR913X + def_bool n + +config ATH79_DEV_GPIO_BUTTONS + def_bool n + +config ATH79_DEV_LEDS_GPIO + def_bool n + +config ATH79_DEV_SPI + def_bool n + +endif diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile new file mode 100644 index 00000000000..c33d4653007 --- /dev/null +++ b/arch/mips/ath79/Makefile @@ -0,0 +1,28 @@ +# +# Makefile for the Atheros AR71XX/AR724X/AR913X specific parts of the kernel +# +# Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> +# Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. + +obj-y := prom.o setup.o irq.o common.o clock.o gpio.o + +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +# +# Devices +# +obj-y += dev-common.o +obj-$(CONFIG_ATH79_DEV_AR913X_WMAC) += dev-ar913x-wmac.o +obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o +obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o +obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o + +# +# Machines +# +obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o +obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o diff --git a/arch/mips/ath79/Platform b/arch/mips/ath79/Platform new file mode 100644 index 00000000000..2bd663647d2 --- /dev/null +++ b/arch/mips/ath79/Platform @@ -0,0 +1,7 @@ +# +# Atheros AR71xx/AR724x/AR913x +# + +platform-$(CONFIG_ATH79) += ath79/ +cflags-$(CONFIG_ATH79) += -I$(srctree)/arch/mips/include/asm/mach-ath79 +load-$(CONFIG_ATH79) = 0xffffffff80060000 diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c new file mode 100644 index 00000000000..680bde99a26 --- /dev/null +++ b/arch/mips/ath79/clock.c @@ -0,0 +1,183 @@ +/* + * Atheros AR71XX/AR724X/AR913X common routines + * + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/clk.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> +#include "common.h" + +#define AR71XX_BASE_FREQ 40000000 +#define AR724X_BASE_FREQ 5000000 +#define AR913X_BASE_FREQ 5000000 + +struct clk { + unsigned long rate; +}; + +static struct clk ath79_ref_clk; +static struct clk ath79_cpu_clk; +static struct clk ath79_ddr_clk; +static struct clk ath79_ahb_clk; +static struct clk ath79_wdt_clk; +static struct clk ath79_uart_clk; + +static void __init ar71xx_clocks_init(void) +{ + u32 pll; + u32 freq; + u32 div; + + ath79_ref_clk.rate = AR71XX_BASE_FREQ; + + pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; + freq = div * ath79_ref_clk.rate; + + div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; + ath79_cpu_clk.rate = freq / div; + + div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; + ath79_ddr_clk.rate = freq / div; + + div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; + ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; + + ath79_wdt_clk.rate = ath79_ahb_clk.rate; + ath79_uart_clk.rate = ath79_ahb_clk.rate; +} + +static void __init ar724x_clocks_init(void) +{ + u32 pll; + u32 freq; + u32 div; + + ath79_ref_clk.rate = AR724X_BASE_FREQ; + pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); + freq = div * ath79_ref_clk.rate; + + div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); + freq *= div; + + ath79_cpu_clk.rate = freq; + + div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; + ath79_ddr_clk.rate = freq / div; + + div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; + ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; + + ath79_wdt_clk.rate = ath79_ahb_clk.rate; + ath79_uart_clk.rate = ath79_ahb_clk.rate; +} + +static void __init ar913x_clocks_init(void) +{ + u32 pll; + u32 freq; + u32 div; + + ath79_ref_clk.rate = AR913X_BASE_FREQ; + pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK); + freq = div * ath79_ref_clk.rate; + + ath79_cpu_clk.rate = freq; + + div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1; + ath79_ddr_clk.rate = freq / div; + + div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2; + ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; + + ath79_wdt_clk.rate = ath79_ahb_clk.rate; + ath79_uart_clk.rate = ath79_ahb_clk.rate; +} + +void __init ath79_clocks_init(void) +{ + if (soc_is_ar71xx()) + ar71xx_clocks_init(); + else if (soc_is_ar724x()) + ar724x_clocks_init(); + else if (soc_is_ar913x()) + ar913x_clocks_init(); + else + BUG(); + + pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, " + "Ref:%lu.%03luMHz", + ath79_cpu_clk.rate / 1000000, + (ath79_cpu_clk.rate / 1000) % 1000, + ath79_ddr_clk.rate / 1000000, + (ath79_ddr_clk.rate / 1000) % 1000, + ath79_ahb_clk.rate / 1000000, + (ath79_ahb_clk.rate / 1000) % 1000, + ath79_ref_clk.rate / 1000000, + (ath79_ref_clk.rate / 1000) % 1000); +} + +/* + * Linux clock API + */ +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "ref")) + return &ath79_ref_clk; + + if (!strcmp(id, "cpu")) + return &ath79_cpu_clk; + + if (!strcmp(id, "ddr")) + return &ath79_ddr_clk; + + if (!strcmp(id, "ahb")) + return &ath79_ahb_clk; + + if (!strcmp(id, "wdt")) + return &ath79_wdt_clk; + + if (!strcmp(id, "uart")) + return &ath79_uart_clk; + + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c new file mode 100644 index 00000000000..58f60e722a0 --- /dev/null +++ b/arch/mips/ath79/common.c @@ -0,0 +1,97 @@ +/* + * Atheros AR71XX/AR724X/AR913X common routines + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/spinlock.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> +#include "common.h" + +static DEFINE_SPINLOCK(ath79_device_reset_lock); + +u32 ath79_cpu_freq; +EXPORT_SYMBOL_GPL(ath79_cpu_freq); + +u32 ath79_ahb_freq; +EXPORT_SYMBOL_GPL(ath79_ahb_freq); + +u32 ath79_ddr_freq; +EXPORT_SYMBOL_GPL(ath79_ddr_freq); + +enum ath79_soc_type ath79_soc; + +void __iomem *ath79_pll_base; +void __iomem *ath79_reset_base; +EXPORT_SYMBOL_GPL(ath79_reset_base); +void __iomem *ath79_ddr_base; + +void ath79_ddr_wb_flush(u32 reg) +{ + void __iomem *flush_reg = ath79_ddr_base + reg; + + /* Flush the DDR write buffer. */ + __raw_writel(0x1, flush_reg); + while (__raw_readl(flush_reg) & 0x1) + ; + + /* It must be run twice. */ + __raw_writel(0x1, flush_reg); + while (__raw_readl(flush_reg) & 0x1) + ; +} +EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush); + +void ath79_device_reset_set(u32 mask) +{ + unsigned long flags; + u32 reg; + u32 t; + + if (soc_is_ar71xx()) + reg = AR71XX_RESET_REG_RESET_MODULE; + else if (soc_is_ar724x()) + reg = AR724X_RESET_REG_RESET_MODULE; + else if (soc_is_ar913x()) + reg = AR913X_RESET_REG_RESET_MODULE; + else + BUG(); + + spin_lock_irqsave(&ath79_device_reset_lock, flags); + t = ath79_reset_rr(reg); + ath79_reset_wr(reg, t | mask); + spin_unlock_irqrestore(&ath79_device_reset_lock, flags); +} +EXPORT_SYMBOL_GPL(ath79_device_reset_set); + +void ath79_device_reset_clear(u32 mask) +{ + unsigned long flags; + u32 reg; + u32 t; + + if (soc_is_ar71xx()) + reg = AR71XX_RESET_REG_RESET_MODULE; + else if (soc_is_ar724x()) + reg = AR724X_RESET_REG_RESET_MODULE; + else if (soc_is_ar913x()) + reg = AR913X_RESET_REG_RESET_MODULE; + else + BUG(); + + spin_lock_irqsave(&ath79_device_reset_lock, flags); + t = ath79_reset_rr(reg); + ath79_reset_wr(reg, t & ~mask); + spin_unlock_irqrestore(&ath79_device_reset_lock, flags); +} +EXPORT_SYMBOL_GPL(ath79_device_reset_clear); diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h new file mode 100644 index 00000000000..561906c2345 --- /dev/null +++ b/arch/mips/ath79/common.h @@ -0,0 +1,31 @@ +/* + * Atheros AR71XX/AR724X/AR913X common definitions + * + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ATH79_COMMON_H +#define __ATH79_COMMON_H + +#include <linux/types.h> +#include <linux/init.h> + +#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024) +#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024) + +void ath79_clocks_init(void); +void ath79_ddr_wb_flush(unsigned int reg); + +void ath79_gpio_function_enable(u32 mask); +void ath79_gpio_function_disable(u32 mask); +void ath79_gpio_function_setup(u32 set, u32 clear); +void ath79_gpio_init(void); + +#endif /* __ATH79_COMMON_H */ diff --git a/arch/mips/ath79/dev-ar913x-wmac.c b/arch/mips/ath79/dev-ar913x-wmac.c new file mode 100644 index 00000000000..48f425a5ba2 --- /dev/null +++ b/arch/mips/ath79/dev-ar913x-wmac.c @@ -0,0 +1,60 @@ +/* + * Atheros AR913X SoC built-in WMAC device support + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/ath9k_platform.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> +#include "dev-ar913x-wmac.h" + +static struct ath9k_platform_data ar913x_wmac_data; + +static struct resource ar913x_wmac_resources[] = { + { + .start = AR913X_WMAC_BASE, + .end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .start = ATH79_CPU_IRQ_IP2, + .end = ATH79_CPU_IRQ_IP2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ar913x_wmac_device = { + .name = "ath9k", + .id = -1, + .resource = ar913x_wmac_resources, + .num_resources = ARRAY_SIZE(ar913x_wmac_resources), + .dev = { + .platform_data = &ar913x_wmac_data, + }, +}; + +void __init ath79_register_ar913x_wmac(u8 *cal_data) +{ + if (cal_data) + memcpy(ar913x_wmac_data.eeprom_data, cal_data, + sizeof(ar913x_wmac_data.eeprom_data)); + + /* reset the WMAC */ + ath79_device_reset_set(AR913X_RESET_AMBA2WMAC); + mdelay(10); + + ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC); + mdelay(10); + + platform_device_register(&ar913x_wmac_device); +} diff --git a/arch/mips/ath79/dev-ar913x-wmac.h b/arch/mips/ath79/dev-ar913x-wmac.h new file mode 100644 index 00000000000..579d562bbda --- /dev/null +++ b/arch/mips/ath79/dev-ar913x-wmac.h @@ -0,0 +1,17 @@ +/* + * Atheros AR913X SoC built-in WMAC device support + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_AR913X_WMAC_H +#define _ATH79_DEV_AR913X_WMAC_H + +void ath79_register_ar913x_wmac(u8 *cal_data); + +#endif /* _ATH79_DEV_AR913X_WMAC_H */ diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c new file mode 100644 index 00000000000..3b82e325beb --- /dev/null +++ b/arch/mips/ath79/dev-common.c @@ -0,0 +1,77 @@ +/* + * Atheros AR71XX/AR724X/AR913X common devices + * + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/clk.h> +#include <linux/err.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> +#include "common.h" +#include "dev-common.h" + +static struct resource ath79_uart_resources[] = { + { + .start = AR71XX_UART_BASE, + .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) +static struct plat_serial8250_port ath79_uart_data[] = { + { + .mapbase = AR71XX_UART_BASE, + .irq = ATH79_MISC_IRQ_UART, + .flags = AR71XX_UART_FLAGS, + .iotype = UPIO_MEM32, + .regshift = 2, + }, { + /* terminating entry */ + } +}; + +static struct platform_device ath79_uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .resource = ath79_uart_resources, + .num_resources = ARRAY_SIZE(ath79_uart_resources), + .dev = { + .platform_data = ath79_uart_data + }, +}; + +void __init ath79_register_uart(void) +{ + struct clk *clk; + + clk = clk_get(NULL, "uart"); + if (IS_ERR(clk)) + panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); + + ath79_uart_data[0].uartclk = clk_get_rate(clk); + platform_device_register(&ath79_uart_device); +} + +static struct platform_device ath79_wdt_device = { + .name = "ath79-wdt", + .id = -1, +}; + +void __init ath79_register_wdt(void) +{ + platform_device_register(&ath79_wdt_device); +} diff --git a/arch/mips/ath79/dev-common.h b/arch/mips/ath79/dev-common.h new file mode 100644 index 00000000000..0f514e1affc --- /dev/null +++ b/arch/mips/ath79/dev-common.h @@ -0,0 +1,18 @@ +/* + * Atheros AR71XX/AR724X/AR913X common devices + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_COMMON_H +#define _ATH79_DEV_COMMON_H + +void ath79_register_uart(void); +void ath79_register_wdt(void); + +#endif /* _ATH79_DEV_COMMON_H */ diff --git a/arch/mips/ath79/dev-gpio-buttons.c b/arch/mips/ath79/dev-gpio-buttons.c new file mode 100644 index 00000000000..4b0168a11c0 --- /dev/null +++ b/arch/mips/ath79/dev-gpio-buttons.c @@ -0,0 +1,58 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO button support + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "linux/init.h" +#include "linux/slab.h" +#include <linux/platform_device.h> + +#include "dev-gpio-buttons.h" + +void __init ath79_register_gpio_keys_polled(int id, + unsigned poll_interval, + unsigned nbuttons, + struct gpio_keys_button *buttons) +{ + struct platform_device *pdev; + struct gpio_keys_platform_data pdata; + struct gpio_keys_button *p; + int err; + + p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); + if (!p) + return; + + memcpy(p, buttons, nbuttons * sizeof(*p)); + + pdev = platform_device_alloc("gpio-keys-polled", id); + if (!pdev) + goto err_free_buttons; + + memset(&pdata, 0, sizeof(pdata)); + pdata.poll_interval = poll_interval; + pdata.nbuttons = nbuttons; + pdata.buttons = p; + + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); + if (err) + goto err_put_pdev; + + err = platform_device_add(pdev); + if (err) + goto err_put_pdev; + + return; + +err_put_pdev: + platform_device_put(pdev); + +err_free_buttons: + kfree(p); +} diff --git a/arch/mips/ath79/dev-gpio-buttons.h b/arch/mips/ath79/dev-gpio-buttons.h new file mode 100644 index 00000000000..481847ac1cb --- /dev/null +++ b/arch/mips/ath79/dev-gpio-buttons.h @@ -0,0 +1,23 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO button support + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_GPIO_BUTTONS_H +#define _ATH79_DEV_GPIO_BUTTONS_H + +#include <linux/input.h> +#include <linux/gpio_keys.h> + +void ath79_register_gpio_keys_polled(int id, + unsigned poll_interval, + unsigned nbuttons, + struct gpio_keys_button *buttons); + +#endif /* _ATH79_DEV_GPIO_BUTTONS_H */ diff --git a/arch/mips/ath79/dev-leds-gpio.c b/arch/mips/ath79/dev-leds-gpio.c new file mode 100644 index 00000000000..cdade68dcd1 --- /dev/null +++ b/arch/mips/ath79/dev-leds-gpio.c @@ -0,0 +1,56 @@ +/* + * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/platform_device.h> + +#include "dev-leds-gpio.h" + +void __init ath79_register_leds_gpio(int id, + unsigned num_leds, + struct gpio_led *leds) +{ + struct platform_device *pdev; + struct gpio_led_platform_data pdata; + struct gpio_led *p; + int err; + + p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); + if (!p) + return; + + memcpy(p, leds, num_leds * sizeof(*p)); + + pdev = platform_device_alloc("leds-gpio", id); + if (!pdev) + goto err_free_leds; + + memset(&pdata, 0, sizeof(pdata)); + pdata.num_leds = num_leds; + pdata.leds = p; + + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); + if (err) + goto err_put_pdev; + + err = platform_device_add(pdev); + if (err) + goto err_put_pdev; + + return; + +err_put_pdev: + platform_device_put(pdev); + +err_free_leds: + kfree(p); +} diff --git a/arch/mips/ath79/dev-leds-gpio.h b/arch/mips/ath79/dev-leds-gpio.h new file mode 100644 index 00000000000..6e5d8851ebc --- /dev/null +++ b/arch/mips/ath79/dev-leds-gpio.h @@ -0,0 +1,21 @@ +/* + * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_LEDS_GPIO_H +#define _ATH79_DEV_LEDS_GPIO_H + +#include <linux/leds.h> + +void ath79_register_leds_gpio(int id, + unsigned num_leds, + struct gpio_led *leds); + +#endif /* _ATH79_DEV_LEDS_GPIO_H */ diff --git a/arch/mips/ath79/dev-spi.c b/arch/mips/ath79/dev-spi.c new file mode 100644 index 00000000000..aa30163efbf --- /dev/null +++ b/arch/mips/ath79/dev-spi.c @@ -0,0 +1,38 @@ +/* + * Atheros AR71XX/AR724X/AR913X SPI controller device + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <asm/mach-ath79/ar71xx_regs.h> +#include "dev-spi.h" + +static struct resource ath79_spi_resources[] = { + { + .start = AR71XX_SPI_BASE, + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ath79_spi_device = { + .name = "ath79-spi", + .id = -1, + .resource = ath79_spi_resources, + .num_resources = ARRAY_SIZE(ath79_spi_resources), +}; + +void __init ath79_register_spi(struct ath79_spi_platform_data *pdata, + struct spi_board_info const *info, + unsigned n) +{ + spi_register_board_info(info, n); + ath79_spi_device.dev.platform_data = pdata; + platform_device_register(&ath79_spi_device); +} diff --git a/arch/mips/ath79/dev-spi.h b/arch/mips/ath79/dev-spi.h new file mode 100644 index 00000000000..d732565ca73 --- /dev/null +++ b/arch/mips/ath79/dev-spi.h @@ -0,0 +1,22 @@ +/* + * Atheros AR71XX/AR724X/AR913X SPI controller device + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_SPI_H +#define _ATH79_DEV_SPI_H + +#include <linux/spi/spi.h> +#include <asm/mach-ath79/ath79_spi_platform.h> + +void ath79_register_spi(struct ath79_spi_platform_data *pdata, + struct spi_board_info const *info, + unsigned n); + +#endif /* _ATH79_DEV_SPI_H */ diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c new file mode 100644 index 00000000000..7499b0e9df2 --- /dev/null +++ b/arch/mips/ath79/early_printk.c @@ -0,0 +1,36 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC early printk support + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/io.h> +#include <linux/serial_reg.h> +#include <asm/addrspace.h> + +#include <asm/mach-ath79/ar71xx_regs.h> + +static inline void prom_wait_thre(void __iomem *base) +{ + u32 lsr; + + do { + lsr = __raw_readl(base + UART_LSR * 4); + if (lsr & UART_LSR_THRE) + break; + } while (1); +} + +void prom_putchar(unsigned char ch) +{ + void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); + + prom_wait_thre(base); + __raw_writel(ch, base + UART_TX * 4); + prom_wait_thre(base); +} diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c new file mode 100644 index 00000000000..a0c426b8212 --- /dev/null +++ b/arch/mips/ath79/gpio.c @@ -0,0 +1,197 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO API support + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/spinlock.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/gpio.h> + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> +#include "common.h" + +static void __iomem *ath79_gpio_base; +static unsigned long ath79_gpio_count; +static DEFINE_SPINLOCK(ath79_gpio_lock); + +static void __ath79_gpio_set_value(unsigned gpio, int value) +{ + void __iomem *base = ath79_gpio_base; + + if (value) + __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET); + else + __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR); +} + +static int __ath79_gpio_get_value(unsigned gpio) +{ + return (__raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1; +} + +static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned offset) +{ + return __ath79_gpio_get_value(offset); +} + +static void ath79_gpio_set_value(struct gpio_chip *chip, + unsigned offset, int value) +{ + __ath79_gpio_set_value(offset, value); +} + +static int ath79_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), + base + AR71XX_GPIO_REG_OE); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + + return 0; +} + +static int ath79_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + if (value) + __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); + else + __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), + base + AR71XX_GPIO_REG_OE); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + + return 0; +} + +static struct gpio_chip ath79_gpio_chip = { + .label = "ath79", + .get = ath79_gpio_get_value, + .set = ath79_gpio_set_value, + .direction_input = ath79_gpio_direction_input, + .direction_output = ath79_gpio_direction_output, + .base = 0, +}; + +void ath79_gpio_function_enable(u32 mask) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask, + base + AR71XX_GPIO_REG_FUNC); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_FUNC); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); +} + +void ath79_gpio_function_disable(u32 mask) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask, + base + AR71XX_GPIO_REG_FUNC); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_FUNC); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); +} + +void ath79_gpio_function_setup(u32 set, u32 clear) +{ + void __iomem *base = ath79_gpio_base; + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + + __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set, + base + AR71XX_GPIO_REG_FUNC); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_FUNC); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); +} + +void __init ath79_gpio_init(void) +{ + int err; + + if (soc_is_ar71xx()) + ath79_gpio_count = AR71XX_GPIO_COUNT; + else if (soc_is_ar724x()) + ath79_gpio_count = AR724X_GPIO_COUNT; + else if (soc_is_ar913x()) + ath79_gpio_count = AR913X_GPIO_COUNT; + else + BUG(); + + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + ath79_gpio_chip.ngpio = ath79_gpio_count; + + err = gpiochip_add(&ath79_gpio_chip); + if (err) + panic("cannot add AR71xx GPIO chip, error=%d", err); +} + +int gpio_get_value(unsigned gpio) +{ + if (gpio < ath79_gpio_count) + return __ath79_gpio_get_value(gpio); + + return __gpio_get_value(gpio); +} +EXPORT_SYMBOL(gpio_get_value); + +void gpio_set_value(unsigned gpio, int value) +{ + if (gpio < ath79_gpio_count) + __ath79_gpio_set_value(gpio, value); + else + __gpio_set_value(gpio, value); +} +EXPORT_SYMBOL(gpio_set_value); + +int gpio_to_irq(unsigned gpio) +{ + /* FIXME */ + return -EINVAL; +} +EXPORT_SYMBOL(gpio_to_irq); + +int irq_to_gpio(unsigned irq) +{ + /* FIXME */ + return -EINVAL; +} +EXPORT_SYMBOL(irq_to_gpio); diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c new file mode 100644 index 00000000000..1bf7f719ba5 --- /dev/null +++ b/arch/mips/ath79/irq.c @@ -0,0 +1,187 @@ +/* + * Atheros AR71xx/AR724x/AR913x specific interrupt handling + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> + +#include <asm/irq_cpu.h> +#include <asm/mipsregs.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> +#include "common.h" + +static unsigned int ath79_ip2_flush_reg; +static unsigned int ath79_ip3_flush_reg; + +static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + void __iomem *base = ath79_reset_base; + u32 pending; + + pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); + + if (pending & MISC_INT_UART) + generic_handle_irq(ATH79_MISC_IRQ_UART); + + else if (pending & MISC_INT_DMA) + generic_handle_irq(ATH79_MISC_IRQ_DMA); + + else if (pending & MISC_INT_PERFC) + generic_handle_irq(ATH79_MISC_IRQ_PERFC); + + else if (pending & MISC_INT_TIMER) + generic_handle_irq(ATH79_MISC_IRQ_TIMER); + + else if (pending & MISC_INT_OHCI) + generic_handle_irq(ATH79_MISC_IRQ_OHCI); + + else if (pending & MISC_INT_ERROR) + generic_handle_irq(ATH79_MISC_IRQ_ERROR); + + else if (pending & MISC_INT_GPIO) + generic_handle_irq(ATH79_MISC_IRQ_GPIO); + + else if (pending & MISC_INT_WDOG) + generic_handle_irq(ATH79_MISC_IRQ_WDOG); + + else + spurious_interrupt(); +} + +static void ar71xx_misc_irq_unmask(unsigned int irq) +{ + void __iomem *base = ath79_reset_base; + u32 t; + + irq -= ATH79_MISC_IRQ_BASE; + + t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); + __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); + + /* flush write */ + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); +} + +static void ar71xx_misc_irq_mask(unsigned int irq) +{ + void __iomem *base = ath79_reset_base; + u32 t; + + irq -= ATH79_MISC_IRQ_BASE; + + t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); + __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); + + /* flush write */ + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); +} + +static void ar724x_misc_irq_ack(unsigned int irq) +{ + void __iomem *base = ath79_reset_base; + u32 t; + + irq -= ATH79_MISC_IRQ_BASE; + + t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); + __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); + + /* flush write */ + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); +} + +static struct irq_chip ath79_misc_irq_chip = { + .name = "MISC", + .unmask = ar71xx_misc_irq_unmask, + .mask = ar71xx_misc_irq_mask, +}; + +static void __init ath79_misc_irq_init(void) +{ + void __iomem *base = ath79_reset_base; + int i; + + __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); + __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); + + if (soc_is_ar71xx() || soc_is_ar913x()) + ath79_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask; + else if (soc_is_ar724x()) + ath79_misc_irq_chip.ack = ar724x_misc_irq_ack; + else + BUG(); + + for (i = ATH79_MISC_IRQ_BASE; + i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) { + irq_desc[i].status = IRQ_DISABLED; + set_irq_chip_and_handler(i, &ath79_misc_irq_chip, + handle_level_irq); + } + + set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned long pending; + + pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP7) + do_IRQ(ATH79_CPU_IRQ_TIMER); + + else if (pending & STATUSF_IP2) { + ath79_ddr_wb_flush(ath79_ip2_flush_reg); + do_IRQ(ATH79_CPU_IRQ_IP2); + } + + else if (pending & STATUSF_IP4) + do_IRQ(ATH79_CPU_IRQ_GE0); + + else if (pending & STATUSF_IP5) + do_IRQ(ATH79_CPU_IRQ_GE1); + + else if (pending & STATUSF_IP3) { + ath79_ddr_wb_flush(ath79_ip3_flush_reg); + do_IRQ(ATH79_CPU_IRQ_USB); + } + + else if (pending & STATUSF_IP6) + do_IRQ(ATH79_CPU_IRQ_MISC); + + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + if (soc_is_ar71xx()) { + ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; + ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB; + } else if (soc_is_ar724x()) { + ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; + ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB; + } else if (soc_is_ar913x()) { + ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC; + ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB; + } else + BUG(); + + cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; + mips_cpu_irq_init(); + ath79_misc_irq_init(); +} diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c new file mode 100644 index 00000000000..eee4c121deb --- /dev/null +++ b/arch/mips/ath79/mach-ap81.c @@ -0,0 +1,98 @@ +/* + * Atheros AP81 board support + * + * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "machtypes.h" +#include "dev-ar913x-wmac.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-spi.h" + +#define AP81_GPIO_LED_STATUS 1 +#define AP81_GPIO_LED_AOSS 3 +#define AP81_GPIO_LED_WLAN 6 +#define AP81_GPIO_LED_POWER 14 + +#define AP81_GPIO_BTN_SW4 12 +#define AP81_GPIO_BTN_SW1 21 + +#define AP81_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP81_KEYS_DEBOUNCE_INTERVAL (3 * AP81_KEYS_POLL_INTERVAL) + +#define AP81_CAL_DATA_ADDR 0x1fff1000 + +static struct gpio_led ap81_leds_gpio[] __initdata = { + { + .name = "ap81:green:status", + .gpio = AP81_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "ap81:amber:aoss", + .gpio = AP81_GPIO_LED_AOSS, + .active_low = 1, + }, { + .name = "ap81:green:wlan", + .gpio = AP81_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "ap81:green:power", + .gpio = AP81_GPIO_LED_POWER, + .active_low = 1, + } +}; + +static struct gpio_keys_button ap81_gpio_keys[] __initdata = { + { + .desc = "sw1", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP81_GPIO_BTN_SW1, + .active_low = 1, + } , { + .desc = "sw4", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP81_GPIO_BTN_SW4, + .active_low = 1, + } +}; + +static struct spi_board_info ap81_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", + } +}; + +static struct ath79_spi_platform_data ap81_spi_data = { + .bus_num = 0, + .num_chipselect = 1, +}; + +static void __init ap81_setup(void) +{ + u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio), + ap81_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap81_gpio_keys), + ap81_gpio_keys); + ath79_register_spi(&ap81_spi_data, ap81_spi_info, + ARRAY_SIZE(ap81_spi_info)); + ath79_register_ar913x_wmac(cal_data); +} + +MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board", + ap81_setup); diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c new file mode 100644 index 00000000000..ec7b7a135d5 --- /dev/null +++ b/arch/mips/ath79/mach-pb44.c @@ -0,0 +1,118 @@ +/* + * Atheros PB44 reference board support + * + * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> +#include <linux/i2c-gpio.h> +#include <linux/i2c/pcf857x.h> + +#include "machtypes.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-spi.h" + +#define PB44_GPIO_I2C_SCL 0 +#define PB44_GPIO_I2C_SDA 1 + +#define PB44_GPIO_EXP_BASE 16 +#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6) +#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8) +#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9) +#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + 10) + +#define PB44_KEYS_POLL_INTERVAL 20 /* msecs */ +#define PB44_KEYS_DEBOUNCE_INTERVAL (3 * PB44_KEYS_POLL_INTERVAL) + +static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { + .sda_pin = PB44_GPIO_I2C_SDA, + .scl_pin = PB44_GPIO_I2C_SCL, +}; + +static struct platform_device pb44_i2c_gpio_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &pb44_i2c_gpio_data, + } +}; + +static struct pcf857x_platform_data pb44_pcf857x_data = { + .gpio_base = PB44_GPIO_EXP_BASE, +}; + +static struct i2c_board_info pb44_i2c_board_info[] __initdata = { + { + I2C_BOARD_INFO("pcf8575", 0x20), + .platform_data = &pb44_pcf857x_data, + }, +}; + +static struct gpio_led pb44_leds_gpio[] __initdata = { + { + .name = "pb44:amber:jump1", + .gpio = PB44_GPIO_LED_JUMP1, + .active_low = 1, + }, { + .name = "pb44:green:jump2", + .gpio = PB44_GPIO_LED_JUMP2, + .active_low = 1, + }, +}; + +static struct gpio_keys_button pb44_gpio_keys[] __initdata = { + { + .desc = "soft_reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB44_GPIO_SW_RESET, + .active_low = 1, + } , { + .desc = "jumpstart", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB44_GPIO_SW_JUMP, + .active_low = 1, + } +}; + +static struct spi_board_info pb44_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", + }, +}; + +static struct ath79_spi_platform_data pb44_spi_data = { + .bus_num = 0, + .num_chipselect = 1, +}; + +static void __init pb44_init(void) +{ + i2c_register_board_info(0, pb44_i2c_board_info, + ARRAY_SIZE(pb44_i2c_board_info)); + platform_device_register(&pb44_i2c_gpio_device); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), + pb44_leds_gpio); + ath79_register_gpio_keys_polled(-1, PB44_KEYS_POLL_INTERVAL, + ARRAY_SIZE(pb44_gpio_keys), + pb44_gpio_keys); + ath79_register_spi(&pb44_spi_data, pb44_spi_info, + ARRAY_SIZE(pb44_spi_info)); +} + +MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", + pb44_init); diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h new file mode 100644 index 00000000000..3940fe470b2 --- /dev/null +++ b/arch/mips/ath79/machtypes.h @@ -0,0 +1,23 @@ +/* + * Atheros AR71XX/AR724X/AR913X machine type definitions + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_MACHTYPE_H +#define _ATH79_MACHTYPE_H + +#include <asm/mips_machine.h> + +enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_PB44, /* Atheros PB44 reference board */ +}; + +#endif /* _ATH79_MACHTYPE_H */ diff --git a/arch/mips/ath79/prom.c b/arch/mips/ath79/prom.c new file mode 100644 index 00000000000..e9cbd7c2918 --- /dev/null +++ b/arch/mips/ath79/prom.c @@ -0,0 +1,57 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific prom routines + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/string.h> + +#include <asm/bootinfo.h> +#include <asm/addrspace.h> + +#include "common.h" + +static inline int is_valid_ram_addr(void *addr) +{ + if (((u32) addr > KSEG0) && + ((u32) addr < (KSEG0 + ATH79_MEM_SIZE_MAX))) + return 1; + + if (((u32) addr > KSEG1) && + ((u32) addr < (KSEG1 + ATH79_MEM_SIZE_MAX))) + return 1; + + return 0; +} + +static __init void ath79_prom_init_cmdline(int argc, char **argv) +{ + int i; + + if (!is_valid_ram_addr(argv)) + return; + + for (i = 0; i < argc; i++) + if (is_valid_ram_addr(argv[i])) { + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + strlcat(arcs_cmdline, argv[i], sizeof(arcs_cmdline)); + } +} + +void __init prom_init(void) +{ + ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1); +} + +void __init prom_free_prom_memory(void) +{ + /* We do not have to prom memory to free */ +} diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c new file mode 100644 index 00000000000..159b42f106b --- /dev/null +++ b/arch/mips/ath79/setup.c @@ -0,0 +1,206 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific setup + * + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/bootmem.h> +#include <linux/err.h> +#include <linux/clk.h> + +#include <asm/bootinfo.h> +#include <asm/time.h> /* for mips_hpt_frequency */ +#include <asm/reboot.h> /* for _machine_{restart,halt} */ +#include <asm/mips_machine.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> +#include "common.h" +#include "dev-common.h" +#include "machtypes.h" + +#define ATH79_SYS_TYPE_LEN 64 + +#define AR71XX_BASE_FREQ 40000000 +#define AR724X_BASE_FREQ 5000000 +#define AR913X_BASE_FREQ 5000000 + +static char ath79_sys_type[ATH79_SYS_TYPE_LEN]; + +static void ath79_restart(char *command) +{ + ath79_device_reset_set(AR71XX_RESET_FULL_CHIP); + for (;;) + if (cpu_wait) + cpu_wait(); +} + +static void ath79_halt(void) +{ + while (1) + cpu_wait(); +} + +static void __init ath79_detect_mem_size(void) +{ + unsigned long size; + + for (size = ATH79_MEM_SIZE_MIN; size < ATH79_MEM_SIZE_MAX; + size <<= 1) { + if (!memcmp(ath79_detect_mem_size, + ath79_detect_mem_size + size, 1024)) + break; + } + + add_memory_region(0, size, BOOT_MEM_RAM); +} + +static void __init ath79_detect_sys_type(void) +{ + char *chip = "????"; + u32 id; + u32 major; + u32 minor; + u32 rev = 0; + + id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); + major = id & REV_ID_MAJOR_MASK; + + switch (major) { + case REV_ID_MAJOR_AR71XX: + minor = id & AR71XX_REV_ID_MINOR_MASK; + rev = id >> AR71XX_REV_ID_REVISION_SHIFT; + rev &= AR71XX_REV_ID_REVISION_MASK; + switch (minor) { + case AR71XX_REV_ID_MINOR_AR7130: + ath79_soc = ATH79_SOC_AR7130; + chip = "7130"; + break; + + case AR71XX_REV_ID_MINOR_AR7141: + ath79_soc = ATH79_SOC_AR7141; + chip = "7141"; + break; + + case AR71XX_REV_ID_MINOR_AR7161: + ath79_soc = ATH79_SOC_AR7161; + chip = "7161"; + break; + } + break; + + case REV_ID_MAJOR_AR7240: + ath79_soc = ATH79_SOC_AR7240; + chip = "7240"; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR7241: + ath79_soc = ATH79_SOC_AR7241; + chip = "7241"; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR7242: + ath79_soc = ATH79_SOC_AR7242; + chip = "7242"; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR913X: + minor = id & AR913X_REV_ID_MINOR_MASK; + rev = id >> AR913X_REV_ID_REVISION_SHIFT; + rev &= AR913X_REV_ID_REVISION_MASK; + switch (minor) { + case AR913X_REV_ID_MINOR_AR9130: + ath79_soc = ATH79_SOC_AR9130; + chip = "9130"; + break; + + case AR913X_REV_ID_MINOR_AR9132: + ath79_soc = ATH79_SOC_AR9132; + chip = "9132"; + break; + } + break; + + default: + panic("ath79: unknown SoC, id:0x%08x\n", id); + } + + sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); + pr_info("SoC: %s\n", ath79_sys_type); +} + +const char *get_system_type(void) +{ + return ath79_sys_type; +} + +unsigned int __cpuinit get_c0_compare_int(void) +{ + return CP0_LEGACY_COMPARE_IRQ; +} + +void __init plat_mem_setup(void) +{ + set_io_port_base(KSEG1); + + ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, + AR71XX_RESET_SIZE); + ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, + AR71XX_PLL_SIZE); + ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, + AR71XX_DDR_CTRL_SIZE); + + ath79_detect_sys_type(); + ath79_detect_mem_size(); + ath79_clocks_init(); + + _machine_restart = ath79_restart; + _machine_halt = ath79_halt; + pm_power_off = ath79_halt; +} + +void __init plat_time_init(void) +{ + struct clk *clk; + + clk = clk_get(NULL, "cpu"); + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + + mips_hpt_frequency = clk_get_rate(clk) / 2; +} + +static int __init ath79_setup(void) +{ + ath79_gpio_init(); + ath79_register_uart(); + ath79_register_wdt(); + + mips_machine_setup(); + + return 0; +} + +arch_initcall(ath79_setup); + +static void __init ath79_generic_init(void) +{ + /* Nothing to do */ +} + +MIPS_MACHINE(ATH79_MACH_GENERIC, + "Generic", + "Generic AR71XX/AR724X/AR913X based board", + ath79_generic_init); diff --git a/arch/mips/configs/ar7_defconfig b/arch/mips/configs/ar7_defconfig index c78c7e7e41d..6cd5a519ce5 100644 --- a/arch/mips/configs/ar7_defconfig +++ b/arch/mips/configs/ar7_defconfig @@ -14,7 +14,7 @@ CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_RD_LZMA=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_ELF_CORE is not set # CONFIG_PCSPKR_PLATFORM is not set diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig index 927d58b2cd0..22fdf2f0cc2 100644 --- a/arch/mips/configs/bcm47xx_defconfig +++ b/arch/mips/configs/bcm47xx_defconfig @@ -21,7 +21,7 @@ CONFIG_CGROUP_CPUACCT=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_RD_LZMA=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/mips/configs/bcm63xx_defconfig b/arch/mips/configs/bcm63xx_defconfig index b806a4e3289..919005139f5 100644 --- a/arch/mips/configs/bcm63xx_defconfig +++ b/arch/mips/configs/bcm63xx_defconfig @@ -10,7 +10,7 @@ CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_TINY_RCU=y CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_PCSPKR_PLATFORM is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index 9749bc8758d..1cdff6b6327 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -26,7 +26,7 @@ CONFIG_PID_NS=y CONFIG_NET_NS=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_PCSPKR_PLATFORM is not set CONFIG_SLAB=y diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index 502a8e9c084..5135dc0b950 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig @@ -4,7 +4,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/mips/configs/cavium-octeon_defconfig b/arch/mips/configs/cavium-octeon_defconfig index 3567b6f07b3..75165dfa60c 100644 --- a/arch/mips/configs/cavium-octeon_defconfig +++ b/arch/mips/configs/cavium-octeon_defconfig @@ -15,7 +15,7 @@ CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_PCSPKR_PLATFORM is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index 6c4f7e9d338..5419adb219a 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index dda158b2c8d..4044c9e0fb7 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -11,7 +11,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_TINY_RCU=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_PCSPKR_PLATFORM is not set # CONFIG_VM_EVENT_COUNTERS is not set diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index 7e4fc76df53..c6b49938ee8 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig @@ -11,7 +11,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_TINY_RCU=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_KALLSYMS is not set # CONFIG_PCSPKR_PLATFORM is not set diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index 6fe205fa7b6..1f69249b839 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -12,7 +12,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_TINY_RCU=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_KALLSYMS is not set # CONFIG_PCSPKR_PLATFORM is not set diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index a741c55448d..b6e21c7cb6b 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig @@ -10,7 +10,7 @@ CONFIG_LOCALVERSION="-db1500" CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_PCSPKR_PLATFORM is not set # CONFIG_VM_EVENT_COUNTERS is not set diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index cd32dd8c800..798a553c9e8 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -11,7 +11,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_TINY_RCU=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_KALLSYMS is not set # CONFIG_PCSPKR_PLATFORM is not set diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index b15bfd1e69c..87d0340837a 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -4,7 +4,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_HOTPLUG is not set CONFIG_SLAB=y diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index 0b60c06a943..0126e66d60c 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig @@ -4,7 +4,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_HOTPLUG is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/mips/configs/fuloong2e_defconfig b/arch/mips/configs/fuloong2e_defconfig index 63944a14b81..e5b73de08fc 100644 --- a/arch/mips/configs/fuloong2e_defconfig +++ b/arch/mips/configs/fuloong2e_defconfig @@ -17,7 +17,7 @@ CONFIG_NAMESPACES=y CONFIG_USER_NS=y CONFIG_PID_NS=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_PCSPKR_PLATFORM is not set # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig index 53edc134f27..48a40aefaf5 100644 --- a/arch/mips/configs/gpr_defconfig +++ b/arch/mips/configs/gpr_defconfig @@ -11,7 +11,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MODULES=y diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 36de199f4c2..d1606569b00 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -17,7 +17,7 @@ CONFIG_IPC_NS=y CONFIG_USER_NS=y CONFIG_PID_NS=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_HOTPLUG is not set # CONFIG_PCSPKR_PLATFORM is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index 4b16c48b0c3..0e36abcd39c 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -15,7 +15,7 @@ CONFIG_CGROUPS=y CONFIG_CPUSETS=y CONFIG_RELAY=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_PCSPKR_PLATFORM is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig index 98f2c7736e8..4dbf6269b3f 100644 --- a/arch/mips/configs/ip28_defconfig +++ b/arch/mips/configs/ip28_defconfig @@ -8,7 +8,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_HOTPLUG is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index 5bea99b26fa..7bbd52194fc 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -10,7 +10,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_OPROFILE=m diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig index 6ae46bcdb20..92a60aecad5 100644 --- a/arch/mips/configs/jazz_defconfig +++ b/arch/mips/configs/jazz_defconfig @@ -10,7 +10,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index bf24e9309b9..db5705e18b3 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -4,7 +4,7 @@ CONFIG_TOSHIBA_JMR3927=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_HOTPLUG is not set # CONFIG_PCSPKR_PLATFORM is not set CONFIG_SLAB=y diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig index 6447261c61d..d9f3db29ab9 100644 --- a/arch/mips/configs/lasat_defconfig +++ b/arch/mips/configs/lasat_defconfig @@ -8,7 +8,7 @@ CONFIG_HZ_1000=y CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig index f7033f3a582..167c1d07b80 100644 --- a/arch/mips/configs/lemote2f_defconfig +++ b/arch/mips/configs/lemote2f_defconfig @@ -21,7 +21,7 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_PROFILING=y CONFIG_OPROFILE=m CONFIG_MODULES=y diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index b455d0f3648..7270f3183bd 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -15,7 +15,7 @@ CONFIG_UTS_NS=y CONFIG_IPC_NS=y CONFIG_PID_NS=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y @@ -369,7 +369,10 @@ CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y # CONFIG_HWMON is not set +CONFIG_FB=y +CONFIG_FB_CIRRUS=y # CONFIG_VGA_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_HID=m CONFIG_LEDS_CLASS=m CONFIG_LEDS_TRIGGER_TIMER=m diff --git a/arch/mips/configs/markeins_defconfig b/arch/mips/configs/markeins_defconfig index 86bf001babe..9c9a123016c 100644 --- a/arch/mips/configs/markeins_defconfig +++ b/arch/mips/configs/markeins_defconfig @@ -9,7 +9,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig index 4925f507dc2..b5ad7387bbb 100644 --- a/arch/mips/configs/mipssim_defconfig +++ b/arch/mips/configs/mipssim_defconfig @@ -7,7 +7,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index efb779f8f6f..c16de981292 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig @@ -5,7 +5,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig index ab051458452..d1142e9cd9a 100644 --- a/arch/mips/configs/msp71xx_defconfig +++ b/arch/mips/configs/msp71xx_defconfig @@ -8,7 +8,7 @@ CONFIG_LOCALVERSION="-pmc" CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SHMEM is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index 814699754e0..a97a42c6b2c 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -11,7 +11,7 @@ CONFIG_AUDIT=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_OPROFILE=m diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index 1597aa1842f..75eb1b1f316 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig @@ -11,7 +11,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_TINY_RCU=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_KALLSYMS is not set # CONFIG_PCSPKR_PLATFORM is not set diff --git a/arch/mips/configs/pb1200_defconfig b/arch/mips/configs/pb1200_defconfig index 96f0d43cf08..dcbe2704e5e 100644 --- a/arch/mips/configs/pb1200_defconfig +++ b/arch/mips/configs/pb1200_defconfig @@ -12,7 +12,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_TINY_RCU=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_KALLSYMS is not set # CONFIG_PCSPKR_PLATFORM is not set diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index b4bfd482345..fa00487146f 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig @@ -11,7 +11,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_TINY_RCU=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_KALLSYMS is not set # CONFIG_PCSPKR_PLATFORM is not set diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index 5a660024d22..e83d6497e8b 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -11,7 +11,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_TINY_RCU=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_KALLSYMS is not set # CONFIG_PCSPKR_PLATFORM is not set diff --git a/arch/mips/configs/pnx8335-stb225_defconfig b/arch/mips/configs/pnx8335-stb225_defconfig index 39926a1a96b..f2925769dfa 100644 --- a/arch/mips/configs/pnx8335-stb225_defconfig +++ b/arch/mips/configs/pnx8335-stb225_defconfig @@ -11,7 +11,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig index 3376bc8616c..1d1f2067f3e 100644 --- a/arch/mips/configs/pnx8550-jbs_defconfig +++ b/arch/mips/configs/pnx8550-jbs_defconfig @@ -6,7 +6,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig index 6514f1bf0af..15c66a571f9 100644 --- a/arch/mips/configs/pnx8550-stb810_defconfig +++ b/arch/mips/configs/pnx8550-stb810_defconfig @@ -6,7 +6,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_HOTPLUG is not set CONFIG_SLAB=y diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig index f1f58e91dd8..3b0b6e8c853 100644 --- a/arch/mips/configs/powertv_defconfig +++ b/arch/mips/configs/powertv_defconfig @@ -14,7 +14,7 @@ CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_GZIP is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS_ALL=y # CONFIG_PCSPKR_PLATFORM is not set diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig index d6457bc38c7..55902d9cd0f 100644 --- a/arch/mips/configs/rb532_defconfig +++ b/arch/mips/configs/rb532_defconfig @@ -13,7 +13,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_ELF_CORE is not set # CONFIG_VM_EVENT_COUNTERS is not set diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig index 29acfab3151..9cba856277f 100644 --- a/arch/mips/configs/rbtx49xx_defconfig +++ b/arch/mips/configs/rbtx49xx_defconfig @@ -12,7 +12,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_HOTPLUG is not set # CONFIG_PCSPKR_PLATFORM is not set # CONFIG_EPOLL is not set diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index 2b3e47653f6..2c0230e76d2 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -12,7 +12,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index 64840d71775..5b0463ef938 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -15,7 +15,7 @@ CONFIG_RELAY=y CONFIG_NAMESPACES=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig index d9be37fc9cb..30036b4cbeb 100644 --- a/arch/mips/configs/tb0219_defconfig +++ b/arch/mips/configs/tb0219_defconfig @@ -5,7 +5,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_PCSPKR_PLATFORM is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index 3d25dd08907..81bfa1d4d8e 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -5,7 +5,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_PCSPKR_PLATFORM is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig index be697c9b23c..c415c4f0e5c 100644 --- a/arch/mips/configs/tb0287_defconfig +++ b/arch/mips/configs/tb0287_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_PCSPKR_PLATFORM is not set CONFIG_SLAB=y diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index 7ec9287254d..ee4b2be43c4 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig @@ -4,7 +4,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig index a231b73b1a4..44a451be359 100644 --- a/arch/mips/configs/wrppmc_defconfig +++ b/arch/mips/configs/wrppmc_defconfig @@ -7,7 +7,7 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_EXTRA_PASS=y # CONFIG_EPOLL is not set CONFIG_SLAB=y diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig index ab3a3dcec04..f72d305a3f0 100644 --- a/arch/mips/configs/yosemite_defconfig +++ b/arch/mips/configs/yosemite_defconfig @@ -8,7 +8,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 37f175c42bb..650ac9ba734 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -17,4 +17,6 @@ #define SMP_CACHE_SHIFT L1_CACHE_SHIFT #define SMP_CACHE_BYTES L1_CACHE_BYTES +#define __read_mostly __attribute__((__section__(".data.read_mostly"))) + #endif /* _ASM_CACHE_H */ diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index b39def3f6e0..c454550eb0c 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -78,6 +78,7 @@ struct cpuinfo_mips { unsigned int watch_reg_use_cnt; /* Usable by ptrace */ #define NUM_WATCH_REGS 4 u16 watch_reg_masks[NUM_WATCH_REGS]; + unsigned int kscratch_mask; /* Usable KScratch mask. */ } __attribute__((aligned(SMP_CACHE_BYTES))); extern struct cpuinfo_mips cpu_data[]; diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index 444ff71aa0e..7ebfc392e58 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -72,6 +72,7 @@ enum spec2_op { enum spec3_op { ext_op, dextm_op, dextu_op, dext_op, ins_op, dinsm_op, dinsu_op, dins_op, + lx_op = 0x0a, bshfl_op = 0x20, dbshfl_op = 0x24, rdhwr_op = 0x3b @@ -179,6 +180,19 @@ enum mad_func { }; /* + * func field for special3 lx opcodes (Cavium Octeon). + */ +enum lx_func { + lwx_op = 0x00, + lhx_op = 0x04, + lbux_op = 0x06, + ldx_op = 0x08, + lwux_op = 0x10, + lhux_op = 0x14, + lbx_op = 0x16, +}; + +/* * Damn ... bitfields depend from byteorder :-( */ #ifdef __MIPSEB__ diff --git a/arch/mips/include/asm/jump_label.h b/arch/mips/include/asm/jump_label.h new file mode 100644 index 00000000000..7622ccf7507 --- /dev/null +++ b/arch/mips/include/asm/jump_label.h @@ -0,0 +1,48 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2010 Cavium Networks, Inc. + */ +#ifndef _ASM_MIPS_JUMP_LABEL_H +#define _ASM_MIPS_JUMP_LABEL_H + +#include <linux/types.h> + +#ifdef __KERNEL__ + +#define JUMP_LABEL_NOP_SIZE 4 + +#ifdef CONFIG_64BIT +#define WORD_INSN ".dword" +#else +#define WORD_INSN ".word" +#endif + +#define JUMP_LABEL(key, label) \ + do { \ + asm goto("1:\tnop\n\t" \ + "nop\n\t" \ + ".pushsection __jump_table, \"a\"\n\t" \ + WORD_INSN " 1b, %l[" #label "], %0\n\t" \ + ".popsection\n\t" \ + : : "i" (key) : : label); \ + } while (0) + + +#endif /* __KERNEL__ */ + +#ifdef CONFIG_64BIT +typedef u64 jump_label_t; +#else +typedef u32 jump_label_t; +#endif + +struct jump_entry { + jump_label_t code; + jump_label_t target; + jump_label_t key; +}; + +#endif /* _ASM_MIPS_JUMP_LABEL_H */ diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h new file mode 100644 index 00000000000..cda1c8070b2 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -0,0 +1,233 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#include <linux/types.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/bitops.h> + +#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 + +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 + +#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + +/* + * DDR_CTRL block + */ +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +/* + * PLL block + */ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +/* + * RESET block + */ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_OHCI_DLL BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 + +#define AR913X_REV_ID_MINOR_MASK 0x3 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 +#define AR913X_REV_ID_REVISION_MASK 0x3 +#define AR913X_REV_ID_REVISION_SHIFT 2 + +#define AR724X_REV_ID_REVISION_MASK 0x3 + +/* + * SPI block + */ +#define AR71XX_SPI_REG_FS 0x00 /* Function Select */ +#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ +#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ +#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ + +#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ + +#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ +#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ + AR71XX_SPI_IOC_CS2) + +/* + * GPIO block + */ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 + +#define AR71XX_GPIO_COUNT 16 +#define AR724X_GPIO_COUNT 18 +#define AR913X_GPIO_COUNT 22 + +#endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h new file mode 100644 index 00000000000..6a9f168506f --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ath79.h @@ -0,0 +1,96 @@ +/* + * Atheros AR71XX/AR724X/AR913X common definitions + * + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_ATH79_H +#define __ASM_MACH_ATH79_H + +#include <linux/types.h> +#include <linux/io.h> + +enum ath79_soc_type { + ATH79_SOC_UNKNOWN, + ATH79_SOC_AR7130, + ATH79_SOC_AR7141, + ATH79_SOC_AR7161, + ATH79_SOC_AR7240, + ATH79_SOC_AR7241, + ATH79_SOC_AR7242, + ATH79_SOC_AR9130, + ATH79_SOC_AR9132 +}; + +extern enum ath79_soc_type ath79_soc; + +static inline int soc_is_ar71xx(void) +{ + return (ath79_soc == ATH79_SOC_AR7130 || + ath79_soc == ATH79_SOC_AR7141 || + ath79_soc == ATH79_SOC_AR7161); +} + +static inline int soc_is_ar724x(void) +{ + return (ath79_soc == ATH79_SOC_AR7240 || + ath79_soc == ATH79_SOC_AR7241 || + ath79_soc == ATH79_SOC_AR7242); +} + +static inline int soc_is_ar7240(void) +{ + return (ath79_soc == ATH79_SOC_AR7240); +} + +static inline int soc_is_ar7241(void) +{ + return (ath79_soc == ATH79_SOC_AR7241); +} + +static inline int soc_is_ar7242(void) +{ + return (ath79_soc == ATH79_SOC_AR7242); +} + +static inline int soc_is_ar913x(void) +{ + return (ath79_soc == ATH79_SOC_AR9130 || + ath79_soc == ATH79_SOC_AR9132); +} + +extern void __iomem *ath79_ddr_base; +extern void __iomem *ath79_pll_base; +extern void __iomem *ath79_reset_base; + +static inline void ath79_pll_wr(unsigned reg, u32 val) +{ + __raw_writel(val, ath79_pll_base + reg); +} + +static inline u32 ath79_pll_rr(unsigned reg) +{ + return __raw_readl(ath79_pll_base + reg); +} + +static inline void ath79_reset_wr(unsigned reg, u32 val) +{ + __raw_writel(val, ath79_reset_base + reg); +} + +static inline u32 ath79_reset_rr(unsigned reg) +{ + return __raw_readl(ath79_reset_base + reg); +} + +void ath79_device_reset_set(u32 mask); +void ath79_device_reset_clear(u32 mask); + +#endif /* __ASM_MACH_ATH79_H */ diff --git a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h new file mode 100644 index 00000000000..aa2283e602f --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h @@ -0,0 +1,23 @@ +/* + * Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_SPI_PLATFORM_H +#define _ATH79_SPI_PLATFORM_H + +struct ath79_spi_platform_data { + unsigned bus_num; + unsigned num_chipselect; +}; + +struct ath79_spi_controller_data { + unsigned gpio; +}; + +#endif /* _ATH79_SPI_PLATFORM_H */ diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h new file mode 100644 index 00000000000..4476fa03bf3 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h @@ -0,0 +1,56 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific CPU feature overrides + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-ath79/gpio.h b/arch/mips/include/asm/mach-ath79/gpio.h new file mode 100644 index 00000000000..60dcb62785b --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/gpio.h @@ -0,0 +1,26 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO API definitions + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __ASM_MACH_ATH79_GPIO_H +#define __ASM_MACH_ATH79_GPIO_H + +#define ARCH_NR_GPIOS 64 +#include <asm-generic/gpio.h> + +int gpio_to_irq(unsigned gpio); +int irq_to_gpio(unsigned irq); +int gpio_get_value(unsigned gpio); +void gpio_set_value(unsigned gpio, int value); + +#define gpio_cansleep __gpio_cansleep + +#endif /* __ASM_MACH_ATH79_GPIO_H */ diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h new file mode 100644 index 00000000000..189bc6eb9c1 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ +#ifndef __ASM_MACH_ATH79_IRQ_H +#define __ASM_MACH_ATH79_IRQ_H + +#define MIPS_CPU_IRQ_BASE 0 +#define NR_IRQS 16 + +#define ATH79_MISC_IRQ_BASE 8 +#define ATH79_MISC_IRQ_COUNT 8 + +#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) +#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) +#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) +#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5) +#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) +#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7) + +#define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0) +#define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1) +#define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2) +#define ATH79_MISC_IRQ_UART (ATH79_MISC_IRQ_BASE + 3) +#define ATH79_MISC_IRQ_WDOG (ATH79_MISC_IRQ_BASE + 4) +#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5) +#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6) +#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7) + +#include_next <irq.h> + +#endif /* __ASM_MACH_ATH79_IRQ_H */ diff --git a/arch/mips/include/asm/mach-ath79/kernel-entry-init.h b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h new file mode 100644 index 00000000000..d8d046bccc8 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h @@ -0,0 +1,32 @@ +/* + * Atheros AR71XX/AR724X/AR913X specific kernel entry setup + * + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_ATH79_KERNEL_ENTRY_H +#define __ASM_MACH_ATH79_KERNEL_ENTRY_H + + /* + * Some bootloaders set the 'Kseg0 coherency algorithm' to + * 'Cacheable, noncoherent, write-through, no write allocate' + * and this cause performance issues. Let's go and change it to + * 'Cacheable, noncoherent, write-back, write allocate' + */ + .macro kernel_entry_setup + mfc0 t0, CP0_CONFIG + li t1, ~CONF_CM_CMASK + and t0, t1 + ori t0, CONF_CM_CACHABLE_NONCOHERENT + mtc0 t0, CP0_CONFIG + nop + .endm + + .macro smp_slave_setup + .endm + +#endif /* __ASM_MACH_ATH79_KERNEL_ENTRY_H */ diff --git a/arch/mips/include/asm/mach-ath79/war.h b/arch/mips/include/asm/mach-ath79/war.h new file mode 100644 index 00000000000..323d9f1d8c4 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MACH_ATH79_WAR_H +#define __ASM_MACH_ATH79_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_ATH79_WAR_H */ diff --git a/arch/mips/include/asm/mips_machine.h b/arch/mips/include/asm/mips_machine.h new file mode 100644 index 00000000000..363bb352c7f --- /dev/null +++ b/arch/mips/include/asm/mips_machine.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __ASM_MIPS_MACHINE_H +#define __ASM_MIPS_MACHINE_H + +#include <linux/init.h> +#include <linux/stddef.h> + +#include <asm/bootinfo.h> + +struct mips_machine { + unsigned long mach_type; + const char *mach_id; + const char *mach_name; + void (*mach_setup)(void); +}; + +#define MIPS_MACHINE(_type, _id, _name, _setup) \ +static const char machine_name_##_type[] __initconst \ + __aligned(1) = _name; \ +static const char machine_id_##_type[] __initconst \ + __aligned(1) = _id; \ +static struct mips_machine machine_##_type \ + __used __section(.mips.machines.init) = \ +{ \ + .mach_type = _type, \ + .mach_id = machine_id_##_type, \ + .mach_name = machine_name_##_type, \ + .mach_setup = _setup, \ +}; + +extern long __mips_machines_start; +extern long __mips_machines_end; + +#ifdef CONFIG_MIPS_MACHINE +int mips_machtype_setup(char *id) __init; +void mips_machine_setup(void) __init; +void mips_set_machine_name(const char *name) __init; +char *mips_get_machine_name(void); +#else +static inline int mips_machtype_setup(char *id) { return 1; } +static inline void mips_machine_setup(void) { } +static inline void mips_set_machine_name(const char *name) { } +static inline char *mips_get_machine_name(void) { return NULL; } +#endif /* CONFIG_MIPS_MACHINE */ + +#endif /* __ASM_MIPS_MACHINE_H */ diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index d9592733a7b..73c0d45798d 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -29,13 +29,7 @@ #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ tlbmiss_handler_setup_pgd((unsigned long)(pgd)) -static inline void tlbmiss_handler_setup_pgd(unsigned long pgd) -{ - /* Check for swapper_pg_dir and convert to physical address. */ - if ((pgd & CKSEG3) == CKSEG0) - pgd = CPHYSADDR(pgd); - write_c0_context(pgd << 11); -} +extern void tlbmiss_handler_setup_pgd(unsigned long pgd); #define TLBMISS_HANDLER_SETUP() \ do { \ diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 892062d6d74..dcbd4bb417e 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -115,7 +115,12 @@ Ip_0(_tlbwr); Ip_u3u1u2(_xor); Ip_u2u1u3(_xori); Ip_u2u1msbu3(_dins); +Ip_u2u1msbu3(_dinsm); Ip_u1(_syscall); +Ip_u1u2s3(_bbit0); +Ip_u1u2s3(_bbit1); +Ip_u3u1u2(_lwx); +Ip_u3u1u2(_ldx); /* Handle labels. */ struct uasm_label { @@ -153,6 +158,7 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ # define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd) # define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off) # define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off) +# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd) #else # define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off) # define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off) @@ -167,6 +173,7 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ # define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd) # define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off) # define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off) +# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd) #endif #define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off) diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 22b2e0e3861..cedee2bcbd1 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_GPIO_TXX9) += gpio_txx9.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o +obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o obj-$(CONFIG_OF) += prom.o @@ -106,4 +107,6 @@ obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o +obj-$(CONFIG_JUMP_LABEL) += jump_label.o + CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 68dae7b6b5d..f65d4c8c65a 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -739,6 +739,8 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c) && cpu_has_tlb) c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; + c->kscratch_mask = (config4 >> 16) & 0xff; + return config4 & MIPS_CONF_M; } diff --git a/arch/mips/kernel/jump_label.c b/arch/mips/kernel/jump_label.c new file mode 100644 index 00000000000..6001610cfe5 --- /dev/null +++ b/arch/mips/kernel/jump_label.c @@ -0,0 +1,54 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2010 Cavium Networks, Inc. + */ + +#include <linux/jump_label.h> +#include <linux/kernel.h> +#include <linux/memory.h> +#include <linux/mutex.h> +#include <linux/types.h> +#include <linux/cpu.h> + +#include <asm/cacheflush.h> +#include <asm/inst.h> + +#ifdef HAVE_JUMP_LABEL + +#define J_RANGE_MASK ((1ul << 28) - 1) + +void arch_jump_label_transform(struct jump_entry *e, + enum jump_label_type type) +{ + union mips_instruction insn; + union mips_instruction *insn_p = + (union mips_instruction *)(unsigned long)e->code; + + /* Jump only works within a 256MB aligned region. */ + BUG_ON((e->target & ~J_RANGE_MASK) != (e->code & ~J_RANGE_MASK)); + + /* Target must have 4 byte alignment. */ + BUG_ON((e->target & 3) != 0); + + if (type == JUMP_LABEL_ENABLE) { + insn.j_format.opcode = j_op; + insn.j_format.target = (e->target & J_RANGE_MASK) >> 2; + } else { + insn.word = 0; /* nop */ + } + + get_online_cpus(); + mutex_lock(&text_mutex); + *insn_p = insn; + + flush_icache_range((unsigned long)insn_p, + (unsigned long)insn_p + sizeof(*insn_p)); + + mutex_unlock(&text_mutex); + put_online_cpus(); +} + +#endif /* HAVE_JUMP_LABEL */ diff --git a/arch/mips/kernel/mips_machine.c b/arch/mips/kernel/mips_machine.c new file mode 100644 index 00000000000..411a058d2c5 --- /dev/null +++ b/arch/mips/kernel/mips_machine.c @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#include <linux/mm.h> +#include <linux/string.h> +#include <linux/slab.h> + +#include <asm/mips_machine.h> + +static struct mips_machine *mips_machine __initdata; +static char *mips_machine_name = "Unknown"; + +#define for_each_machine(mach) \ + for ((mach) = (struct mips_machine *)&__mips_machines_start; \ + (mach) && \ + (unsigned long)(mach) < (unsigned long)&__mips_machines_end; \ + (mach)++) + +__init void mips_set_machine_name(const char *name) +{ + char *p; + + if (name == NULL) + return; + + p = kstrdup(name, GFP_KERNEL); + if (!p) + pr_err("MIPS: no memory for machine_name\n"); + + mips_machine_name = p; +} + +char *mips_get_machine_name(void) +{ + return mips_machine_name; +} + +__init int mips_machtype_setup(char *id) +{ + struct mips_machine *mach; + + for_each_machine(mach) { + if (mach->mach_id == NULL) + continue; + + if (strcmp(mach->mach_id, id) == 0) { + mips_machtype = mach->mach_type; + return 0; + } + } + + pr_err("MIPS: no machine found for id '%s', supported machines:\n", id); + pr_err("%-24s %s\n", "id", "name"); + for_each_machine(mach) + pr_err("%-24s %s\n", mach->mach_id, mach->mach_name); + + return 1; +} + +__setup("machtype=", mips_machtype_setup); + +__init void mips_machine_setup(void) +{ + struct mips_machine *mach; + + for_each_machine(mach) { + if (mips_machtype == mach->mach_type) { + mips_machine = mach; + break; + } + } + + if (!mips_machine) + return; + + mips_set_machine_name(mips_machine->mach_name); + pr_info("MIPS: machine is %s\n", mips_machine_name); + + if (mips_machine->mach_setup) + mips_machine->mach_setup(); +} diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c index d87a72e9fac..dd940b70196 100644 --- a/arch/mips/kernel/module.c +++ b/arch/mips/kernel/module.c @@ -30,6 +30,8 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/spinlock.h> +#include <linux/jump_label.h> + #include <asm/pgtable.h> /* MODULE_START */ struct mips_hi16 { @@ -382,6 +384,9 @@ int module_finalize(const Elf_Ehdr *hdr, const Elf_Shdr *s; char *secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; + /* Make jump label nops. */ + jump_label_apply_nops(me); + INIT_LIST_HEAD(&me->arch.dbe_list); for (s = sechdrs; s < sechdrs + hdr->e_shnum; s++) { if (strcmp("__dbe_table", secstrings + s->sh_name) != 0) diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 26109c4d517..e309665b6c8 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -12,6 +12,7 @@ #include <asm/cpu-features.h> #include <asm/mipsregs.h> #include <asm/processor.h> +#include <asm/mips_machine.h> unsigned int vced_count, vcei_count; @@ -31,8 +32,12 @@ static int show_cpuinfo(struct seq_file *m, void *v) /* * For the first processor also print the system type */ - if (n == 0) + if (n == 0) { seq_printf(m, "system type\t\t: %s\n", get_system_type()); + if (mips_get_machine_name()) + seq_printf(m, "machine\t\t\t: %s\n", + mips_get_machine_name()); + } seq_printf(m, "processor\t\t: %ld\n", n); sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", @@ -69,6 +74,8 @@ static int show_cpuinfo(struct seq_file *m, void *v) ); seq_printf(m, "shadow register sets\t: %d\n", cpu_data[n].srsets); + seq_printf(m, "kscratch registers\t: %d\n", + hweight8(cpu_data[n].kscratch_mask)); seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index 9dbe5836895..a19811e98a4 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -45,11 +45,9 @@ void __init free_mem_mach(unsigned long addr, unsigned long size) return free_bootmem(addr, size); } -u64 __init early_init_dt_alloc_memory_arch(u64 size, u64 align) +void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) { - return virt_to_phys( - __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS)) - ); + return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS)); } #ifdef CONFIG_BLK_DEV_INITRD diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index acd3f2c49c0..8ad1d5679f1 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -70,7 +70,7 @@ static char __initdata builtin_cmdline[COMMAND_LINE_SIZE] = CONFIG_CMDLINE; * mips_io_port_base is the begin of the address space to which x86 style * I/O ports are mapped. */ -const unsigned long mips_io_port_base __read_mostly = -1; +const unsigned long mips_io_port_base = -1; EXPORT_SYMBOL(mips_io_port_base); static struct resource code_resource = { .name = "Kernel code", }; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index e9710430254..71350f7f2d8 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1592,7 +1592,6 @@ void __cpuinit per_cpu_trap_init(void) #endif /* CONFIG_MIPS_MT_SMTC */ cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; - TLBMISS_HANDLER_SETUP(); atomic_inc(&init_mm.mm_count); current->active_mm = &init_mm; @@ -1614,6 +1613,7 @@ void __cpuinit per_cpu_trap_init(void) write_c0_wired(0); } #endif /* CONFIG_MIPS_MT_SMTC */ + TLBMISS_HANDLER_SETUP(); } /* Install CPU exception handler */ diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index f25df73db92..570607b376b 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -98,6 +98,13 @@ SECTIONS INIT_TEXT_SECTION(PAGE_SIZE) INIT_DATA_SECTION(16) + . = ALIGN(4); + .mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) { + __mips_machines_start = .; + *(.mips.machines.init) + __mips_machines_end = .; + } + /* .exit.text is discarded at runtime, not link time, to deal with * references from .rodata */ diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 93816f3bca6..083d3412d0b 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -26,8 +26,10 @@ #include <linux/smp.h> #include <linux/string.h> #include <linux/init.h> +#include <linux/cache.h> -#include <asm/mmu_context.h> +#include <asm/cacheflush.h> +#include <asm/pgtable.h> #include <asm/war.h> #include <asm/uasm.h> @@ -63,6 +65,52 @@ static inline int __maybe_unused r10000_llsc_war(void) return R10000_LLSC_WAR; } +static int use_bbit_insns(void) +{ + switch (current_cpu_type()) { + case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: + case CPU_CAVIUM_OCTEON2: + return 1; + default: + return 0; + } +} + +static int use_lwx_insns(void) +{ + switch (current_cpu_type()) { + case CPU_CAVIUM_OCTEON2: + return 1; + default: + return 0; + } +} +#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ + CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 +static bool scratchpad_available(void) +{ + return true; +} +static int scratchpad_offset(int i) +{ + /* + * CVMSEG starts at address -32768 and extends for + * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. + */ + i += 1; /* Kernel use starts at the top and works down. */ + return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; +} +#else +static bool scratchpad_available(void) +{ + return false; +} +static int scratchpad_offset(int i) +{ + BUG(); +} +#endif /* * Found by experiment: At least some revisions of the 4kc throw under * some circumstances a machine check exception, triggered by invalid @@ -173,11 +221,41 @@ static struct uasm_reloc relocs[128] __cpuinitdata; static int check_for_high_segbits __cpuinitdata; #endif +static int check_for_high_segbits __cpuinitdata; + +static unsigned int kscratch_used_mask __cpuinitdata; + +static int __cpuinit allocate_kscratch(void) +{ + int r; + unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; + + r = ffs(a); + + if (r == 0) + return -1; + + r--; /* make it zero based */ + + kscratch_used_mask |= (1 << r); + + return r; +} + +static int scratch_reg __cpuinitdata; +static int pgd_reg __cpuinitdata; +enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; + #ifndef CONFIG_MIPS_PGD_C0_CONTEXT + /* * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, * we cannot do r3000 under these circumstances. + * + * Declare pgd_current here instead of including mmu_context.h to avoid type + * conflicts for tlbmiss_handler_setup_pgd */ +extern unsigned long pgd_current[]; /* * The R3000 TLB handler is simple. @@ -440,21 +518,43 @@ static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, static __cpuinit void build_restore_pagemask(u32 **p, struct uasm_reloc **r, unsigned int tmp, - enum label_id lid) + enum label_id lid, + int restore_scratch) { - /* Reset default page size */ - if (PM_DEFAULT_MASK >> 16) { - uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); - uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); - uasm_il_b(p, r, lid); - uasm_i_mtc0(p, tmp, C0_PAGEMASK); - } else if (PM_DEFAULT_MASK) { - uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); - uasm_il_b(p, r, lid); - uasm_i_mtc0(p, tmp, C0_PAGEMASK); + if (restore_scratch) { + /* Reset default page size */ + if (PM_DEFAULT_MASK >> 16) { + uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); + uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); + uasm_i_mtc0(p, tmp, C0_PAGEMASK); + uasm_il_b(p, r, lid); + } else if (PM_DEFAULT_MASK) { + uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); + uasm_i_mtc0(p, tmp, C0_PAGEMASK); + uasm_il_b(p, r, lid); + } else { + uasm_i_mtc0(p, 0, C0_PAGEMASK); + uasm_il_b(p, r, lid); + } + if (scratch_reg > 0) + UASM_i_MFC0(p, 1, 31, scratch_reg); + else + UASM_i_LW(p, 1, scratchpad_offset(0), 0); } else { - uasm_il_b(p, r, lid); - uasm_i_mtc0(p, 0, C0_PAGEMASK); + /* Reset default page size */ + if (PM_DEFAULT_MASK >> 16) { + uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); + uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); + uasm_il_b(p, r, lid); + uasm_i_mtc0(p, tmp, C0_PAGEMASK); + } else if (PM_DEFAULT_MASK) { + uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); + uasm_il_b(p, r, lid); + uasm_i_mtc0(p, tmp, C0_PAGEMASK); + } else { + uasm_il_b(p, r, lid); + uasm_i_mtc0(p, 0, C0_PAGEMASK); + } } } @@ -462,7 +562,8 @@ static __cpuinit void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, struct uasm_reloc **r, unsigned int tmp, - enum tlb_write_entry wmode) + enum tlb_write_entry wmode, + int restore_scratch) { /* Set huge page tlb entry size */ uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); @@ -471,7 +572,7 @@ static __cpuinit void build_huge_tlb_write_entry(u32 **p, build_tlb_write_entry(p, l, r, wmode); - build_restore_pagemask(p, r, tmp, label_leave); + build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); } /* @@ -482,8 +583,12 @@ build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, unsigned int pmd, int lid) { UASM_i_LW(p, tmp, 0, pmd); - uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); - uasm_il_bnez(p, r, tmp, lid); + if (use_bbit_insns()) { + uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); + } else { + uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); + uasm_il_bnez(p, r, tmp, lid); + } } static __cpuinit void build_huge_update_entries(u32 **p, @@ -532,7 +637,7 @@ static __cpuinit void build_huge_handler_tail(u32 **p, UASM_i_SW(p, pte, 0, ptr); #endif build_huge_update_entries(p, pte, ptr); - build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed); + build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); } #endif /* CONFIG_HUGETLB_PAGE */ @@ -573,13 +678,22 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ #ifdef CONFIG_MIPS_PGD_C0_CONTEXT - /* - * &pgd << 11 stored in CONTEXT [23..63]. - */ - UASM_i_MFC0(p, ptr, C0_CONTEXT); - uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */ - uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */ - uasm_i_drotr(p, ptr, ptr, 11); + if (pgd_reg != -1) { + /* pgd is in pgd_reg */ + UASM_i_MFC0(p, ptr, 31, pgd_reg); + } else { + /* + * &pgd << 11 stored in CONTEXT [23..63]. + */ + UASM_i_MFC0(p, ptr, C0_CONTEXT); + + /* Clear lower 23 bits of context. */ + uasm_i_dins(p, ptr, 0, 0, 23); + + /* 1 0 1 0 1 << 6 xkphys cached */ + uasm_i_ori(p, ptr, ptr, 0x540); + uasm_i_drotr(p, ptr, ptr, 11); + } #elif defined(CONFIG_SMP) # ifdef CONFIG_MIPS_MT_SMTC /* @@ -620,7 +734,6 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, #endif } -enum vmalloc64_mode {not_refill, refill}; /* * BVADDR is the faulting address, PTR is scratch. * PTR will hold the pgd for vmalloc. @@ -638,7 +751,7 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, uasm_l_vmalloc(l, *p); - if (mode == refill && check_for_high_segbits) { + if (mode != not_refill && check_for_high_segbits) { if (single_insn_swpd) { uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); @@ -661,7 +774,7 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); } } - if (mode == refill && check_for_high_segbits) { + if (mode != not_refill && check_for_high_segbits) { uasm_l_large_segbits_fault(l, *p); /* * We get here if we are an xsseg address, or if we are @@ -677,7 +790,15 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, */ UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); uasm_i_jr(p, ptr); - uasm_i_nop(p); + + if (mode == refill_scratch) { + if (scratch_reg > 0) + UASM_i_MFC0(p, 1, 31, scratch_reg); + else + UASM_i_LW(p, 1, scratchpad_offset(0), 0); + } else { + uasm_i_nop(p); + } } } @@ -834,6 +955,185 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, #endif } +struct mips_huge_tlb_info { + int huge_pte; + int restore_scratch; +}; + +static struct mips_huge_tlb_info __cpuinit +build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, + struct uasm_reloc **r, unsigned int tmp, + unsigned int ptr, int c0_scratch) +{ + struct mips_huge_tlb_info rv; + unsigned int even, odd; + int vmalloc_branch_delay_filled = 0; + const int scratch = 1; /* Our extra working register */ + + rv.huge_pte = scratch; + rv.restore_scratch = 0; + + if (check_for_high_segbits) { + UASM_i_MFC0(p, tmp, C0_BADVADDR); + + if (pgd_reg != -1) + UASM_i_MFC0(p, ptr, 31, pgd_reg); + else + UASM_i_MFC0(p, ptr, C0_CONTEXT); + + if (c0_scratch >= 0) + UASM_i_MTC0(p, scratch, 31, c0_scratch); + else + UASM_i_SW(p, scratch, scratchpad_offset(0), 0); + + uasm_i_dsrl_safe(p, scratch, tmp, + PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); + uasm_il_bnez(p, r, scratch, label_vmalloc); + + if (pgd_reg == -1) { + vmalloc_branch_delay_filled = 1; + /* Clear lower 23 bits of context. */ + uasm_i_dins(p, ptr, 0, 0, 23); + } + } else { + if (pgd_reg != -1) + UASM_i_MFC0(p, ptr, 31, pgd_reg); + else + UASM_i_MFC0(p, ptr, C0_CONTEXT); + + UASM_i_MFC0(p, tmp, C0_BADVADDR); + + if (c0_scratch >= 0) + UASM_i_MTC0(p, scratch, 31, c0_scratch); + else + UASM_i_SW(p, scratch, scratchpad_offset(0), 0); + + if (pgd_reg == -1) + /* Clear lower 23 bits of context. */ + uasm_i_dins(p, ptr, 0, 0, 23); + + uasm_il_bltz(p, r, tmp, label_vmalloc); + } + + if (pgd_reg == -1) { + vmalloc_branch_delay_filled = 1; + /* 1 0 1 0 1 << 6 xkphys cached */ + uasm_i_ori(p, ptr, ptr, 0x540); + uasm_i_drotr(p, ptr, ptr, 11); + } + +#ifdef __PAGETABLE_PMD_FOLDED +#define LOC_PTEP scratch +#else +#define LOC_PTEP ptr +#endif + + if (!vmalloc_branch_delay_filled) + /* get pgd offset in bytes */ + uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); + + uasm_l_vmalloc_done(l, *p); + + /* + * tmp ptr + * fall-through case = badvaddr *pgd_current + * vmalloc case = badvaddr swapper_pg_dir + */ + + if (vmalloc_branch_delay_filled) + /* get pgd offset in bytes */ + uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); + +#ifdef __PAGETABLE_PMD_FOLDED + GET_CONTEXT(p, tmp); /* get context reg */ +#endif + uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); + + if (use_lwx_insns()) { + UASM_i_LWX(p, LOC_PTEP, scratch, ptr); + } else { + uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ + uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ + } + +#ifndef __PAGETABLE_PMD_FOLDED + /* get pmd offset in bytes */ + uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); + uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); + GET_CONTEXT(p, tmp); /* get context reg */ + + if (use_lwx_insns()) { + UASM_i_LWX(p, scratch, scratch, ptr); + } else { + uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ + UASM_i_LW(p, scratch, 0, ptr); + } +#endif + /* Adjust the context during the load latency. */ + build_adjust_context(p, tmp); + +#ifdef CONFIG_HUGETLB_PAGE + uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); + /* + * The in the LWX case we don't want to do the load in the + * delay slot. It cannot issue in the same cycle and may be + * speculative and unneeded. + */ + if (use_lwx_insns()) + uasm_i_nop(p); +#endif /* CONFIG_HUGETLB_PAGE */ + + + /* build_update_entries */ + if (use_lwx_insns()) { + even = ptr; + odd = tmp; + UASM_i_LWX(p, even, scratch, tmp); + UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); + UASM_i_LWX(p, odd, scratch, tmp); + } else { + UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ + even = tmp; + odd = ptr; + UASM_i_LW(p, even, 0, ptr); /* get even pte */ + UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ + } + if (kernel_uses_smartmips_rixi) { + uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_NO_EXEC)); + uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_NO_EXEC)); + uasm_i_drotr(p, even, even, + ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); + UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ + uasm_i_drotr(p, odd, odd, + ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); + } else { + uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); + UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ + uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); + } + UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ + + if (c0_scratch >= 0) { + UASM_i_MFC0(p, scratch, 31, c0_scratch); + build_tlb_write_entry(p, l, r, tlb_random); + uasm_l_leave(l, *p); + rv.restore_scratch = 1; + } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { + build_tlb_write_entry(p, l, r, tlb_random); + uasm_l_leave(l, *p); + UASM_i_LW(p, scratch, scratchpad_offset(0), 0); + } else { + UASM_i_LW(p, scratch, scratchpad_offset(0), 0); + build_tlb_write_entry(p, l, r, tlb_random); + uasm_l_leave(l, *p); + rv.restore_scratch = 1; + } + + uasm_i_eret(p); /* return from trap */ + + return rv; +} + /* * For a 64-bit kernel, we are using the 64-bit XTLB refill exception * because EXL == 0. If we wrap, we can also use the 32 instruction @@ -849,54 +1149,67 @@ static void __cpuinit build_r4000_tlb_refill_handler(void) struct uasm_reloc *r = relocs; u32 *f; unsigned int final_len; + struct mips_huge_tlb_info htlb_info; + enum vmalloc64_mode vmalloc_mode; memset(tlb_handler, 0, sizeof(tlb_handler)); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); memset(final_handler, 0, sizeof(final_handler)); - /* - * create the plain linear handler - */ - if (bcm1250_m3_war()) { - unsigned int segbits = 44; + if (scratch_reg == 0) + scratch_reg = allocate_kscratch(); - uasm_i_dmfc0(&p, K0, C0_BADVADDR); - uasm_i_dmfc0(&p, K1, C0_ENTRYHI); - uasm_i_xor(&p, K0, K0, K1); - uasm_i_dsrl_safe(&p, K1, K0, 62); - uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); - uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); - uasm_i_or(&p, K0, K0, K1); - uasm_il_bnez(&p, &r, K0, label_leave); - /* No need for uasm_i_nop */ - } + if ((scratch_reg > 0 || scratchpad_available()) && use_bbit_insns()) { + htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, + scratch_reg); + vmalloc_mode = refill_scratch; + } else { + htlb_info.huge_pte = K0; + htlb_info.restore_scratch = 0; + vmalloc_mode = refill_noscratch; + /* + * create the plain linear handler + */ + if (bcm1250_m3_war()) { + unsigned int segbits = 44; + + uasm_i_dmfc0(&p, K0, C0_BADVADDR); + uasm_i_dmfc0(&p, K1, C0_ENTRYHI); + uasm_i_xor(&p, K0, K0, K1); + uasm_i_dsrl_safe(&p, K1, K0, 62); + uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); + uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); + uasm_i_or(&p, K0, K0, K1); + uasm_il_bnez(&p, &r, K0, label_leave); + /* No need for uasm_i_nop */ + } #ifdef CONFIG_64BIT - build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ + build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ #else - build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ + build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ #endif #ifdef CONFIG_HUGETLB_PAGE - build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); + build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); #endif - build_get_ptep(&p, K0, K1); - build_update_entries(&p, K0, K1); - build_tlb_write_entry(&p, &l, &r, tlb_random); - uasm_l_leave(&l, p); - uasm_i_eret(&p); /* return from trap */ - + build_get_ptep(&p, K0, K1); + build_update_entries(&p, K0, K1); + build_tlb_write_entry(&p, &l, &r, tlb_random); + uasm_l_leave(&l, p); + uasm_i_eret(&p); /* return from trap */ + } #ifdef CONFIG_HUGETLB_PAGE uasm_l_tlb_huge_update(&l, p); - UASM_i_LW(&p, K0, 0, K1); - build_huge_update_entries(&p, K0, K1); - build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random); + build_huge_update_entries(&p, htlb_info.huge_pte, K1); + build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, + htlb_info.restore_scratch); #endif #ifdef CONFIG_64BIT - build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, refill); + build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); #endif /* @@ -1014,6 +1327,55 @@ static void __cpuinit build_r4000_tlb_refill_handler(void) u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT +u32 tlbmiss_handler_setup_pgd[16] __cacheline_aligned; + +static void __cpuinit build_r4000_setup_pgd(void) +{ + const int a0 = 4; + const int a1 = 5; + u32 *p = tlbmiss_handler_setup_pgd; + struct uasm_label *l = labels; + struct uasm_reloc *r = relocs; + + memset(tlbmiss_handler_setup_pgd, 0, sizeof(tlbmiss_handler_setup_pgd)); + memset(labels, 0, sizeof(labels)); + memset(relocs, 0, sizeof(relocs)); + + pgd_reg = allocate_kscratch(); + + if (pgd_reg == -1) { + /* PGD << 11 in c0_Context */ + /* + * If it is a ckseg0 address, convert to a physical + * address. Shifting right by 29 and adding 4 will + * result in zero for these addresses. + * + */ + UASM_i_SRA(&p, a1, a0, 29); + UASM_i_ADDIU(&p, a1, a1, 4); + uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); + uasm_i_nop(&p); + uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); + uasm_l_tlbl_goaround1(&l, p); + UASM_i_SLL(&p, a0, a0, 11); + uasm_i_jr(&p, 31); + UASM_i_MTC0(&p, a0, C0_CONTEXT); + } else { + /* PGD in c0_KScratch */ + uasm_i_jr(&p, 31); + UASM_i_MTC0(&p, a0, 31, pgd_reg); + } + if (p - tlbmiss_handler_setup_pgd > ARRAY_SIZE(tlbmiss_handler_setup_pgd)) + panic("tlbmiss_handler_setup_pgd space exceeded"); + uasm_resolve_relocs(relocs, labels); + pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", + (unsigned int)(p - tlbmiss_handler_setup_pgd)); + + dump_handler(tlbmiss_handler_setup_pgd, + ARRAY_SIZE(tlbmiss_handler_setup_pgd)); +} +#endif static void __cpuinit iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) @@ -1100,14 +1462,20 @@ build_pte_present(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, enum label_id lid) { if (kernel_uses_smartmips_rixi) { - uasm_i_andi(p, pte, pte, _PAGE_PRESENT); - uasm_il_beqz(p, r, pte, lid); + if (use_bbit_insns()) { + uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); + uasm_i_nop(p); + } else { + uasm_i_andi(p, pte, pte, _PAGE_PRESENT); + uasm_il_beqz(p, r, pte, lid); + iPTE_LW(p, pte, ptr); + } } else { uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); uasm_il_bnez(p, r, pte, lid); + iPTE_LW(p, pte, ptr); } - iPTE_LW(p, pte, ptr); } /* Make PTE valid, store result in PTR. */ @@ -1128,10 +1496,17 @@ static void __cpuinit build_pte_writable(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, enum label_id lid) { - uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); - uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); - uasm_il_bnez(p, r, pte, lid); - iPTE_LW(p, pte, ptr); + if (use_bbit_insns()) { + uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); + uasm_i_nop(p); + uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); + uasm_i_nop(p); + } else { + uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); + uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); + uasm_il_bnez(p, r, pte, lid); + iPTE_LW(p, pte, ptr); + } } /* Make PTE writable, update software status bits as well, then store @@ -1155,12 +1530,19 @@ static void __cpuinit build_pte_modifiable(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, enum label_id lid) { - uasm_i_andi(p, pte, pte, _PAGE_WRITE); - uasm_il_beqz(p, r, pte, lid); - iPTE_LW(p, pte, ptr); + if (use_bbit_insns()) { + uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); + uasm_i_nop(p); + } else { + uasm_i_andi(p, pte, pte, _PAGE_WRITE); + uasm_il_beqz(p, r, pte, lid); + iPTE_LW(p, pte, ptr); + } } #ifndef CONFIG_MIPS_PGD_C0_CONTEXT + + /* * R3000 style TLB load/store/modify handlers. */ @@ -1402,14 +1784,23 @@ static void __cpuinit build_r4000_tlb_load_handler(void) * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. */ - uasm_i_andi(&p, K0, K0, _PAGE_VALID); - uasm_il_beqz(&p, &r, K0, label_tlbl_goaround1); + if (use_bbit_insns()) { + uasm_il_bbit0(&p, &r, K0, ilog2(_PAGE_VALID), + label_tlbl_goaround1); + } else { + uasm_i_andi(&p, K0, K0, _PAGE_VALID); + uasm_il_beqz(&p, &r, K0, label_tlbl_goaround1); + } uasm_i_nop(&p); uasm_i_tlbr(&p); /* Examine entrylo 0 or 1 based on ptr. */ - uasm_i_andi(&p, K0, K1, sizeof(pte_t)); - uasm_i_beqz(&p, K0, 8); + if (use_bbit_insns()) { + uasm_i_bbit0(&p, K1, ilog2(sizeof(pte_t)), 8); + } else { + uasm_i_andi(&p, K0, K1, sizeof(pte_t)); + uasm_i_beqz(&p, K0, 8); + } UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/ UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */ @@ -1417,12 +1808,18 @@ static void __cpuinit build_r4000_tlb_load_handler(void) * If the entryLo (now in K0) is valid (bit 1), RI or * XI must have triggered it. */ - uasm_i_andi(&p, K0, K0, 2); - uasm_il_bnez(&p, &r, K0, label_nopage_tlbl); - - uasm_l_tlbl_goaround1(&l, p); - /* Reload the PTE value */ - iPTE_LW(&p, K0, K1); + if (use_bbit_insns()) { + uasm_il_bbit1(&p, &r, K0, 1, label_nopage_tlbl); + /* Reload the PTE value */ + iPTE_LW(&p, K0, K1); + uasm_l_tlbl_goaround1(&l, p); + } else { + uasm_i_andi(&p, K0, K0, 2); + uasm_il_bnez(&p, &r, K0, label_nopage_tlbl); + uasm_l_tlbl_goaround1(&l, p); + /* Reload the PTE value */ + iPTE_LW(&p, K0, K1); + } } build_make_valid(&p, &r, K0, K1); build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); @@ -1442,23 +1839,35 @@ static void __cpuinit build_r4000_tlb_load_handler(void) * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. */ - uasm_i_andi(&p, K0, K0, _PAGE_VALID); - uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); + if (use_bbit_insns()) { + uasm_il_bbit0(&p, &r, K0, ilog2(_PAGE_VALID), + label_tlbl_goaround2); + } else { + uasm_i_andi(&p, K0, K0, _PAGE_VALID); + uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); + } uasm_i_nop(&p); uasm_i_tlbr(&p); /* Examine entrylo 0 or 1 based on ptr. */ - uasm_i_andi(&p, K0, K1, sizeof(pte_t)); - uasm_i_beqz(&p, K0, 8); - + if (use_bbit_insns()) { + uasm_i_bbit0(&p, K1, ilog2(sizeof(pte_t)), 8); + } else { + uasm_i_andi(&p, K0, K1, sizeof(pte_t)); + uasm_i_beqz(&p, K0, 8); + } UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/ UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */ /* * If the entryLo (now in K0) is valid (bit 1), RI or * XI must have triggered it. */ - uasm_i_andi(&p, K0, K0, 2); - uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); + if (use_bbit_insns()) { + uasm_il_bbit0(&p, &r, K0, 1, label_tlbl_goaround2); + } else { + uasm_i_andi(&p, K0, K0, 2); + uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); + } /* Reload the PTE value */ iPTE_LW(&p, K0, K1); @@ -1466,7 +1875,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void) * We clobbered C0_PAGEMASK, restore it. On the other branch * it is restored in build_huge_tlb_write_entry. */ - build_restore_pagemask(&p, &r, K0, label_nopage_tlbl); + build_restore_pagemask(&p, &r, K0, label_nopage_tlbl, 0); uasm_l_tlbl_goaround2(&l, p); } @@ -1623,13 +2032,16 @@ void __cpuinit build_tlb_refill_handler(void) break; default: - build_r4000_tlb_refill_handler(); if (!run_once) { +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT + build_r4000_setup_pgd(); +#endif build_r4000_tlb_load_handler(); build_r4000_tlb_store_handler(); build_r4000_tlb_modify_handler(); run_once++; } + build_r4000_tlb_refill_handler(); } } @@ -1641,4 +2053,8 @@ void __cpuinit flush_tlb_handlers(void) (unsigned long)handle_tlbs + sizeof(handle_tlbs)); local_flush_icache_range((unsigned long)handle_tlbm, (unsigned long)handle_tlbm + sizeof(handle_tlbm)); +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT + local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, + (unsigned long)tlbmiss_handler_setup_pgd + sizeof(handle_tlbm)); +#endif } diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 23afdebc8e5..5fa185151fc 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -68,7 +68,8 @@ enum opcode { insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, - insn_dins, insn_syscall, insn_bbit0, insn_bbit1 + insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1, + insn_lwx, insn_ldx }; struct insn { @@ -142,9 +143,12 @@ static struct insn insn_table[] __uasminitdata = { { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, + { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, + { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, + { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD }, { insn_invalid, 0, 0 } }; @@ -152,91 +156,83 @@ static struct insn insn_table[] __uasminitdata = { static inline __uasminit u32 build_rs(u32 arg) { - if (arg & ~RS_MASK) - printk(KERN_WARNING "Micro-assembler field overflow\n"); + WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); return (arg & RS_MASK) << RS_SH; } static inline __uasminit u32 build_rt(u32 arg) { - if (arg & ~RT_MASK) - printk(KERN_WARNING "Micro-assembler field overflow\n"); + WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); return (arg & RT_MASK) << RT_SH; } static inline __uasminit u32 build_rd(u32 arg) { - if (arg & ~RD_MASK) - printk(KERN_WARNING "Micro-assembler field overflow\n"); + WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n"); return (arg & RD_MASK) << RD_SH; } static inline __uasminit u32 build_re(u32 arg) { - if (arg & ~RE_MASK) - printk(KERN_WARNING "Micro-assembler field overflow\n"); + WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n"); return (arg & RE_MASK) << RE_SH; } static inline __uasminit u32 build_simm(s32 arg) { - if (arg > 0x7fff || arg < -0x8000) - printk(KERN_WARNING "Micro-assembler field overflow\n"); + WARN(arg > 0x7fff || arg < -0x8000, + KERN_WARNING "Micro-assembler field overflow\n"); return arg & 0xffff; } static inline __uasminit u32 build_uimm(u32 arg) { - if (arg & ~IMM_MASK) - printk(KERN_WARNING "Micro-assembler field overflow\n"); + WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n"); return arg & IMM_MASK; } static inline __uasminit u32 build_bimm(s32 arg) { - if (arg > 0x1ffff || arg < -0x20000) - printk(KERN_WARNING "Micro-assembler field overflow\n"); + WARN(arg > 0x1ffff || arg < -0x20000, + KERN_WARNING "Micro-assembler field overflow\n"); - if (arg & 0x3) - printk(KERN_WARNING "Invalid micro-assembler branch target\n"); + WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); } static inline __uasminit u32 build_jimm(u32 arg) { - if (arg & ~((JIMM_MASK) << 2)) - printk(KERN_WARNING "Micro-assembler field overflow\n"); + WARN(arg & ~(JIMM_MASK << 2), + KERN_WARNING "Micro-assembler field overflow\n"); return (arg >> 2) & JIMM_MASK; } static inline __uasminit u32 build_scimm(u32 arg) { - if (arg & ~SCIMM_MASK) - printk(KERN_WARNING "Micro-assembler field overflow\n"); + WARN(arg & ~SCIMM_MASK, + KERN_WARNING "Micro-assembler field overflow\n"); return (arg & SCIMM_MASK) << SCIMM_SH; } static inline __uasminit u32 build_func(u32 arg) { - if (arg & ~FUNC_MASK) - printk(KERN_WARNING "Micro-assembler field overflow\n"); + WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); return arg & FUNC_MASK; } static inline __uasminit u32 build_set(u32 arg) { - if (arg & ~SET_MASK) - printk(KERN_WARNING "Micro-assembler field overflow\n"); + WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n"); return arg & SET_MASK; } @@ -340,6 +336,13 @@ Ip_u2u1msbu3(op) \ } \ UASM_EXPORT_SYMBOL(uasm_i##op); +#define I_u2u1msb32u3(op) \ +Ip_u2u1msbu3(op) \ +{ \ + build_insn(buf, insn##op, b, a, c+d-33, c); \ +} \ +UASM_EXPORT_SYMBOL(uasm_i##op); + #define I_u1u2(op) \ Ip_u1u2(op) \ { \ @@ -422,9 +425,12 @@ I_0(_tlbwr) I_u3u1u2(_xor) I_u2u1u3(_xori) I_u2u1msbu3(_dins); +I_u2u1msb32u3(_dinsm); I_u1(_syscall); I_u1u2s3(_bbit0); I_u1u2s3(_bbit1); +I_u3u1u2(_lwx) +I_u3u1u2(_ldx) #ifdef CONFIG_CPU_CAVIUM_OCTEON #include <asm/octeon/octeon.h> diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c index 87ccdb4b5ac..48853ab5bcf 100644 --- a/arch/mips/sibyte/common/sb_tbprof.c +++ b/arch/mips/sibyte/common/sb_tbprof.c @@ -410,14 +410,13 @@ static int sbprof_tb_open(struct inode *inode, struct file *filp) return -EBUSY; memset(&sbp, 0, sizeof(struct sbprof_tb)); - sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES); + sbp.sbprof_tbbuf = vzalloc(MAX_TBSAMPLE_BYTES); if (!sbp.sbprof_tbbuf) { sbp.open = SB_CLOSED; wmb(); return -ENOMEM; } - memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES); init_waitqueue_head(&sbp.tb_sync); init_waitqueue_head(&sbp.tb_read); mutex_init(&sbp.lock); diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c index 96e69a00ffc..85a87de17eb 100644 --- a/arch/mips/txx9/generic/pci.c +++ b/arch/mips/txx9/generic/pci.c @@ -213,11 +213,8 @@ txx9_alloc_pci_controller(struct pci_controller *pcic, pcic->mem_offset = 0; /* busaddr == physaddr */ - printk(KERN_INFO "PCI: IO 0x%08llx-0x%08llx MEM 0x%08llx-0x%08llx\n", - (unsigned long long)pcic->mem_resource[1].start, - (unsigned long long)pcic->mem_resource[1].end, - (unsigned long long)pcic->mem_resource[0].start, - (unsigned long long)pcic->mem_resource[0].end); + printk(KERN_INFO "PCI: IO %pR MEM %pR\n", + &pcic->mem_resource[1], &pcic->mem_resource[0]); /* register_pci_controller() will request MEM resource */ release_resource(&pcic->mem_resource[0]); diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig index 8ed41cf2b08..243bfa23fd5 100644 --- a/arch/mn10300/Kconfig +++ b/arch/mn10300/Kconfig @@ -1,6 +1,7 @@ config MN10300 def_bool y select HAVE_OPROFILE + select GENERIC_HARDIRQS config AM33_2 def_bool n @@ -34,9 +35,6 @@ config RWSEM_GENERIC_SPINLOCK config RWSEM_XCHGADD_ALGORITHM bool -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config GENERIC_CALIBRATE_DELAY def_bool y @@ -79,10 +77,6 @@ config QUICKLIST config ARCH_HAS_ILOG2_U32 def_bool y -# Use the generic interrupt handling code in kernel/irq/ -config GENERIC_HARDIRQS - def_bool y - config HOTPLUG_CPU def_bool n diff --git a/arch/mn10300/configs/asb2303_defconfig b/arch/mn10300/configs/asb2303_defconfig index 3f749b69ca7..1fd41ec1dfb 100644 --- a/arch/mn10300/configs/asb2303_defconfig +++ b/arch/mn10300/configs/asb2303_defconfig @@ -4,7 +4,7 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_TINY_RCU=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_VM_EVENT_COUNTERS is not set diff --git a/arch/mn10300/configs/asb2364_defconfig b/arch/mn10300/configs/asb2364_defconfig index 83ce2f27b12..31d76261a3d 100644 --- a/arch/mn10300/configs/asb2364_defconfig +++ b/arch/mn10300/configs/asb2364_defconfig @@ -15,7 +15,7 @@ CONFIG_CGROUP_CPUACCT=y CONFIG_RESOURCE_COUNTERS=y CONFIG_RELAY=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_VM_EVENT_COUNTERS is not set CONFIG_SLAB=y diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 0888675c98d..fed2946f733 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -12,7 +12,10 @@ config PARISC select HAVE_IRQ_WORK select HAVE_PERF_EVENTS select GENERIC_ATOMIC64 if !64BIT - select GENERIC_HARDIRQS_NO__DO_IRQ + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE + select IRQ_PER_CPU + help The PA-RISC microprocessor is designed by Hewlett-Packard and used in many of their workstations & servers (HP9000 700 and 800 series, @@ -66,22 +69,9 @@ config TIME_LOW_RES depends on SMP default y -config GENERIC_HARDIRQS - def_bool y - -config GENERIC_IRQ_PROBE - def_bool y - config HAVE_LATENCYTOP_SUPPORT def_bool y -config IRQ_PER_CPU - bool - default y - -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - # unless you want to implement ACPI on PA-RISC ... ;-) config PM bool diff --git a/arch/parisc/configs/a500_defconfig b/arch/parisc/configs/a500_defconfig index f9305f30603..b647b182dac 100644 --- a/arch/parisc/configs/a500_defconfig +++ b/arch/parisc/configs/a500_defconfig @@ -8,7 +8,7 @@ CONFIG_LOG_BUF_SHIFT=16 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_SLAB=y CONFIG_PROFILING=y diff --git a/arch/parisc/configs/c3000_defconfig b/arch/parisc/configs/c3000_defconfig index 628d3e02253..311ca367b62 100644 --- a/arch/parisc/configs/c3000_defconfig +++ b/arch/parisc/configs/c3000_defconfig @@ -6,7 +6,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_SLAB=y CONFIG_PROFILING=y diff --git a/arch/parisc/include/asm/pgtable.h b/arch/parisc/include/asm/pgtable.h index 865f37a8a88..6f1f65d3c0e 100644 --- a/arch/parisc/include/asm/pgtable.h +++ b/arch/parisc/include/asm/pgtable.h @@ -10,11 +10,13 @@ * we simulate an x86-style page table for the linux mm code */ -#include <linux/mm.h> /* for vm_area_struct */ #include <linux/bitops.h> +#include <linux/spinlock.h> #include <asm/processor.h> #include <asm/cache.h> +struct vm_area_struct; + /* * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel * memory. For the return value to be meaningful, ADDR must be >= diff --git a/arch/parisc/kernel/firmware.c b/arch/parisc/kernel/firmware.c index df971fa0c32..4896ed09058 100644 --- a/arch/parisc/kernel/firmware.c +++ b/arch/parisc/kernel/firmware.c @@ -1126,15 +1126,13 @@ int pdc_iodc_print(const unsigned char *str, unsigned count) unsigned int i; unsigned long flags; - for (i = 0; i < count && i < 79;) { + for (i = 0; i < count;) { switch(str[i]) { case '\n': iodc_dbuf[i+0] = '\r'; iodc_dbuf[i+1] = '\n'; i += 2; goto print; - case '\b': /* BS */ - i--; /* overwrite last */ default: iodc_dbuf[i] = str[i]; i++; @@ -1142,15 +1140,6 @@ int pdc_iodc_print(const unsigned char *str, unsigned count) } } - /* if we're at the end of line, and not already inserting a newline, - * insert one anyway. iodc console doesn't claim to support >79 char - * lines. don't account for this in the return value. - */ - if (i == 79 && iodc_dbuf[i-1] != '\n') { - iodc_dbuf[i+0] = '\r'; - iodc_dbuf[i+1] = '\n'; - } - print: spin_lock_irqsave(&pdc_lock, flags); real32_call(PAGE0->mem_cons.iodc_io, diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 959f38ccb9a..7d69e9bf5e6 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -36,24 +36,12 @@ config GENERIC_TIME_VSYSCALL config GENERIC_CLOCKEVENTS def_bool y -config GENERIC_HARDIRQS - bool - default y - -config GENERIC_HARDIRQS_NO__DO_IRQ - bool - default y - config HAVE_SETUP_PER_CPU_AREA def_bool PPC64 config NEED_PER_CPU_EMBED_FIRST_CHUNK def_bool PPC64 -config IRQ_PER_CPU - bool - default y - config NR_IRQS int "Number of virtual interrupt numbers" range 32 32768 @@ -143,6 +131,9 @@ config PPC select HAVE_PERF_EVENTS select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64 + select HAVE_GENERIC_HARDIRQS + select HAVE_SPARSE_IRQ + select IRQ_PER_CPU config EARLY_PRINTK bool @@ -392,19 +383,6 @@ config IRQ_ALL_CPUS CPU. Generally saying Y is safe, although some problems have been reported with SMP Power Macintoshes with this option enabled. -config SPARSE_IRQ - bool "Support sparse irq numbering" - default n - help - This enables support for sparse irqs. This is useful for distro - kernels that want to define a high CONFIG_NR_CPUS value but still - want to have low kernel memory footprint on smaller machines. - - ( Sparse IRQs can also be beneficial on NUMA boxes, as they spread - out the irq_desc[] array in a more NUMA-friendly way. ) - - If you don't know what to do here, say N. - config NUMA bool "NUMA support" depends on PPC64 diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index 96deec63bcf..89178164af5 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -368,7 +368,7 @@ INSTALL := install extra-installed := $(patsubst $(obj)/%, $(DESTDIR)$(WRAPPER_OBJDIR)/%, $(extra-y)) hostprogs-installed := $(patsubst %, $(DESTDIR)$(WRAPPER_BINDIR)/%, $(hostprogs-y)) wrapper-installed := $(DESTDIR)$(WRAPPER_BINDIR)/wrapper -dts-installed := $(patsubst $(obj)/dts/%, $(DESTDIR)$(WRAPPER_DTSDIR)/%, $(wildcard $(obj)/dts/*.dts)) +dts-installed := $(patsubst $(dtstree)/%, $(DESTDIR)$(WRAPPER_DTSDIR)/%, $(wildcard $(dtstree)/*.dts)) all-installed := $(extra-installed) $(hostprogs-installed) $(wrapper-installed) $(dts-installed) diff --git a/arch/powerpc/boot/dts/mpc8308rdb.dts b/arch/powerpc/boot/dts/mpc8308rdb.dts index d3db02f98dd..a0bd1881081 100644 --- a/arch/powerpc/boot/dts/mpc8308rdb.dts +++ b/arch/powerpc/boot/dts/mpc8308rdb.dts @@ -109,7 +109,7 @@ #address-cells = <1>; #size-cells = <1>; device_type = "soc"; - compatible = "fsl,mpc8315-immr", "simple-bus"; + compatible = "fsl,mpc8308-immr", "simple-bus"; ranges = <0 0xe0000000 0x00100000>; reg = <0xe0000000 0x00000200>; bus-frequency = <0>; diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts index 2bbecbb4cbf..69422eb24d9 100644 --- a/arch/powerpc/boot/dts/p1022ds.dts +++ b/arch/powerpc/boot/dts/p1022ds.dts @@ -291,13 +291,13 @@ ranges = <0x0 0xc100 0x200>; cell-index = <1>; dma00: dma-channel@0 { - compatible = "fsl,eloplus-dma-channel"; + compatible = "fsl,ssi-dma-channel"; reg = <0x0 0x80>; cell-index = <0>; interrupts = <76 2>; }; dma01: dma-channel@80 { - compatible = "fsl,eloplus-dma-channel"; + compatible = "fsl,ssi-dma-channel"; reg = <0x80 0x80>; cell-index = <1>; interrupts = <77 2>; diff --git a/arch/powerpc/configs/40x/acadia_defconfig b/arch/powerpc/configs/40x/acadia_defconfig index 97fedceaa30..4182c772340 100644 --- a/arch/powerpc/configs/40x/acadia_defconfig +++ b/arch/powerpc/configs/40x/acadia_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/40x/ep405_defconfig b/arch/powerpc/configs/40x/ep405_defconfig index 33b3c24f4ed..2dbb293163f 100644 --- a/arch/powerpc/configs/40x/ep405_defconfig +++ b/arch/powerpc/configs/40x/ep405_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/40x/hcu4_defconfig b/arch/powerpc/configs/40x/hcu4_defconfig index 4613079a0ab..ebeb4accad6 100644 --- a/arch/powerpc/configs/40x/hcu4_defconfig +++ b/arch/powerpc/configs/40x/hcu4_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/40x/kilauea_defconfig b/arch/powerpc/configs/40x/kilauea_defconfig index 34b8c1a1e75..532ea9d93a1 100644 --- a/arch/powerpc/configs/40x/kilauea_defconfig +++ b/arch/powerpc/configs/40x/kilauea_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/40x/makalu_defconfig b/arch/powerpc/configs/40x/makalu_defconfig index 651be09136f..3c142ac1b34 100644 --- a/arch/powerpc/configs/40x/makalu_defconfig +++ b/arch/powerpc/configs/40x/makalu_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/40x/walnut_defconfig b/arch/powerpc/configs/40x/walnut_defconfig index ded455e1833..ff57d4828ff 100644 --- a/arch/powerpc/configs/40x/walnut_defconfig +++ b/arch/powerpc/configs/40x/walnut_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/44x/arches_defconfig b/arch/powerpc/configs/44x/arches_defconfig index 63746a041d6..3ed16d5c909 100644 --- a/arch/powerpc/configs/44x/arches_defconfig +++ b/arch/powerpc/configs/44x/arches_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/44x/bamboo_defconfig b/arch/powerpc/configs/44x/bamboo_defconfig index f5f2a4e3e21..b1b7d2c5c05 100644 --- a/arch/powerpc/configs/44x/bamboo_defconfig +++ b/arch/powerpc/configs/44x/bamboo_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/44x/bluestone_defconfig b/arch/powerpc/configs/44x/bluestone_defconfig index ac65b48b8cc..30a0a8e08fd 100644 --- a/arch/powerpc/configs/44x/bluestone_defconfig +++ b/arch/powerpc/configs/44x/bluestone_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_PCI_QUIRKS is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/powerpc/configs/44x/canyonlands_defconfig b/arch/powerpc/configs/44x/canyonlands_defconfig index 17e4dd98eed..a46942aac69 100644 --- a/arch/powerpc/configs/44x/canyonlands_defconfig +++ b/arch/powerpc/configs/44x/canyonlands_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/44x/ebony_defconfig b/arch/powerpc/configs/44x/ebony_defconfig index fedd03fdf5d..07d77e51f1b 100644 --- a/arch/powerpc/configs/44x/ebony_defconfig +++ b/arch/powerpc/configs/44x/ebony_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/44x/eiger_defconfig b/arch/powerpc/configs/44x/eiger_defconfig index ebff7011282..2ce7e9aff09 100644 --- a/arch/powerpc/configs/44x/eiger_defconfig +++ b/arch/powerpc/configs/44x/eiger_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/44x/icon_defconfig b/arch/powerpc/configs/44x/icon_defconfig index 865e93fb41f..18730ff9de7 100644 --- a/arch/powerpc/configs/44x/icon_defconfig +++ b/arch/powerpc/configs/44x/icon_defconfig @@ -6,7 +6,7 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/44x/iss476-smp_defconfig b/arch/powerpc/configs/44x/iss476-smp_defconfig index 8ece4c77441..92f863ac844 100644 --- a/arch/powerpc/configs/44x/iss476-smp_defconfig +++ b/arch/powerpc/configs/44x/iss476-smp_defconfig @@ -7,7 +7,7 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_PROFILING=y diff --git a/arch/powerpc/configs/44x/katmai_defconfig b/arch/powerpc/configs/44x/katmai_defconfig index 4ca9b4873c5..34c09144a69 100644 --- a/arch/powerpc/configs/44x/katmai_defconfig +++ b/arch/powerpc/configs/44x/katmai_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/44x/rainier_defconfig b/arch/powerpc/configs/44x/rainier_defconfig index e3b65d24207..21c33faf61a 100644 --- a/arch/powerpc/configs/44x/rainier_defconfig +++ b/arch/powerpc/configs/44x/rainier_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/44x/redwood_defconfig b/arch/powerpc/configs/44x/redwood_defconfig index 64cd0f3421a..01cc2b1a7f9 100644 --- a/arch/powerpc/configs/44x/redwood_defconfig +++ b/arch/powerpc/configs/44x/redwood_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/44x/sam440ep_defconfig b/arch/powerpc/configs/44x/sam440ep_defconfig index 01d03367917..dfcffede16a 100644 --- a/arch/powerpc/configs/44x/sam440ep_defconfig +++ b/arch/powerpc/configs/44x/sam440ep_defconfig @@ -6,7 +6,7 @@ CONFIG_IKCONFIG=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/44x/sequoia_defconfig b/arch/powerpc/configs/44x/sequoia_defconfig index 89b2f962613..47e399f2892 100644 --- a/arch/powerpc/configs/44x/sequoia_defconfig +++ b/arch/powerpc/configs/44x/sequoia_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/44x/taishan_defconfig b/arch/powerpc/configs/44x/taishan_defconfig index e3386cf6f5b..a6a002ed568 100644 --- a/arch/powerpc/configs/44x/taishan_defconfig +++ b/arch/powerpc/configs/44x/taishan_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/44x/warp_defconfig b/arch/powerpc/configs/44x/warp_defconfig index 9c13b9dffaf..6cf9d661480 100644 --- a/arch/powerpc/configs/44x/warp_defconfig +++ b/arch/powerpc/configs/44x/warp_defconfig @@ -8,7 +8,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/52xx/cm5200_defconfig b/arch/powerpc/configs/52xx/cm5200_defconfig index f234c4d0b15..69b57daf402 100644 --- a/arch/powerpc/configs/52xx/cm5200_defconfig +++ b/arch/powerpc/configs/52xx/cm5200_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_KALLSYMS is not set # CONFIG_EPOLL is not set diff --git a/arch/powerpc/configs/52xx/lite5200b_defconfig b/arch/powerpc/configs/52xx/lite5200b_defconfig index a4a795c8074..f3638ae0a62 100644 --- a/arch/powerpc/configs/52xx/lite5200b_defconfig +++ b/arch/powerpc/configs/52xx/lite5200b_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_KALLSYMS is not set # CONFIG_EPOLL is not set diff --git a/arch/powerpc/configs/52xx/motionpro_defconfig b/arch/powerpc/configs/52xx/motionpro_defconfig index 20d53a1aa7e..6828eda02bd 100644 --- a/arch/powerpc/configs/52xx/motionpro_defconfig +++ b/arch/powerpc/configs/52xx/motionpro_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_KALLSYMS is not set # CONFIG_EPOLL is not set diff --git a/arch/powerpc/configs/52xx/pcm030_defconfig b/arch/powerpc/configs/52xx/pcm030_defconfig index 6bd58338bf1..7f7e4a87860 100644 --- a/arch/powerpc/configs/52xx/pcm030_defconfig +++ b/arch/powerpc/configs/52xx/pcm030_defconfig @@ -8,7 +8,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_VM_EVENT_COUNTERS is not set CONFIG_SLAB=y diff --git a/arch/powerpc/configs/52xx/tqm5200_defconfig b/arch/powerpc/configs/52xx/tqm5200_defconfig index 3a1f70292d9..959cd2cfc27 100644 --- a/arch/powerpc/configs/52xx/tqm5200_defconfig +++ b/arch/powerpc/configs/52xx/tqm5200_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_KALLSYMS is not set # CONFIG_EPOLL is not set diff --git a/arch/powerpc/configs/83xx/asp8347_defconfig b/arch/powerpc/configs/83xx/asp8347_defconfig index eed42d8919e..d2762d9dcb8 100644 --- a/arch/powerpc/configs/83xx/asp8347_defconfig +++ b/arch/powerpc/configs/83xx/asp8347_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/83xx/kmeter1_defconfig b/arch/powerpc/configs/83xx/kmeter1_defconfig index e43ecb27dfd..7a7b731c573 100644 --- a/arch/powerpc/configs/83xx/kmeter1_defconfig +++ b/arch/powerpc/configs/83xx/kmeter1_defconfig @@ -3,7 +3,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_HOTPLUG is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig index c2e6ab51d33..c683bce4c26 100644 --- a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig +++ b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig index 1d3b2006591..a721cd3d793 100644 --- a/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig +++ b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/83xx/mpc832x_mds_defconfig b/arch/powerpc/configs/83xx/mpc832x_mds_defconfig index 91fe73bd5ad..a5699a1f7d0 100644 --- a/arch/powerpc/configs/83xx/mpc832x_mds_defconfig +++ b/arch/powerpc/configs/83xx/mpc832x_mds_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig b/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig index 6d300f20560..b4da1a7e644 100644 --- a/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig +++ b/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/83xx/mpc834x_itx_defconfig b/arch/powerpc/configs/83xx/mpc834x_itx_defconfig index b236a67e01f..291f8221d5a 100644 --- a/arch/powerpc/configs/83xx/mpc834x_itx_defconfig +++ b/arch/powerpc/configs/83xx/mpc834x_itx_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig b/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig index 001dead3cde..f8b228aaa03 100644 --- a/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig +++ b/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/83xx/mpc834x_mds_defconfig b/arch/powerpc/configs/83xx/mpc834x_mds_defconfig index 9dccefca00c..99660c06219 100644 --- a/arch/powerpc/configs/83xx/mpc834x_mds_defconfig +++ b/arch/powerpc/configs/83xx/mpc834x_mds_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/83xx/mpc836x_mds_defconfig b/arch/powerpc/configs/83xx/mpc836x_mds_defconfig index d4b165d7d29..10b5c4cd0e7 100644 --- a/arch/powerpc/configs/83xx/mpc836x_mds_defconfig +++ b/arch/powerpc/configs/83xx/mpc836x_mds_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig b/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig index 89ba67274bd..45925d701d2 100644 --- a/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig +++ b/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/83xx/mpc837x_mds_defconfig b/arch/powerpc/configs/83xx/mpc837x_mds_defconfig index 2ea6b405046..f367985be6f 100644 --- a/arch/powerpc/configs/83xx/mpc837x_mds_defconfig +++ b/arch/powerpc/configs/83xx/mpc837x_mds_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig b/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig index bffe3c77503..414eda38159 100644 --- a/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig +++ b/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/83xx/sbc834x_defconfig b/arch/powerpc/configs/83xx/sbc834x_defconfig index fa5c9eefc9a..6d6463fe06f 100644 --- a/arch/powerpc/configs/83xx/sbc834x_defconfig +++ b/arch/powerpc/configs/83xx/sbc834x_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/85xx/ksi8560_defconfig b/arch/powerpc/configs/85xx/ksi8560_defconfig index 385b1af37d7..8f7c1061891 100644 --- a/arch/powerpc/configs/85xx/ksi8560_defconfig +++ b/arch/powerpc/configs/85xx/ksi8560_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_BLK_DEV_BSG is not set CONFIG_KSI8560=y CONFIG_CPM2=y diff --git a/arch/powerpc/configs/85xx/mpc8540_ads_defconfig b/arch/powerpc/configs/85xx/mpc8540_ads_defconfig index 222b704c1f4..55e0725500d 100644 --- a/arch/powerpc/configs/85xx/mpc8540_ads_defconfig +++ b/arch/powerpc/configs/85xx/mpc8540_ads_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_BLK_DEV_BSG is not set CONFIG_MPC8540_ADS=y CONFIG_NO_HZ=y diff --git a/arch/powerpc/configs/85xx/mpc8560_ads_defconfig b/arch/powerpc/configs/85xx/mpc8560_ads_defconfig index 619702de947..d724095530a 100644 --- a/arch/powerpc/configs/85xx/mpc8560_ads_defconfig +++ b/arch/powerpc/configs/85xx/mpc8560_ads_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_BLK_DEV_BSG is not set CONFIG_MPC8560_ADS=y CONFIG_BINFMT_MISC=y diff --git a/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig b/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig index 6bf56e83f95..4b44beaa21a 100644 --- a/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig +++ b/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_BLK_DEV_BSG is not set CONFIG_MPC85xx_CDS=y CONFIG_NO_HZ=y diff --git a/arch/powerpc/configs/85xx/sbc8548_defconfig b/arch/powerpc/configs/85xx/sbc8548_defconfig index a9a17d05576..5b2b651dfb9 100644 --- a/arch/powerpc/configs/85xx/sbc8548_defconfig +++ b/arch/powerpc/configs/85xx/sbc8548_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y # CONFIG_BLK_DEV_BSG is not set CONFIG_SBC8548=y diff --git a/arch/powerpc/configs/85xx/sbc8560_defconfig b/arch/powerpc/configs/85xx/sbc8560_defconfig index 820e32d8c42..f7fdb0318e4 100644 --- a/arch/powerpc/configs/85xx/sbc8560_defconfig +++ b/arch/powerpc/configs/85xx/sbc8560_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y # CONFIG_BLK_DEV_BSG is not set CONFIG_SBC8560=y diff --git a/arch/powerpc/configs/85xx/socrates_defconfig b/arch/powerpc/configs/85xx/socrates_defconfig index b6db3f47af9..77506b5d5a4 100644 --- a/arch/powerpc/configs/85xx/socrates_defconfig +++ b/arch/powerpc/configs/85xx/socrates_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=16 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_EPOLL is not set diff --git a/arch/powerpc/configs/85xx/stx_gp3_defconfig b/arch/powerpc/configs/85xx/stx_gp3_defconfig index 333a41bd2a6..5d4db154bf5 100644 --- a/arch/powerpc/configs/85xx/stx_gp3_defconfig +++ b/arch/powerpc/configs/85xx/stx_gp3_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODVERSIONS=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/85xx/tqm8540_defconfig b/arch/powerpc/configs/85xx/tqm8540_defconfig index 33db352f847..ddcb9f37fa1 100644 --- a/arch/powerpc/configs/85xx/tqm8540_defconfig +++ b/arch/powerpc/configs/85xx/tqm8540_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_EPOLL is not set diff --git a/arch/powerpc/configs/85xx/tqm8541_defconfig b/arch/powerpc/configs/85xx/tqm8541_defconfig index f0c20dfbd4d..981abd6d4b5 100644 --- a/arch/powerpc/configs/85xx/tqm8541_defconfig +++ b/arch/powerpc/configs/85xx/tqm8541_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_EPOLL is not set diff --git a/arch/powerpc/configs/85xx/tqm8548_defconfig b/arch/powerpc/configs/85xx/tqm8548_defconfig index a883450dcdf..37b3d7227cd 100644 --- a/arch/powerpc/configs/85xx/tqm8548_defconfig +++ b/arch/powerpc/configs/85xx/tqm8548_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/85xx/tqm8555_defconfig b/arch/powerpc/configs/85xx/tqm8555_defconfig index ff95f90dc17..3593b320c97 100644 --- a/arch/powerpc/configs/85xx/tqm8555_defconfig +++ b/arch/powerpc/configs/85xx/tqm8555_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_EPOLL is not set diff --git a/arch/powerpc/configs/85xx/tqm8560_defconfig b/arch/powerpc/configs/85xx/tqm8560_defconfig index 8d6c90ea478..de413acc34d 100644 --- a/arch/powerpc/configs/85xx/tqm8560_defconfig +++ b/arch/powerpc/configs/85xx/tqm8560_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_EPOLL is not set diff --git a/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig b/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig index f53efe4a0e0..5ea3124518f 100644 --- a/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig +++ b/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig @@ -11,7 +11,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig index 432ebc28d25..4b2441244ea 100644 --- a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig +++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig @@ -11,7 +11,7 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/86xx/gef_sbc310_defconfig b/arch/powerpc/configs/86xx/gef_sbc310_defconfig index ce5e919d9b5..a360ba44b92 100644 --- a/arch/powerpc/configs/86xx/gef_sbc310_defconfig +++ b/arch/powerpc/configs/86xx/gef_sbc310_defconfig @@ -11,7 +11,7 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig index 589e71e6dc1..be2829dd129 100644 --- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig +++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig @@ -11,7 +11,7 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig index 321fb47096d..036bfb2d18c 100644 --- a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig +++ b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig @@ -6,7 +6,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_EXTRA_PASS=y # CONFIG_ELF_CORE is not set CONFIG_MODULES=y diff --git a/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig b/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig index b5e46399374..0c9c7ed7ec7 100644 --- a/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig +++ b/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig @@ -10,7 +10,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/86xx/sbc8641d_defconfig b/arch/powerpc/configs/86xx/sbc8641d_defconfig index 71145c3a64d..0a92ca04564 100644 --- a/arch/powerpc/configs/86xx/sbc8641d_defconfig +++ b/arch/powerpc/configs/86xx/sbc8641d_defconfig @@ -11,7 +11,7 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/adder875_defconfig b/arch/powerpc/configs/adder875_defconfig index ca84c7fc24d..69128740c14 100644 --- a/arch/powerpc/configs/adder875_defconfig +++ b/arch/powerpc/configs/adder875_defconfig @@ -4,7 +4,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_BASE_FULL is not set diff --git a/arch/powerpc/configs/e55xx_smp_defconfig b/arch/powerpc/configs/e55xx_smp_defconfig index 94d120ef99c..06f95492afc 100644 --- a/arch/powerpc/configs/e55xx_smp_defconfig +++ b/arch/powerpc/configs/e55xx_smp_defconfig @@ -12,7 +12,7 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/ep8248e_defconfig b/arch/powerpc/configs/ep8248e_defconfig index 2677b08199e..fceffb3cffb 100644 --- a/arch/powerpc/configs/ep8248e_defconfig +++ b/arch/powerpc/configs/ep8248e_defconfig @@ -2,7 +2,7 @@ CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_SLAB=y # CONFIG_IOSCHED_CFQ is not set diff --git a/arch/powerpc/configs/ep88xc_defconfig b/arch/powerpc/configs/ep88xc_defconfig index f9a3112e544..219fd470ed2 100644 --- a/arch/powerpc/configs/ep88xc_defconfig +++ b/arch/powerpc/configs/ep88xc_defconfig @@ -4,7 +4,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_BASE_FULL is not set diff --git a/arch/powerpc/configs/gamecube_defconfig b/arch/powerpc/configs/gamecube_defconfig index fcf0a398cd6..e74d3a48370 100644 --- a/arch/powerpc/configs/gamecube_defconfig +++ b/arch/powerpc/configs/gamecube_defconfig @@ -6,7 +6,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_ELF_CORE is not set CONFIG_PERF_COUNTERS=y # CONFIG_VM_EVENT_COUNTERS is not set diff --git a/arch/powerpc/configs/holly_defconfig b/arch/powerpc/configs/holly_defconfig index b9b63a60952..94ebfee188d 100644 --- a/arch/powerpc/configs/holly_defconfig +++ b/arch/powerpc/configs/holly_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_MODULES=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_PPC_CHRP is not set diff --git a/arch/powerpc/configs/mgcoge_defconfig b/arch/powerpc/configs/mgcoge_defconfig index c4ed255af18..39518e91822 100644 --- a/arch/powerpc/configs/mgcoge_defconfig +++ b/arch/powerpc/configs/mgcoge_defconfig @@ -3,7 +3,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_SLAB=y # CONFIG_IOSCHED_CFQ is not set diff --git a/arch/powerpc/configs/mgsuvd_defconfig b/arch/powerpc/configs/mgsuvd_defconfig index f276c7cf555..2a490626015 100644 --- a/arch/powerpc/configs/mgsuvd_defconfig +++ b/arch/powerpc/configs/mgsuvd_defconfig @@ -4,7 +4,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_HOTPLUG is not set # CONFIG_BUG is not set diff --git a/arch/powerpc/configs/mpc7448_hpc2_defconfig b/arch/powerpc/configs/mpc7448_hpc2_defconfig index 3b9470883de..75f0bbf0f6e 100644 --- a/arch/powerpc/configs/mpc7448_hpc2_defconfig +++ b/arch/powerpc/configs/mpc7448_hpc2_defconfig @@ -4,7 +4,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_PPC_CHRP is not set # CONFIG_PPC_PMAC is not set diff --git a/arch/powerpc/configs/mpc8272_ads_defconfig b/arch/powerpc/configs/mpc8272_ads_defconfig index c7d68ff1a73..6a22400f73c 100644 --- a/arch/powerpc/configs/mpc8272_ads_defconfig +++ b/arch/powerpc/configs/mpc8272_ads_defconfig @@ -2,7 +2,7 @@ CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y # CONFIG_PPC_CHRP is not set # CONFIG_PPC_PMAC is not set diff --git a/arch/powerpc/configs/mpc83xx_defconfig b/arch/powerpc/configs/mpc83xx_defconfig index 5b1b10fd974..5aac9a8bc53 100644 --- a/arch/powerpc/configs/mpc83xx_defconfig +++ b/arch/powerpc/configs/mpc83xx_defconfig @@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index 3aeb5949cfe..99a19d1e9bf 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig @@ -10,7 +10,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig index d62c8016f4b..c636f23f8c9 100644 --- a/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig @@ -12,7 +12,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/mpc866_ads_defconfig b/arch/powerpc/configs/mpc866_ads_defconfig index 668215cae89..5c258823e69 100644 --- a/arch/powerpc/configs/mpc866_ads_defconfig +++ b/arch/powerpc/configs/mpc866_ads_defconfig @@ -4,7 +4,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_HOTPLUG is not set # CONFIG_BUG is not set diff --git a/arch/powerpc/configs/mpc86xx_defconfig b/arch/powerpc/configs/mpc86xx_defconfig index 63b90d47788..55b54318fef 100644 --- a/arch/powerpc/configs/mpc86xx_defconfig +++ b/arch/powerpc/configs/mpc86xx_defconfig @@ -10,7 +10,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/mpc885_ads_defconfig b/arch/powerpc/configs/mpc885_ads_defconfig index f9b83481b00..9e146cdf63d 100644 --- a/arch/powerpc/configs/mpc885_ads_defconfig +++ b/arch/powerpc/configs/mpc885_ads_defconfig @@ -4,7 +4,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_BASE_FULL is not set diff --git a/arch/powerpc/configs/ppc40x_defconfig b/arch/powerpc/configs/ppc40x_defconfig index 93d7425ce6c..bfd634b5ada 100644 --- a/arch/powerpc/configs/ppc40x_defconfig +++ b/arch/powerpc/configs/ppc40x_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/ppc44x_defconfig b/arch/powerpc/configs/ppc44x_defconfig index 2fa05f7be4c..47133202a62 100644 --- a/arch/powerpc/configs/ppc44x_defconfig +++ b/arch/powerpc/configs/ppc44x_defconfig @@ -5,7 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y diff --git a/arch/powerpc/configs/pq2fads_defconfig b/arch/powerpc/configs/pq2fads_defconfig index a4353bef31c..baad8db21b6 100644 --- a/arch/powerpc/configs/pq2fads_defconfig +++ b/arch/powerpc/configs/pq2fads_defconfig @@ -3,7 +3,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y # CONFIG_PPC_CHRP is not set # CONFIG_PPC_PMAC is not set diff --git a/arch/powerpc/configs/ps3_defconfig b/arch/powerpc/configs/ps3_defconfig index 49cffe00365..caba919f65d 100644 --- a/arch/powerpc/configs/ps3_defconfig +++ b/arch/powerpc/configs/ps3_defconfig @@ -8,7 +8,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_NAMESPACES=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_EXTRA_PASS=y # CONFIG_PERF_EVENTS is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig index f87f0e15cfa..9c3f22c6cde 100644 --- a/arch/powerpc/configs/pseries_defconfig +++ b/arch/powerpc/configs/pseries_defconfig @@ -2,7 +2,7 @@ CONFIG_PPC64=y CONFIG_ALTIVEC=y CONFIG_VSX=y CONFIG_SMP=y -CONFIG_NR_CPUS=128 +CONFIG_NR_CPUS=1024 CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -45,6 +45,8 @@ CONFIG_KEXEC=y CONFIG_IRQ_ALL_CPUS=y CONFIG_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTREMOVE=y +CONFIG_PPC_64K_PAGES=y +CONFIG_PPC_SUBPAGE_PROT=y CONFIG_SCHED_SMT=y CONFIG_HOTPLUG_PCI=m CONFIG_HOTPLUG_PCI_RPA=m @@ -184,6 +186,7 @@ CONFIG_ACENIC_OMIT_TIGON_I=y CONFIG_E1000=y CONFIG_E1000E=y CONFIG_TIGON3=y +CONFIG_BNX2=m CONFIG_CHELSIO_T1=m CONFIG_CHELSIO_T3=m CONFIG_EHEA=y @@ -311,9 +314,7 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_LATENCYTOP=y CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_IRQSOFF_TRACER=y CONFIG_SCHED_TRACER=y -CONFIG_STACK_TRACER=y CONFIG_BLK_DEV_IO_TRACE=y CONFIG_DEBUG_STACKOVERFLOW=y CONFIG_DEBUG_STACK_USAGE=y diff --git a/arch/powerpc/configs/storcenter_defconfig b/arch/powerpc/configs/storcenter_defconfig index 4f0c10a62b9..ebb2a66c99d 100644 --- a/arch/powerpc/configs/storcenter_defconfig +++ b/arch/powerpc/configs/storcenter_defconfig @@ -1,7 +1,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/powerpc/configs/tqm8xx_defconfig b/arch/powerpc/configs/tqm8xx_defconfig index d0a5b676388..8616fde0896 100644 --- a/arch/powerpc/configs/tqm8xx_defconfig +++ b/arch/powerpc/configs/tqm8xx_defconfig @@ -5,7 +5,7 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_BASE_FULL is not set diff --git a/arch/powerpc/configs/wii_defconfig b/arch/powerpc/configs/wii_defconfig index bb8ba75b7c6..175295fbf4f 100644 --- a/arch/powerpc/configs/wii_defconfig +++ b/arch/powerpc/configs/wii_defconfig @@ -7,7 +7,7 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_ELF_CORE is not set CONFIG_PERF_COUNTERS=y # CONFIG_VM_EVENT_COUNTERS is not set diff --git a/arch/powerpc/include/asm/feature-fixups.h b/arch/powerpc/include/asm/feature-fixups.h index 96a7d067fbb..921a8470e18 100644 --- a/arch/powerpc/include/asm/feature-fixups.h +++ b/arch/powerpc/include/asm/feature-fixups.h @@ -37,18 +37,21 @@ label##2: \ .align 2; \ label##3: -#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ -label##4: \ - .popsection; \ - .pushsection sect,"a"; \ - .align 3; \ -label##5: \ - FTR_ENTRY_LONG msk; \ - FTR_ENTRY_LONG val; \ - FTR_ENTRY_OFFSET label##1b-label##5b; \ - FTR_ENTRY_OFFSET label##2b-label##5b; \ - FTR_ENTRY_OFFSET label##3b-label##5b; \ - FTR_ENTRY_OFFSET label##4b-label##5b; \ +#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ +label##4: \ + .popsection; \ + .pushsection sect,"a"; \ + .align 3; \ +label##5: \ + FTR_ENTRY_LONG msk; \ + FTR_ENTRY_LONG val; \ + FTR_ENTRY_OFFSET label##1b-label##5b; \ + FTR_ENTRY_OFFSET label##2b-label##5b; \ + FTR_ENTRY_OFFSET label##3b-label##5b; \ + FTR_ENTRY_OFFSET label##4b-label##5b; \ + .ifgt (label##4b-label##3b)-(label##2b-label##1b); \ + .error "Feature section else case larger than body"; \ + .endif; \ .popsection; diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h index 4e10f508570..0edb6842b13 100644 --- a/arch/powerpc/include/asm/immap_qe.h +++ b/arch/powerpc/include/asm/immap_qe.h @@ -467,13 +467,22 @@ struct qe_immap { extern struct qe_immap __iomem *qe_immr; extern phys_addr_t get_qe_base(void); -static inline unsigned long immrbar_virt_to_phys(void *address) +/* + * Returns the offset within the QE address space of the given pointer. + * + * Note that the QE does not support 36-bit physical addresses, so if + * get_qe_base() returns a number above 4GB, the caller will probably fail. + */ +static inline phys_addr_t immrbar_virt_to_phys(void *address) { - if ( ((u32)address >= (u32)qe_immr) && - ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) ) - return (unsigned long)(address - (u32)qe_immr + - (u32)get_qe_base()); - return (unsigned long)virt_to_phys(address); + void *q = (void *)qe_immr; + + /* Is it a MURAM address? */ + if ((address >= q) && (address < (q + QE_IMMAP_SIZE))) + return get_qe_base() + (address - q); + + /* It's an address returned by kmalloc */ + return virt_to_phys(address); } #endif /* __KERNEL__ */ diff --git a/arch/powerpc/include/asm/irqflags.h b/arch/powerpc/include/asm/irqflags.h index b85d8ddbb66..b0b06d85788 100644 --- a/arch/powerpc/include/asm/irqflags.h +++ b/arch/powerpc/include/asm/irqflags.h @@ -12,24 +12,44 @@ #else #ifdef CONFIG_TRACE_IRQFLAGS +#ifdef CONFIG_IRQSOFF_TRACER +/* + * Since the ftrace irqsoff latency trace checks CALLER_ADDR1, + * which is the stack frame here, we need to force a stack frame + * in case we came from user space. + */ +#define TRACE_WITH_FRAME_BUFFER(func) \ + mflr r0; \ + stdu r1, -32(r1); \ + std r0, 16(r1); \ + stdu r1, -32(r1); \ + bl func; \ + ld r1, 0(r1); \ + ld r1, 0(r1); +#else +#define TRACE_WITH_FRAME_BUFFER(func) \ + bl func; +#endif + /* * Most of the CPU's IRQ-state tracing is done from assembly code; we * have to call a C function so call a wrapper that saves all the * C-clobbered registers. */ -#define TRACE_ENABLE_INTS bl .trace_hardirqs_on -#define TRACE_DISABLE_INTS bl .trace_hardirqs_off -#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip) \ - cmpdi en,0; \ - bne 95f; \ - stb en,PACASOFTIRQEN(r13); \ - bl .trace_hardirqs_off; \ - b skip; \ -95: bl .trace_hardirqs_on; \ +#define TRACE_ENABLE_INTS TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_on) +#define TRACE_DISABLE_INTS TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_off) + +#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip) \ + cmpdi en,0; \ + bne 95f; \ + stb en,PACASOFTIRQEN(r13); \ + TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_off) \ + b skip; \ +95: TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_on) \ li en,1; #define TRACE_AND_RESTORE_IRQ(en) \ TRACE_AND_RESTORE_IRQ_PARTIAL(en,96f); \ - stb en,PACASOFTIRQEN(r13); \ + stb en,PACASOFTIRQEN(r13); \ 96: #else #define TRACE_ENABLE_INTS diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h index 8433d36619a..991d5998d6b 100644 --- a/arch/powerpc/include/asm/machdep.h +++ b/arch/powerpc/include/asm/machdep.h @@ -116,9 +116,6 @@ struct machdep_calls { * If for some reason there is no irq, but the interrupt * shouldn't be counted as spurious, return NO_IRQ_IGNORE. */ unsigned int (*get_irq)(void); -#ifdef CONFIG_KEXEC - void (*kexec_cpu_down)(int crash_shutdown, int secondary); -#endif /* PCI stuff */ /* Called after scanning the bus, before allocating resources */ @@ -235,11 +232,7 @@ struct machdep_calls { void (*machine_shutdown)(void); #ifdef CONFIG_KEXEC - /* Called to do the minimal shutdown needed to run a kexec'd kernel - * to run successfully. - * XXX Should we move this one out of kexec scope? - */ - void (*machine_crash_shutdown)(struct pt_regs *regs); + void (*kexec_cpu_down)(int crash_shutdown, int secondary); /* Called to do what every setup is needed on image and the * reboot code buffer. Returns 0 on success. @@ -247,15 +240,6 @@ struct machdep_calls { * claims to support kexec. */ int (*machine_kexec_prepare)(struct kimage *image); - - /* Called to handle any machine specific cleanup on image */ - void (*machine_kexec_cleanup)(struct kimage *image); - - /* Called to perform the _real_ kexec. - * Do NOT allocate memory or fail here. We are past the point of - * no return. - */ - void (*machine_kexec)(struct kimage *image); #endif /* CONFIG_KEXEC */ #ifdef CONFIG_SUSPEND diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index ff0005eec7d..125fc1ad665 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -283,6 +283,7 @@ #define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */ #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ +#ifdef CONFIG_6xx #define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ #define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */ #define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ @@ -292,6 +293,7 @@ #define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ #define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ #define HID1_PS (1<<16) /* 750FX PLL selection */ +#endif #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ #define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 667a498eaee..e68c69bf741 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -246,6 +246,20 @@ store or cache line push */ #endif +/* Bit definitions for the HID1 */ +#ifdef CONFIG_E500 +/* e500v1/v2 */ +#define HID1_PLL_CFG_MASK 0xfc000000 /* PLL_CFG input pins */ +#define HID1_RFXE 0x00020000 /* Read fault exception enable */ +#define HID1_R1DPE 0x00008000 /* R1 data bus parity enable */ +#define HID1_R2DPE 0x00004000 /* R2 data bus parity enable */ +#define HID1_ASTME 0x00002000 /* Address bus streaming mode enable */ +#define HID1_ABE 0x00001000 /* Address broadcast enable */ +#define HID1_MPXTT 0x00000400 /* MPX re-map transfer type */ +#define HID1_ATS 0x00000080 /* Atomic status */ +#define HID1_MID_MASK 0x0000000f /* MID input pins */ +#endif + /* Bit definitions for the DBSR. */ /* * DBSR bits which have conflicting definitions on true Book E versus IBM 40x. diff --git a/arch/powerpc/include/asm/spu.h b/arch/powerpc/include/asm/spu.h index 0ab8d869e3d..0c8b35d7523 100644 --- a/arch/powerpc/include/asm/spu.h +++ b/arch/powerpc/include/asm/spu.h @@ -203,14 +203,6 @@ void spu_irq_setaffinity(struct spu *spu, int cpu); void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa, void *code, int code_size); -#ifdef CONFIG_KEXEC -void crash_register_spus(struct list_head *list); -#else -static inline void crash_register_spus(struct list_head *list) -{ -} -#endif - extern void spu_invalidate_slbs(struct spu *spu); extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm); int spu_64k_pages_available(void); diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 894e64fa481..5c518ad3445 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -64,6 +64,12 @@ _GLOBAL(__setup_cpu_e500v2) bl __e500_icache_setup bl __e500_dcache_setup bl __setup_e500_ivors +#ifdef CONFIG_RAPIDIO + /* Ensure that RFXE is set */ + mfspr r3,SPRN_HID1 + oris r3,r3,HID1_RFXE@h + mtspr SPRN_HID1,r3 +#endif mtlr r4 blr _GLOBAL(__setup_cpu_e500mc) diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index be5ab18b03b..8d74a24c550 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -116,7 +116,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .pmc_type = PPC_PMC_IBM, .oprofile_cpu_type = "ppc64/power3", .oprofile_type = PPC_OPROFILE_RS64, - .machine_check = machine_check_generic, .platform = "power3", }, { /* Power3+ */ @@ -132,7 +131,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .pmc_type = PPC_PMC_IBM, .oprofile_cpu_type = "ppc64/power3", .oprofile_type = PPC_OPROFILE_RS64, - .machine_check = machine_check_generic, .platform = "power3", }, { /* Northstar */ @@ -148,7 +146,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .pmc_type = PPC_PMC_IBM, .oprofile_cpu_type = "ppc64/rs64", .oprofile_type = PPC_OPROFILE_RS64, - .machine_check = machine_check_generic, .platform = "rs64", }, { /* Pulsar */ @@ -164,7 +161,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .pmc_type = PPC_PMC_IBM, .oprofile_cpu_type = "ppc64/rs64", .oprofile_type = PPC_OPROFILE_RS64, - .machine_check = machine_check_generic, .platform = "rs64", }, { /* I-star */ @@ -180,7 +176,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .pmc_type = PPC_PMC_IBM, .oprofile_cpu_type = "ppc64/rs64", .oprofile_type = PPC_OPROFILE_RS64, - .machine_check = machine_check_generic, .platform = "rs64", }, { /* S-star */ @@ -196,7 +191,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .pmc_type = PPC_PMC_IBM, .oprofile_cpu_type = "ppc64/rs64", .oprofile_type = PPC_OPROFILE_RS64, - .machine_check = machine_check_generic, .platform = "rs64", }, { /* Power4 */ @@ -212,7 +206,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .pmc_type = PPC_PMC_IBM, .oprofile_cpu_type = "ppc64/power4", .oprofile_type = PPC_OPROFILE_POWER4, - .machine_check = machine_check_generic, .platform = "power4", }, { /* Power4+ */ @@ -228,7 +221,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .pmc_type = PPC_PMC_IBM, .oprofile_cpu_type = "ppc64/power4", .oprofile_type = PPC_OPROFILE_POWER4, - .machine_check = machine_check_generic, .platform = "power4", }, { /* PPC970 */ @@ -247,7 +239,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_restore = __restore_cpu_ppc970, .oprofile_cpu_type = "ppc64/970", .oprofile_type = PPC_OPROFILE_POWER4, - .machine_check = machine_check_generic, .platform = "ppc970", }, { /* PPC970FX */ @@ -266,7 +257,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_restore = __restore_cpu_ppc970, .oprofile_cpu_type = "ppc64/970", .oprofile_type = PPC_OPROFILE_POWER4, - .machine_check = machine_check_generic, .platform = "ppc970", }, { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */ @@ -285,7 +275,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_restore = __restore_cpu_ppc970, .oprofile_cpu_type = "ppc64/970MP", .oprofile_type = PPC_OPROFILE_POWER4, - .machine_check = machine_check_generic, .platform = "ppc970", }, { /* PPC970MP */ @@ -304,7 +293,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_restore = __restore_cpu_ppc970, .oprofile_cpu_type = "ppc64/970MP", .oprofile_type = PPC_OPROFILE_POWER4, - .machine_check = machine_check_generic, .platform = "ppc970", }, { /* PPC970GX */ @@ -322,7 +310,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_setup = __setup_cpu_ppc970, .oprofile_cpu_type = "ppc64/970", .oprofile_type = PPC_OPROFILE_POWER4, - .machine_check = machine_check_generic, .platform = "ppc970", }, { /* Power5 GR */ @@ -343,7 +330,6 @@ static struct cpu_spec __initdata cpu_specs[] = { */ .oprofile_mmcra_sihv = MMCRA_SIHV, .oprofile_mmcra_sipr = MMCRA_SIPR, - .machine_check = machine_check_generic, .platform = "power5", }, { /* Power5++ */ @@ -360,7 +346,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .oprofile_type = PPC_OPROFILE_POWER4, .oprofile_mmcra_sihv = MMCRA_SIHV, .oprofile_mmcra_sipr = MMCRA_SIPR, - .machine_check = machine_check_generic, .platform = "power5+", }, { /* Power5 GS */ @@ -378,7 +363,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .oprofile_type = PPC_OPROFILE_POWER4, .oprofile_mmcra_sihv = MMCRA_SIHV, .oprofile_mmcra_sipr = MMCRA_SIPR, - .machine_check = machine_check_generic, .platform = "power5+", }, { /* POWER6 in P5+ mode; 2.04-compliant processor */ @@ -390,7 +374,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .mmu_features = MMU_FTR_HPTE_TABLE, .icache_bsize = 128, .dcache_bsize = 128, - .machine_check = machine_check_generic, .oprofile_cpu_type = "ppc64/ibm-compat-v1", .oprofile_type = PPC_OPROFILE_POWER4, .platform = "power5+", @@ -413,7 +396,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR, .oprofile_mmcra_clear = POWER6_MMCRA_THRM | POWER6_MMCRA_OTHER, - .machine_check = machine_check_generic, .platform = "power6x", }, { /* 2.05-compliant processor, i.e. Power6 "architected" mode */ @@ -425,7 +407,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .mmu_features = MMU_FTR_HPTE_TABLE, .icache_bsize = 128, .dcache_bsize = 128, - .machine_check = machine_check_generic, .oprofile_cpu_type = "ppc64/ibm-compat-v1", .oprofile_type = PPC_OPROFILE_POWER4, .platform = "power6", @@ -440,7 +421,6 @@ static struct cpu_spec __initdata cpu_specs[] = { MMU_FTR_TLBIE_206, .icache_bsize = 128, .dcache_bsize = 128, - .machine_check = machine_check_generic, .oprofile_type = PPC_OPROFILE_POWER4, .oprofile_cpu_type = "ppc64/ibm-compat-v1", .platform = "power7", @@ -492,7 +472,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .pmc_type = PPC_PMC_IBM, .oprofile_cpu_type = "ppc64/cell-be", .oprofile_type = PPC_OPROFILE_CELL, - .machine_check = machine_check_generic, .platform = "ppc-cell-be", }, { /* PA Semi PA6T */ @@ -510,7 +489,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_restore = __restore_cpu_pa6t, .oprofile_cpu_type = "ppc64/pa6t", .oprofile_type = PPC_OPROFILE_PA6T, - .machine_check = machine_check_generic, .platform = "pa6t", }, { /* default match */ @@ -524,7 +502,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .dcache_bsize = 128, .num_pmcs = 6, .pmc_type = PPC_PMC_IBM, - .machine_check = machine_check_generic, .platform = "power4", } #endif /* CONFIG_PPC_BOOK3S_64 */ diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c index 832c8c4db25..3d569e2aff1 100644 --- a/arch/powerpc/kernel/crash.c +++ b/arch/powerpc/kernel/crash.c @@ -48,7 +48,7 @@ int crashing_cpu = -1; static cpumask_t cpus_in_crash = CPU_MASK_NONE; cpumask_t cpus_in_sr = CPU_MASK_NONE; -#define CRASH_HANDLER_MAX 2 +#define CRASH_HANDLER_MAX 3 /* NULL terminated list of shutdown handles */ static crash_shutdown_t crash_shutdown_handles[CRASH_HANDLER_MAX+1]; static DEFINE_SPINLOCK(crash_handlers_lock); @@ -125,7 +125,7 @@ static void crash_kexec_prepare_cpus(int cpu) smp_wmb(); /* - * FIXME: Until we will have the way to stop other CPUSs reliabally, + * FIXME: Until we will have the way to stop other CPUs reliably, * the crash CPU will send an IPI and wait for other CPUs to * respond. * Delay of at least 10 seconds. @@ -254,72 +254,6 @@ void crash_kexec_secondary(struct pt_regs *regs) cpus_in_sr = CPU_MASK_NONE; } #endif -#ifdef CONFIG_SPU_BASE - -#include <asm/spu.h> -#include <asm/spu_priv1.h> - -struct crash_spu_info { - struct spu *spu; - u32 saved_spu_runcntl_RW; - u32 saved_spu_status_R; - u32 saved_spu_npc_RW; - u64 saved_mfc_sr1_RW; - u64 saved_mfc_dar; - u64 saved_mfc_dsisr; -}; - -#define CRASH_NUM_SPUS 16 /* Enough for current hardware */ -static struct crash_spu_info crash_spu_info[CRASH_NUM_SPUS]; - -static void crash_kexec_stop_spus(void) -{ - struct spu *spu; - int i; - u64 tmp; - - for (i = 0; i < CRASH_NUM_SPUS; i++) { - if (!crash_spu_info[i].spu) - continue; - - spu = crash_spu_info[i].spu; - - crash_spu_info[i].saved_spu_runcntl_RW = - in_be32(&spu->problem->spu_runcntl_RW); - crash_spu_info[i].saved_spu_status_R = - in_be32(&spu->problem->spu_status_R); - crash_spu_info[i].saved_spu_npc_RW = - in_be32(&spu->problem->spu_npc_RW); - - crash_spu_info[i].saved_mfc_dar = spu_mfc_dar_get(spu); - crash_spu_info[i].saved_mfc_dsisr = spu_mfc_dsisr_get(spu); - tmp = spu_mfc_sr1_get(spu); - crash_spu_info[i].saved_mfc_sr1_RW = tmp; - - tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; - spu_mfc_sr1_set(spu, tmp); - - __delay(200); - } -} - -void crash_register_spus(struct list_head *list) -{ - struct spu *spu; - - list_for_each_entry(spu, list, full_list) { - if (WARN_ON(spu->number >= CRASH_NUM_SPUS)) - continue; - - crash_spu_info[spu->number].spu = spu; - } -} - -#else -static inline void crash_kexec_stop_spus(void) -{ -} -#endif /* CONFIG_SPU_BASE */ /* * Register a function to be called on shutdown. Only use this if you @@ -439,8 +373,6 @@ void default_machine_crash_shutdown(struct pt_regs *regs) crash_shutdown_cpu = -1; __debugger_fault_handler = old_handler; - crash_kexec_stop_spus(); - if (ppc_md.kexec_cpu_down) ppc_md.kexec_cpu_down(1, 0); } diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index c22dc1ec1c9..56212bc0ab0 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -880,7 +880,18 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) */ andi. r10,r9,MSR_EE beq 1f + /* + * Since the ftrace irqsoff latency trace checks CALLER_ADDR1, + * which is the stack frame here, we need to force a stack frame + * in case we came from user space. + */ + stwu r1,-32(r1) + mflr r0 + stw r0,4(r1) + stwu r1,-32(r1) bl trace_hardirqs_on + lwz r1,0(r1) + lwz r1,0(r1) lwz r9,_MSR(r1) 1: #endif /* CONFIG_TRACE_IRQFLAGS */ diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c index df7e20c191c..49a170af814 100644 --- a/arch/powerpc/kernel/machine_kexec.c +++ b/arch/powerpc/kernel/machine_kexec.c @@ -15,6 +15,7 @@ #include <linux/memblock.h> #include <linux/of.h> #include <linux/irq.h> +#include <linux/ftrace.h> #include <asm/machdep.h> #include <asm/prom.h> @@ -44,10 +45,7 @@ void machine_kexec_mask_interrupts(void) { void machine_crash_shutdown(struct pt_regs *regs) { - if (ppc_md.machine_crash_shutdown) - ppc_md.machine_crash_shutdown(regs); - else - default_machine_crash_shutdown(regs); + default_machine_crash_shutdown(regs); } /* @@ -65,8 +63,6 @@ int machine_kexec_prepare(struct kimage *image) void machine_kexec_cleanup(struct kimage *image) { - if (ppc_md.machine_kexec_cleanup) - ppc_md.machine_kexec_cleanup(image); } void arch_crash_save_vmcoreinfo(void) @@ -87,10 +83,13 @@ void arch_crash_save_vmcoreinfo(void) */ void machine_kexec(struct kimage *image) { - if (ppc_md.machine_kexec) - ppc_md.machine_kexec(image); - else - default_machine_kexec(image); + int save_ftrace_enabled; + + save_ftrace_enabled = __ftrace_enabled_save(); + + default_machine_kexec(image); + + __ftrace_enabled_restore(save_ftrace_enabled); /* Fall back to normal restart if we're still alive. */ machine_restart(NULL); diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c index 56748070578..ab6f6beadb5 100644 --- a/arch/powerpc/kernel/perf_event.c +++ b/arch/powerpc/kernel/perf_event.c @@ -1212,6 +1212,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val, if (left <= 0) left = period; record = 1; + event->hw.last_period = event->hw.sample_period; } if (left < 0x80000000LL) val = 0x80000000LL - left; diff --git a/arch/powerpc/kernel/perf_event_fsl_emb.c b/arch/powerpc/kernel/perf_event_fsl_emb.c index 4dcf5f831e9..b0dc8f7069c 100644 --- a/arch/powerpc/kernel/perf_event_fsl_emb.c +++ b/arch/powerpc/kernel/perf_event_fsl_emb.c @@ -596,6 +596,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val, if (left <= 0) left = period; record = 1; + event->hw.last_period = event->hw.sample_period; } if (left < 0x80000000LL) val = 0x80000000LL - left; diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 84906d3fc86..7a1d5cb7693 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -631,7 +631,7 @@ void show_regs(struct pt_regs * regs) #ifdef CONFIG_PPC_ADV_DEBUG_REGS printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr); #else - printk("DAR: "REG", DSISR: "REG"\n", regs->dar, regs->dsisr); + printk("DAR: "REG", DSISR: %08lx\n", regs->dar, regs->dsisr); #endif printk("TASK = %p[%d] '%s' THREAD: %p", current, task_pid_nr(current), current->comm, task_thread_info(current)); diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 9e3132db718..7185f0da7dc 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -519,9 +519,9 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size) memblock_add(base, size); } -u64 __init early_init_dt_alloc_memory_arch(u64 size, u64 align) +void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) { - return memblock_alloc(size, align); + return __va(memblock_alloc(size, align)); } #ifdef CONFIG_BLK_DEV_INITRD diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c index 2b442e6c21e..bf5f5ce3a7b 100644 --- a/arch/powerpc/kernel/rtas_flash.c +++ b/arch/powerpc/kernel/rtas_flash.c @@ -256,31 +256,16 @@ static ssize_t rtas_flash_read(struct file *file, char __user *buf, struct proc_dir_entry *dp = PDE(file->f_path.dentry->d_inode); struct rtas_update_flash_t *uf; char msg[RTAS_MSG_MAXLEN]; - int msglen; - uf = (struct rtas_update_flash_t *) dp->data; + uf = dp->data; if (!strcmp(dp->name, FIRMWARE_FLASH_NAME)) { get_flash_status_msg(uf->status, msg); } else { /* FIRMWARE_UPDATE_NAME */ sprintf(msg, "%d\n", uf->status); } - msglen = strlen(msg); - if (msglen > count) - msglen = count; - - if (ppos && *ppos != 0) - return 0; /* be cheap */ - - if (!access_ok(VERIFY_WRITE, buf, msglen)) - return -EINVAL; - if (copy_to_user(buf, msg, msglen)) - return -EFAULT; - - if (ppos) - *ppos = msglen; - return msglen; + return simple_read_from_buffer(buf, count, ppos, msg, strlen(msg)); } /* constructor for flash_block_cache */ @@ -394,26 +379,13 @@ static ssize_t manage_flash_read(struct file *file, char __user *buf, char msg[RTAS_MSG_MAXLEN]; int msglen; - args_buf = (struct rtas_manage_flash_t *) dp->data; + args_buf = dp->data; if (args_buf == NULL) return 0; msglen = sprintf(msg, "%d\n", args_buf->status); - if (msglen > count) - msglen = count; - if (ppos && *ppos != 0) - return 0; /* be cheap */ - - if (!access_ok(VERIFY_WRITE, buf, msglen)) - return -EINVAL; - - if (copy_to_user(buf, msg, msglen)) - return -EFAULT; - - if (ppos) - *ppos = msglen; - return msglen; + return simple_read_from_buffer(buf, count, ppos, msg, msglen); } static ssize_t manage_flash_write(struct file *file, const char __user *buf, @@ -495,24 +467,11 @@ static ssize_t validate_flash_read(struct file *file, char __user *buf, char msg[RTAS_MSG_MAXLEN]; int msglen; - args_buf = (struct rtas_validate_flash_t *) dp->data; + args_buf = dp->data; - if (ppos && *ppos != 0) - return 0; /* be cheap */ - msglen = get_validate_flash_msg(args_buf, msg); - if (msglen > count) - msglen = count; - - if (!access_ok(VERIFY_WRITE, buf, msglen)) - return -EINVAL; - - if (copy_to_user(buf, msg, msglen)) - return -EFAULT; - if (ppos) - *ppos = msglen; - return msglen; + return simple_read_from_buffer(buf, count, ppos, msg, msglen); } static ssize_t validate_flash_write(struct file *file, const char __user *buf, diff --git a/arch/powerpc/kernel/rtasd.c b/arch/powerpc/kernel/rtasd.c index 0438f819fe6..049dbecb5db 100644 --- a/arch/powerpc/kernel/rtasd.c +++ b/arch/powerpc/kernel/rtasd.c @@ -160,7 +160,7 @@ static int log_rtas_len(char * buf) /* rtas fixed header */ len = 8; err = (struct rtas_error_log *)buf; - if (err->extended_log_length) { + if (err->extended && err->extended_log_length) { /* extended header */ len += err->extended_log_length; diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index 09e4dea4a85..09d31dbf43f 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c @@ -265,11 +265,26 @@ void accumulate_stolen_time(void) { u64 sst, ust; - sst = scan_dispatch_log(get_paca()->starttime_user); - ust = scan_dispatch_log(get_paca()->starttime); - get_paca()->system_time -= sst; - get_paca()->user_time -= ust; - get_paca()->stolen_time += ust + sst; + u8 save_soft_enabled = local_paca->soft_enabled; + u8 save_hard_enabled = local_paca->hard_enabled; + + /* We are called early in the exception entry, before + * soft/hard_enabled are sync'ed to the expected state + * for the exception. We are hard disabled but the PACA + * needs to reflect that so various debug stuff doesn't + * complain + */ + local_paca->soft_enabled = 0; + local_paca->hard_enabled = 0; + + sst = scan_dispatch_log(local_paca->starttime_user); + ust = scan_dispatch_log(local_paca->starttime); + local_paca->system_time -= sst; + local_paca->user_time -= ust; + local_paca->stolen_time += ust + sst; + + local_paca->soft_enabled = save_soft_enabled; + local_paca->hard_enabled = save_hard_enabled; } static inline u64 calculate_stolen_time(u64 stop_tb) diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index 1b2cdc8eec9..bd74fac169b 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -626,12 +626,6 @@ void machine_check_exception(struct pt_regs *regs) if (recover > 0) return; - if (user_mode(regs)) { - regs->msr |= MSR_RI; - _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); - return; - } - #if defined(CONFIG_8xx) && defined(CONFIG_PCI) /* the qspan pci read routines can cause machine checks -- Cort * @@ -643,16 +637,12 @@ void machine_check_exception(struct pt_regs *regs) return; #endif - if (debugger_fault_handler(regs)) { - regs->msr |= MSR_RI; + if (debugger_fault_handler(regs)) return; - } if (check_io_access(regs)) return; - if (debugger_fault_handler(regs)) - return; die("Machine check", regs, SIGBUS); /* Must die if the interrupt is not recoverable */ diff --git a/arch/powerpc/lib/feature-fixups-test.S b/arch/powerpc/lib/feature-fixups-test.S index cb737484c5a..f4613118132 100644 --- a/arch/powerpc/lib/feature-fixups-test.S +++ b/arch/powerpc/lib/feature-fixups-test.S @@ -172,6 +172,25 @@ globl(ftr_fixup_test6_expected) 3: or 3,3,3 +#if 0 +/* Test that if we have a larger else case the assembler spots it and + * reports an error. #if 0'ed so as not to break the build normally. + */ +ftr_fixup_test7: + or 1,1,1 +BEGIN_FTR_SECTION + or 2,2,2 + or 2,2,2 + or 2,2,2 +FTR_SECTION_ELSE + or 3,3,3 + or 3,3,3 + or 3,3,3 + or 3,3,3 +ALT_FTR_SECTION_END(0, 1) + or 1,1,1 +#endif + #define MAKE_MACRO_TEST(TYPE) \ globl(ftr_fixup_test_ ##TYPE##_macros) \ or 1,1,1; \ diff --git a/arch/powerpc/platforms/83xx/mpc830x_rdb.c b/arch/powerpc/platforms/83xx/mpc830x_rdb.c index 661d354e4ff..d0c4e15b779 100644 --- a/arch/powerpc/platforms/83xx/mpc830x_rdb.c +++ b/arch/powerpc/platforms/83xx/mpc830x_rdb.c @@ -57,12 +57,12 @@ static void __init mpc830x_rdb_init_IRQ(void) ipic_set_default_priority(); } -struct const char *board[] __initdata = { +static const char *board[] __initdata = { "MPC8308RDB", "fsl,mpc8308rdb", "denx,mpc8308_p1m", NULL -} +}; /* * Called very early, MMU is off, device-tree isn't unflattened diff --git a/arch/powerpc/platforms/83xx/mpc831x_rdb.c b/arch/powerpc/platforms/83xx/mpc831x_rdb.c index b54cd736a89..f859ead49a8 100644 --- a/arch/powerpc/platforms/83xx/mpc831x_rdb.c +++ b/arch/powerpc/platforms/83xx/mpc831x_rdb.c @@ -60,11 +60,11 @@ static void __init mpc831x_rdb_init_IRQ(void) ipic_set_default_priority(); } -struct const char *board[] __initdata = { +static const char *board[] __initdata = { "MPC8313ERDB", "fsl,mpc8315erdb", NULL -} +}; /* * Called very early, MMU is off, device-tree isn't unflattened diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h index 0fea8811d45..82a434510d8 100644 --- a/arch/powerpc/platforms/83xx/mpc83xx.h +++ b/arch/powerpc/platforms/83xx/mpc83xx.h @@ -35,6 +35,8 @@ /* system i/o configuration register high */ #define MPC83XX_SICRH_OFFS 0x118 +#define MPC8308_SICRH_USB_MASK 0x000c0000 +#define MPC8308_SICRH_USB_ULPI 0x00040000 #define MPC834X_SICRH_USB_UTMI 0x00020000 #define MPC831X_SICRH_USB_MASK 0x000000e0 #define MPC831X_SICRH_USB_ULPI 0x000000a0 diff --git a/arch/powerpc/platforms/83xx/usb.c b/arch/powerpc/platforms/83xx/usb.c index 3ba4bb7d41b..2c64164722d 100644 --- a/arch/powerpc/platforms/83xx/usb.c +++ b/arch/powerpc/platforms/83xx/usb.c @@ -127,7 +127,8 @@ int mpc831x_usb_cfg(void) /* Configure clock */ immr_node = of_get_parent(np); - if (immr_node && of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) + if (immr_node && (of_device_is_compatible(immr_node, "fsl,mpc8315-immr") || + of_device_is_compatible(immr_node, "fsl,mpc8308-immr"))) clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, MPC8315_SCCR_USB_MASK, MPC8315_SCCR_USB_DRCM_01); @@ -138,7 +139,11 @@ int mpc831x_usb_cfg(void) /* Configure pin mux for ULPI. There is no pin mux for UTMI */ if (prop && !strcmp(prop, "ulpi")) { - if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) { + if (of_device_is_compatible(immr_node, "fsl,mpc8308-immr")) { + clrsetbits_be32(immap + MPC83XX_SICRH_OFFS, + MPC8308_SICRH_USB_MASK, + MPC8308_SICRH_USB_ULPI); + } else if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) { clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC8315_SICRL_USB_MASK, MPC8315_SICRL_USB_ULPI); @@ -173,6 +178,9 @@ int mpc831x_usb_cfg(void) !strcmp(prop, "utmi"))) { u32 refsel; + if (of_device_is_compatible(immr_node, "fsl,mpc8308-immr")) + goto out; + if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) refsel = CONTROL_REFSEL_24MHZ; else @@ -186,9 +194,11 @@ int mpc831x_usb_cfg(void) temp = CONTROL_PHY_CLK_SEL_ULPI; #ifdef CONFIG_USB_OTG /* Set OTG_PORT */ - dr_mode = of_get_property(np, "dr_mode", NULL); - if (dr_mode && !strcmp(dr_mode, "otg")) - temp |= CONTROL_OTG_PORT; + if (!of_device_is_compatible(immr_node, "fsl,mpc8308-immr")) { + dr_mode = of_get_property(np, "dr_mode", NULL); + if (dr_mode && !strcmp(dr_mode, "otg")) + temp |= CONTROL_OTG_PORT; + } #endif /* CONFIG_USB_OTG */ out_be32(usb_regs + FSL_USB2_CONTROL_OFFS, temp); } else { @@ -196,6 +206,7 @@ int mpc831x_usb_cfg(void) ret = -EINVAL; } +out: iounmap(usb_regs); of_node_put(np); return ret; diff --git a/arch/powerpc/platforms/cell/cpufreq_spudemand.c b/arch/powerpc/platforms/cell/cpufreq_spudemand.c index 968c1c0b4d5..d809836bcf5 100644 --- a/arch/powerpc/platforms/cell/cpufreq_spudemand.c +++ b/arch/powerpc/platforms/cell/cpufreq_spudemand.c @@ -39,8 +39,6 @@ struct spu_gov_info_struct { }; static DEFINE_PER_CPU(struct spu_gov_info_struct, spu_gov_info); -static struct workqueue_struct *kspugov_wq; - static int calc_freq(struct spu_gov_info_struct *info) { int cpu; @@ -71,14 +69,14 @@ static void spu_gov_work(struct work_struct *work) __cpufreq_driver_target(info->policy, target_freq, CPUFREQ_RELATION_H); delay = usecs_to_jiffies(info->poll_int); - queue_delayed_work_on(info->policy->cpu, kspugov_wq, &info->work, delay); + schedule_delayed_work_on(info->policy->cpu, &info->work, delay); } static void spu_gov_init_work(struct spu_gov_info_struct *info) { int delay = usecs_to_jiffies(info->poll_int); INIT_DELAYED_WORK_DEFERRABLE(&info->work, spu_gov_work); - queue_delayed_work_on(info->policy->cpu, kspugov_wq, &info->work, delay); + schedule_delayed_work_on(info->policy->cpu, &info->work, delay); } static void spu_gov_cancel_work(struct spu_gov_info_struct *info) @@ -152,27 +150,15 @@ static int __init spu_gov_init(void) { int ret; - kspugov_wq = create_workqueue("kspugov"); - if (!kspugov_wq) { - printk(KERN_ERR "creation of kspugov failed\n"); - ret = -EFAULT; - goto out; - } - ret = cpufreq_register_governor(&spu_governor); - if (ret) { + if (ret) printk(KERN_ERR "registration of governor failed\n"); - destroy_workqueue(kspugov_wq); - goto out; - } -out: return ret; } static void __exit spu_gov_exit(void) { cpufreq_unregister_governor(&spu_governor); - destroy_workqueue(kspugov_wq); } diff --git a/arch/powerpc/platforms/cell/qpace_setup.c b/arch/powerpc/platforms/cell/qpace_setup.c index 1b574904275..d31c594cfdf 100644 --- a/arch/powerpc/platforms/cell/qpace_setup.c +++ b/arch/powerpc/platforms/cell/qpace_setup.c @@ -145,9 +145,4 @@ define_machine(qpace) { .calibrate_decr = generic_calibrate_decr, .progress = qpace_progress, .init_IRQ = iic_init_IRQ, -#ifdef CONFIG_KEXEC - .machine_kexec = default_machine_kexec, - .machine_kexec_prepare = default_machine_kexec_prepare, - .machine_crash_shutdown = default_machine_crash_shutdown, -#endif }; diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c index 8547e86bfb4..acfaccea5f4 100644 --- a/arch/powerpc/platforms/cell/spu_base.c +++ b/arch/powerpc/platforms/cell/spu_base.c @@ -37,6 +37,7 @@ #include <asm/spu_csa.h> #include <asm/xmon.h> #include <asm/prom.h> +#include <asm/kexec.h> const struct spu_management_ops *spu_management_ops; EXPORT_SYMBOL_GPL(spu_management_ops); @@ -727,6 +728,75 @@ static ssize_t spu_stat_show(struct sys_device *sysdev, static SYSDEV_ATTR(stat, 0644, spu_stat_show, NULL); +#ifdef CONFIG_KEXEC + +struct crash_spu_info { + struct spu *spu; + u32 saved_spu_runcntl_RW; + u32 saved_spu_status_R; + u32 saved_spu_npc_RW; + u64 saved_mfc_sr1_RW; + u64 saved_mfc_dar; + u64 saved_mfc_dsisr; +}; + +#define CRASH_NUM_SPUS 16 /* Enough for current hardware */ +static struct crash_spu_info crash_spu_info[CRASH_NUM_SPUS]; + +static void crash_kexec_stop_spus(void) +{ + struct spu *spu; + int i; + u64 tmp; + + for (i = 0; i < CRASH_NUM_SPUS; i++) { + if (!crash_spu_info[i].spu) + continue; + + spu = crash_spu_info[i].spu; + + crash_spu_info[i].saved_spu_runcntl_RW = + in_be32(&spu->problem->spu_runcntl_RW); + crash_spu_info[i].saved_spu_status_R = + in_be32(&spu->problem->spu_status_R); + crash_spu_info[i].saved_spu_npc_RW = + in_be32(&spu->problem->spu_npc_RW); + + crash_spu_info[i].saved_mfc_dar = spu_mfc_dar_get(spu); + crash_spu_info[i].saved_mfc_dsisr = spu_mfc_dsisr_get(spu); + tmp = spu_mfc_sr1_get(spu); + crash_spu_info[i].saved_mfc_sr1_RW = tmp; + + tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; + spu_mfc_sr1_set(spu, tmp); + + __delay(200); + } +} + +static void crash_register_spus(struct list_head *list) +{ + struct spu *spu; + int ret; + + list_for_each_entry(spu, list, full_list) { + if (WARN_ON(spu->number >= CRASH_NUM_SPUS)) + continue; + + crash_spu_info[spu->number].spu = spu; + } + + ret = crash_shutdown_register(&crash_kexec_stop_spus); + if (ret) + printk(KERN_ERR "Could not register SPU crash handler"); +} + +#else +static inline void crash_register_spus(struct list_head *list) +{ +} +#endif + static int __init init_spu_base(void) { int i, ret = 0; diff --git a/arch/powerpc/platforms/cell/spufs/file.c b/arch/powerpc/platforms/cell/spufs/file.c index 02f7b113a31..3c7c3f82d84 100644 --- a/arch/powerpc/platforms/cell/spufs/file.c +++ b/arch/powerpc/platforms/cell/spufs/file.c @@ -219,24 +219,17 @@ spufs_mem_write(struct file *file, const char __user *buffer, loff_t pos = *ppos; int ret; - if (pos < 0) - return -EINVAL; if (pos > LS_SIZE) return -EFBIG; - if (size > LS_SIZE - pos) - size = LS_SIZE - pos; ret = spu_acquire(ctx); if (ret) return ret; local_store = ctx->ops->get_ls(ctx); - ret = copy_from_user(local_store + pos, buffer, size); + size = simple_write_to_buffer(local_store, LS_SIZE, ppos, buffer, size); spu_release(ctx); - if (ret) - return -EFAULT; - *ppos = pos + size; return size; } @@ -574,18 +567,15 @@ spufs_regs_write(struct file *file, const char __user *buffer, if (*pos >= sizeof(lscsa->gprs)) return -EFBIG; - size = min_t(ssize_t, sizeof(lscsa->gprs) - *pos, size); - *pos += size; - ret = spu_acquire_saved(ctx); if (ret) return ret; - ret = copy_from_user((char *)lscsa->gprs + *pos - size, - buffer, size) ? -EFAULT : size; + size = simple_write_to_buffer(lscsa->gprs, sizeof(lscsa->gprs), pos, + buffer, size); spu_release_saved(ctx); - return ret; + return size; } static const struct file_operations spufs_regs_fops = { @@ -630,18 +620,15 @@ spufs_fpcr_write(struct file *file, const char __user * buffer, if (*pos >= sizeof(lscsa->fpcr)) return -EFBIG; - size = min_t(ssize_t, sizeof(lscsa->fpcr) - *pos, size); - ret = spu_acquire_saved(ctx); if (ret) return ret; - *pos += size; - ret = copy_from_user((char *)&lscsa->fpcr + *pos - size, - buffer, size) ? -EFAULT : size; + size = simple_write_to_buffer(&lscsa->fpcr, sizeof(lscsa->fpcr), pos, + buffer, size); spu_release_saved(ctx); - return ret; + return size; } static const struct file_operations spufs_fpcr_fops = { diff --git a/arch/powerpc/platforms/embedded6xx/gamecube.c b/arch/powerpc/platforms/embedded6xx/gamecube.c index 1106fd99627..a138e14bad2 100644 --- a/arch/powerpc/platforms/embedded6xx/gamecube.c +++ b/arch/powerpc/platforms/embedded6xx/gamecube.c @@ -75,14 +75,6 @@ static void gamecube_shutdown(void) flipper_quiesce(); } -#ifdef CONFIG_KEXEC -static int gamecube_kexec_prepare(struct kimage *image) -{ - return 0; -} -#endif /* CONFIG_KEXEC */ - - define_machine(gamecube) { .name = "gamecube", .probe = gamecube_probe, @@ -95,9 +87,6 @@ define_machine(gamecube) { .calibrate_decr = generic_calibrate_decr, .progress = udbg_progress, .machine_shutdown = gamecube_shutdown, -#ifdef CONFIG_KEXEC - .machine_kexec_prepare = gamecube_kexec_prepare, -#endif }; diff --git a/arch/powerpc/platforms/embedded6xx/wii.c b/arch/powerpc/platforms/embedded6xx/wii.c index 649473a729b..1b5dc1a2e14 100644 --- a/arch/powerpc/platforms/embedded6xx/wii.c +++ b/arch/powerpc/platforms/embedded6xx/wii.c @@ -18,7 +18,6 @@ #include <linux/init.h> #include <linux/irq.h> #include <linux/seq_file.h> -#include <linux/kexec.h> #include <linux/of_platform.h> #include <linux/memblock.h> #include <mm/mmu_decl.h> @@ -226,13 +225,6 @@ static void wii_shutdown(void) flipper_quiesce(); } -#ifdef CONFIG_KEXEC -static int wii_machine_kexec_prepare(struct kimage *image) -{ - return 0; -} -#endif /* CONFIG_KEXEC */ - define_machine(wii) { .name = "wii", .probe = wii_probe, @@ -246,9 +238,6 @@ define_machine(wii) { .calibrate_decr = generic_calibrate_decr, .progress = udbg_progress, .machine_shutdown = wii_shutdown, -#ifdef CONFIG_KEXEC - .machine_kexec_prepare = wii_machine_kexec_prepare, -#endif }; static struct of_device_id wii_of_bus[] = { diff --git a/arch/powerpc/platforms/iseries/Kconfig b/arch/powerpc/platforms/iseries/Kconfig index 47a20cfb448..e5bc9f75d47 100644 --- a/arch/powerpc/platforms/iseries/Kconfig +++ b/arch/powerpc/platforms/iseries/Kconfig @@ -2,7 +2,7 @@ config PPC_ISERIES bool "IBM Legacy iSeries" depends on PPC64 && PPC_BOOK3S select PPC_INDIRECT_IO - select PPC_PCI_CHOICE if EMBEDDED + select PPC_PCI_CHOICE if EXPERT menu "iSeries device drivers" depends on PPC_ISERIES diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig index 5d1b743dbe7..5b3da4b4ea7 100644 --- a/arch/powerpc/platforms/pseries/Kconfig +++ b/arch/powerpc/platforms/pseries/Kconfig @@ -10,7 +10,7 @@ config PPC_PSERIES select RTAS_ERROR_LOGGING select PPC_UDBG_16550 select PPC_NATIVE - select PPC_PCI_CHOICE if EMBEDDED + select PPC_PCI_CHOICE if EXPERT default y config PPC_SPLPAR @@ -24,9 +24,9 @@ config PPC_SPLPAR two or more partitions. config EEH - bool "PCI Extended Error Handling (EEH)" if EMBEDDED + bool "PCI Extended Error Handling (EEH)" if EXPERT depends on PPC_PSERIES && PCI - default y if !EMBEDDED + default y if !EXPERT config PSERIES_MSI bool diff --git a/arch/powerpc/platforms/pseries/kexec.c b/arch/powerpc/platforms/pseries/kexec.c index 53cbd53d874..77d38a5e2ff 100644 --- a/arch/powerpc/platforms/pseries/kexec.c +++ b/arch/powerpc/platforms/pseries/kexec.c @@ -61,13 +61,3 @@ void __init setup_kexec_cpu_down_xics(void) { ppc_md.kexec_cpu_down = pseries_kexec_cpu_down_xics; } - -static int __init pseries_kexec_setup(void) -{ - ppc_md.machine_kexec = default_machine_kexec; - ppc_md.machine_kexec_prepare = default_machine_kexec_prepare; - ppc_md.machine_crash_shutdown = default_machine_crash_shutdown; - - return 0; -} -machine_device_initcall(pseries, pseries_kexec_setup); diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c index a4fc6da87c2..c55d7ad9c64 100644 --- a/arch/powerpc/platforms/pseries/ras.c +++ b/arch/powerpc/platforms/pseries/ras.c @@ -54,7 +54,8 @@ static unsigned char ras_log_buf[RTAS_ERROR_LOG_MAX]; static DEFINE_SPINLOCK(ras_log_buf_lock); -static char mce_data_buf[RTAS_ERROR_LOG_MAX]; +static char global_mce_data_buf[RTAS_ERROR_LOG_MAX]; +static DEFINE_PER_CPU(__u64, mce_data_buf); static int ras_get_sensor_state_token; static int ras_check_exception_token; @@ -196,12 +197,24 @@ static irqreturn_t ras_error_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -/* Get the error information for errors coming through the +/* + * Some versions of FWNMI place the buffer inside the 4kB page starting at + * 0x7000. Other versions place it inside the rtas buffer. We check both. + */ +#define VALID_FWNMI_BUFFER(A) \ + ((((A) >= 0x7000) && ((A) < 0x7ff0)) || \ + (((A) >= rtas.base) && ((A) < (rtas.base + rtas.size - 16)))) + +/* + * Get the error information for errors coming through the * FWNMI vectors. The pt_regs' r3 will be updated to reflect * the actual r3 if possible, and a ptr to the error log entry * will be returned if found. * - * The mce_data_buf does not have any locks or protection around it, + * If the RTAS error is not of the extended type, then we put it in a per + * cpu 64bit buffer. If it is the extended type we use global_mce_data_buf. + * + * The global_mce_data_buf does not have any locks or protection around it, * if a second machine check comes in, or a system reset is done * before we have logged the error, then we will get corruption in the * error log. This is preferable over holding off on calling @@ -210,20 +223,31 @@ static irqreturn_t ras_error_interrupt(int irq, void *dev_id) */ static struct rtas_error_log *fwnmi_get_errinfo(struct pt_regs *regs) { - unsigned long errdata = regs->gpr[3]; - struct rtas_error_log *errhdr = NULL; unsigned long *savep; + struct rtas_error_log *h, *errhdr = NULL; + + if (!VALID_FWNMI_BUFFER(regs->gpr[3])) { + printk(KERN_ERR "FWNMI: corrupt r3\n"); + return NULL; + } - if ((errdata >= 0x7000 && errdata < 0x7fff0) || - (errdata >= rtas.base && errdata < rtas.base + rtas.size - 16)) { - savep = __va(errdata); - regs->gpr[3] = savep[0]; /* restore original r3 */ - memset(mce_data_buf, 0, RTAS_ERROR_LOG_MAX); - memcpy(mce_data_buf, (char *)(savep + 1), RTAS_ERROR_LOG_MAX); - errhdr = (struct rtas_error_log *)mce_data_buf; + savep = __va(regs->gpr[3]); + regs->gpr[3] = savep[0]; /* restore original r3 */ + + /* If it isn't an extended log we can use the per cpu 64bit buffer */ + h = (struct rtas_error_log *)&savep[1]; + if (!h->extended) { + memcpy(&__get_cpu_var(mce_data_buf), h, sizeof(__u64)); + errhdr = (struct rtas_error_log *)&__get_cpu_var(mce_data_buf); } else { - printk("FWNMI: corrupt r3\n"); + int len; + + len = max_t(int, 8+h->extended_log_length, RTAS_ERROR_LOG_MAX); + memset(global_mce_data_buf, 0, RTAS_ERROR_LOG_MAX); + memcpy(global_mce_data_buf, h, len); + errhdr = (struct rtas_error_log *)global_mce_data_buf; } + return errhdr; } @@ -235,7 +259,7 @@ static void fwnmi_release_errinfo(void) { int ret = rtas_call(rtas_token("ibm,nmi-interlock"), 0, 1, NULL); if (ret != 0) - printk("FWNMI: nmi-interlock failed: %d\n", ret); + printk(KERN_ERR "FWNMI: nmi-interlock failed: %d\n", ret); } int pSeries_system_reset_exception(struct pt_regs *regs) @@ -259,31 +283,43 @@ int pSeries_system_reset_exception(struct pt_regs *regs) * Return 1 if corrected (or delivered a signal). * Return 0 if there is nothing we can do. */ -static int recover_mce(struct pt_regs *regs, struct rtas_error_log * err) +static int recover_mce(struct pt_regs *regs, struct rtas_error_log *err) { - int nonfatal = 0; + int recovered = 0; - if (err->disposition == RTAS_DISP_FULLY_RECOVERED) { + if (!(regs->msr & MSR_RI)) { + /* If MSR_RI isn't set, we cannot recover */ + recovered = 0; + + } else if (err->disposition == RTAS_DISP_FULLY_RECOVERED) { /* Platform corrected itself */ - nonfatal = 1; - } else if ((regs->msr & MSR_RI) && - user_mode(regs) && - err->severity == RTAS_SEVERITY_ERROR_SYNC && - err->disposition == RTAS_DISP_NOT_RECOVERED && - err->target == RTAS_TARGET_MEMORY && - err->type == RTAS_TYPE_ECC_UNCORR && - !(current->pid == 0 || is_global_init(current))) { - /* Kill off a user process with an ECC error */ - printk(KERN_ERR "MCE: uncorrectable ecc error for pid %d\n", - current->pid); - /* XXX something better for ECC error? */ - _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); - nonfatal = 1; + recovered = 1; + + } else if (err->disposition == RTAS_DISP_LIMITED_RECOVERY) { + /* Platform corrected itself but could be degraded */ + printk(KERN_ERR "MCE: limited recovery, system may " + "be degraded\n"); + recovered = 1; + + } else if (user_mode(regs) && !is_global_init(current) && + err->severity == RTAS_SEVERITY_ERROR_SYNC) { + + /* + * If we received a synchronous error when in userspace + * kill the task. Firmware may report details of the fail + * asynchronously, so we can't rely on the target and type + * fields being valid here. + */ + printk(KERN_ERR "MCE: uncorrectable error, killing task " + "%s:%d\n", current->comm, current->pid); + + _exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip); + recovered = 1; } - log_error((char *)err, ERR_TYPE_RTAS_LOG, !nonfatal); + log_error((char *)err, ERR_TYPE_RTAS_LOG, 0); - return nonfatal; + return recovered; } /* diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c index 9f99bef2ade..8c6cab01327 100644 --- a/arch/powerpc/sysdev/fsl_rio.c +++ b/arch/powerpc/sysdev/fsl_rio.c @@ -1555,8 +1555,6 @@ int fsl_rio_setup(struct platform_device *dev) saved_mcheck_exception = ppc_md.machine_check_exception; ppc_md.machine_check_exception = fsl_rio_mcheck_exception; #endif - /* Ensure that RFXE is set */ - mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000)); return 0; err: diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 7c1342618a3..b0c8469e5dd 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -674,7 +674,8 @@ void mpic_unmask_irq(unsigned int irq) /* make sure mask gets to controller before we return to user */ do { if (!loops--) { - printk(KERN_ERR "mpic_enable_irq timeout\n"); + printk(KERN_ERR "%s: timeout on hwirq %u\n", + __func__, src); break; } } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); @@ -695,7 +696,8 @@ void mpic_mask_irq(unsigned int irq) /* make sure mask gets to controller before we return to user */ do { if (!loops--) { - printk(KERN_ERR "mpic_enable_irq timeout\n"); + printk(KERN_ERR "%s: timeout on hwirq %u\n", + __func__, src); break; } } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); diff --git a/arch/s390/defconfig b/arch/s390/defconfig index d79697157ac..29c82c640a8 100644 --- a/arch/s390/defconfig +++ b/arch/s390/defconfig @@ -5,10 +5,21 @@ CONFIG_AUDIT=y CONFIG_RCU_TRACE=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_MEM_RES_CTLR=y +CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_CGROUP=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y CONFIG_KPROBES=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y @@ -19,7 +30,9 @@ CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y CONFIG_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTREMOVE=y +CONFIG_KSM=y CONFIG_BINFMT_MISC=m +CONFIG_CMM=m CONFIG_HZ_100=y CONFIG_KEXEC=y CONFIG_PM=y @@ -105,6 +118,7 @@ CONFIG_DEBUG_LIST=y CONFIG_DEBUG_NOTIFIERS=y # CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_KPROBES_SANITY_TEST=y +CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y CONFIG_CPU_NOTIFIER_ERROR_INJECT=m CONFIG_LATENCYTOP=y CONFIG_SYSCTL_SYSCALL_CHECK=y diff --git a/arch/s390/include/asm/compat.h b/arch/s390/include/asm/compat.h index a875c2f542e..da359ca6fe5 100644 --- a/arch/s390/include/asm/compat.h +++ b/arch/s390/include/asm/compat.h @@ -169,7 +169,7 @@ static inline compat_uptr_t ptr_to_compat(void __user *uptr) static inline int is_compat_task(void) { - return test_thread_flag(TIF_31BIT); + return is_32bit_task(); } #else diff --git a/arch/s390/include/asm/elf.h b/arch/s390/include/asm/elf.h index 354d42616c7..10c029cfcc7 100644 --- a/arch/s390/include/asm/elf.h +++ b/arch/s390/include/asm/elf.h @@ -161,7 +161,9 @@ extern unsigned int vdso_enabled; use of this is to invoke "./ld.so someprog" to test out a new version of the loader. We need to make sure that it is out of the way of the program that it will "exec", and that there is sufficient room for the brk. */ -#define ELF_ET_DYN_BASE (STACK_TOP / 3 * 2) + +extern unsigned long randomize_et_dyn(unsigned long base); +#define ELF_ET_DYN_BASE (randomize_et_dyn(STACK_TOP / 3 * 2)) /* This yields a mask that user programs can use to figure out what instruction set this CPU supports. */ @@ -206,6 +208,8 @@ do { \ current->mm->context.noexec == 0; \ }) +#define STACK_RND_MASK 0x7ffUL + #define ARCH_DLINFO \ do { \ if (vdso_enabled) \ @@ -218,4 +222,7 @@ struct linux_binprm; #define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1 int arch_setup_additional_pages(struct linux_binprm *, int); +extern unsigned long arch_randomize_brk(struct mm_struct *mm); +#define arch_randomize_brk arch_randomize_brk + #endif diff --git a/arch/s390/include/asm/system.h b/arch/s390/include/asm/system.h index 6710b0eac16..8f8d759f6a7 100644 --- a/arch/s390/include/asm/system.h +++ b/arch/s390/include/asm/system.h @@ -449,7 +449,7 @@ extern void (*_machine_restart)(char *command); extern void (*_machine_halt)(void); extern void (*_machine_power_off)(void); -#define arch_align_stack(x) (x) +extern unsigned long arch_align_stack(unsigned long sp); static inline int tprot(unsigned long addr) { diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h index ebc77091466..ad1382f7932 100644 --- a/arch/s390/include/asm/thread_info.h +++ b/arch/s390/include/asm/thread_info.h @@ -118,6 +118,12 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_SINGLE_STEP (1<<TIF_FREEZE) #define _TIF_FREEZE (1<<TIF_FREEZE) +#ifdef CONFIG_64BIT +#define is_32bit_task() (test_thread_flag(TIF_31BIT)) +#else +#define is_32bit_task() (1) +#endif + #endif /* __KERNEL__ */ #define PREEMPT_ACTIVE 0x4000000 diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c index 6ba42222b54..a895e69379f 100644 --- a/arch/s390/kernel/process.c +++ b/arch/s390/kernel/process.c @@ -30,9 +30,11 @@ #include <linux/tick.h> #include <linux/elfcore.h> #include <linux/kernel_stat.h> +#include <linux/personality.h> #include <linux/syscalls.h> #include <linux/compat.h> #include <linux/kprobes.h> +#include <linux/random.h> #include <asm/compat.h> #include <asm/uaccess.h> #include <asm/pgtable.h> @@ -332,3 +334,39 @@ unsigned long get_wchan(struct task_struct *p) } return 0; } + +unsigned long arch_align_stack(unsigned long sp) +{ + if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) + sp -= get_random_int() & ~PAGE_MASK; + return sp & ~0xf; +} + +static inline unsigned long brk_rnd(void) +{ + /* 8MB for 32bit, 1GB for 64bit */ + if (is_32bit_task()) + return (get_random_int() & 0x7ffUL) << PAGE_SHIFT; + else + return (get_random_int() & 0x3ffffUL) << PAGE_SHIFT; +} + +unsigned long arch_randomize_brk(struct mm_struct *mm) +{ + unsigned long ret = PAGE_ALIGN(mm->brk + brk_rnd()); + + if (ret < mm->brk) + return mm->brk; + return ret; +} + +unsigned long randomize_et_dyn(unsigned long base) +{ + unsigned long ret = PAGE_ALIGN(base + brk_rnd()); + + if (!(current->flags & PF_RANDOMIZE)) + return base; + if (ret < base) + return base; + return ret; +} diff --git a/arch/s390/kernel/vdso.c b/arch/s390/kernel/vdso.c index e3150dd2fe7..f438d74dedb 100644 --- a/arch/s390/kernel/vdso.c +++ b/arch/s390/kernel/vdso.c @@ -203,7 +203,6 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) if (!uses_interp) return 0; - vdso_base = mm->mmap_base; #ifdef CONFIG_64BIT vdso_pagelist = vdso64_pagelist; vdso_pages = vdso64_pages; @@ -233,8 +232,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) * fail and end up putting it elsewhere. */ down_write(&mm->mmap_sem); - vdso_base = get_unmapped_area(NULL, vdso_base, - vdso_pages << PAGE_SHIFT, 0, 0); + vdso_base = get_unmapped_area(NULL, 0, vdso_pages << PAGE_SHIFT, 0, 0); if (IS_ERR_VALUE(vdso_base)) { rc = vdso_base; goto out_up; diff --git a/arch/s390/mm/mmap.c b/arch/s390/mm/mmap.c index 869efbaed3e..c9a9f7f1818 100644 --- a/arch/s390/mm/mmap.c +++ b/arch/s390/mm/mmap.c @@ -27,17 +27,44 @@ #include <linux/personality.h> #include <linux/mm.h> #include <linux/module.h> +#include <linux/random.h> #include <asm/pgalloc.h> #include <asm/compat.h> +static unsigned long stack_maxrandom_size(void) +{ + if (!(current->flags & PF_RANDOMIZE)) + return 0; + if (current->personality & ADDR_NO_RANDOMIZE) + return 0; + return STACK_RND_MASK << PAGE_SHIFT; +} + /* * Top of mmap area (just below the process stack). * - * Leave an at least ~128 MB hole. + * Leave at least a ~32 MB hole. */ -#define MIN_GAP (128*1024*1024) +#define MIN_GAP (32*1024*1024) #define MAX_GAP (STACK_TOP/6*5) +static inline int mmap_is_legacy(void) +{ + if (current->personality & ADDR_COMPAT_LAYOUT) + return 1; + if (rlimit(RLIMIT_STACK) == RLIM_INFINITY) + return 1; + return sysctl_legacy_va_layout; +} + +static unsigned long mmap_rnd(void) +{ + if (!(current->flags & PF_RANDOMIZE)) + return 0; + /* 8MB randomization for mmap_base */ + return (get_random_int() & 0x7ffUL) << PAGE_SHIFT; +} + static inline unsigned long mmap_base(void) { unsigned long gap = rlimit(RLIMIT_STACK); @@ -46,22 +73,8 @@ static inline unsigned long mmap_base(void) gap = MIN_GAP; else if (gap > MAX_GAP) gap = MAX_GAP; - - return STACK_TOP - (gap & PAGE_MASK); -} - -static inline int mmap_is_legacy(void) -{ -#ifdef CONFIG_64BIT - /* - * Force standard allocation for 64 bit programs. - */ - if (!is_compat_task()) - return 1; -#endif - return sysctl_legacy_va_layout || - (current->personality & ADDR_COMPAT_LAYOUT) || - rlimit(RLIMIT_STACK) == RLIM_INFINITY; + gap &= PAGE_MASK; + return STACK_TOP - stack_maxrandom_size() - mmap_rnd() - gap; } #ifndef CONFIG_64BIT diff --git a/arch/score/Kconfig b/arch/score/Kconfig index 4293fdcb539..27b2295f41f 100644 --- a/arch/score/Kconfig +++ b/arch/score/Kconfig @@ -1,5 +1,9 @@ menu "Machine selection" +config SCORE + def_bool y + select HAVE_GENERIC_HARDIRQS + choice prompt "System type" default MACH_SPCT6600 @@ -53,9 +57,6 @@ config GENERIC_CLOCKEVENTS config SCHED_NO_NO_OMIT_FRAME_POINTER def_bool y -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config GENERIC_SYSCALL_TABLE def_bool y @@ -68,9 +69,6 @@ menu "Kernel type" config 32BIT def_bool y -config GENERIC_HARDIRQS - def_bool y - config ARCH_FLATMEM_ENABLE def_bool y diff --git a/arch/score/configs/spct6600_defconfig b/arch/score/configs/spct6600_defconfig index 9883c50e463..df1edbf507a 100644 --- a/arch/score/configs/spct6600_defconfig +++ b/arch/score/configs/spct6600_defconfig @@ -9,7 +9,7 @@ CONFIG_LOG_BUF_SHIFT=12 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set CONFIG_SLAB=y diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 8d411bdca9b..8a9011dced1 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -1,6 +1,6 @@ config SUPERH def_bool y - select EMBEDDED + select EXPERT select CLKDEV_LOOKUP select HAVE_IDE if HAS_IOPORT select HAVE_MEMBLOCK diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c index 83972aa319c..c19e2a940e3 100644 --- a/arch/sh/kernel/cpu/shmobile/cpuidle.c +++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c @@ -81,7 +81,6 @@ void sh_mobile_setup_cpuidle(void) state->target_residency = 1 * 2; state->power_usage = 3; state->flags = 0; - state->flags |= CPUIDLE_FLAG_SHALLOW; state->flags |= CPUIDLE_FLAG_TIME_VALID; state->enter = cpuidle_sleep_enter; diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 45d9c87d083..95695e97703 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -50,6 +50,7 @@ config SPARC64 select RTC_DRV_STARFIRE select HAVE_PERF_EVENTS select PERF_USE_VMALLOC + select HAVE_GENERIC_HARDIRQS config ARCH_DEFCONFIG string @@ -107,10 +108,6 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK config NEED_PER_CPU_PAGE_FIRST_CHUNK def_bool y if SPARC64 -config GENERIC_HARDIRQS_NO__DO_IRQ - bool - def_bool y if SPARC64 - config MMU bool default y @@ -276,10 +273,6 @@ config HOTPLUG_CPU can be controlled through /sys/devices/system/cpu/cpu#. Say N if you want to disable CPU hotplug. -config GENERIC_HARDIRQS - bool - default y if SPARC64 - source "kernel/time/Kconfig" if SPARC64 diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig index e11b5fcb70e..08948e4e150 100644 --- a/arch/tile/Kconfig +++ b/arch/tile/Kconfig @@ -1,24 +1,33 @@ # For a description of the syntax of this configuration file, # see Documentation/kbuild/config-language.txt. -config MMU - def_bool y - -config GENERIC_CSUM - def_bool y - -config GENERIC_HARDIRQS +config TILE def_bool y + select HAVE_KVM if !TILEGX + select GENERIC_FIND_FIRST_BIT + select GENERIC_FIND_NEXT_BIT + select USE_GENERIC_SMP_HELPERS + select CC_OPTIMIZE_FOR_SIZE + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE + select GENERIC_PENDING_IRQ if SMP -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y +# FIXME: investigate whether we need/want these options. +# select HAVE_IOREMAP_PROT +# select HAVE_OPTPROBES +# select HAVE_REGS_AND_STACK_ACCESS_API +# select HAVE_HW_BREAKPOINT +# select PERF_EVENTS +# select HAVE_USER_RETURN_NOTIFIER +# config NO_BOOTMEM +# config ARCH_SUPPORTS_DEBUG_PAGEALLOC +# config HUGETLB_PAGE_SIZE_VARIABLE -config GENERIC_IRQ_PROBE +config MMU def_bool y -config GENERIC_PENDING_IRQ +config GENERIC_CSUM def_bool y - depends on GENERIC_HARDIRQS && SMP config SEMAPHORE_SLEEPERS def_bool y @@ -97,26 +106,6 @@ config HVC_TILE select HVC_DRIVER def_bool y -config TILE - def_bool y - select HAVE_KVM if !TILEGX - select GENERIC_FIND_FIRST_BIT - select GENERIC_FIND_NEXT_BIT - select USE_GENERIC_SMP_HELPERS - select CC_OPTIMIZE_FOR_SIZE - -# FIXME: investigate whether we need/want these options. -# select HAVE_IOREMAP_PROT -# select HAVE_OPTPROBES -# select HAVE_REGS_AND_STACK_ACCESS_API -# select HAVE_HW_BREAKPOINT -# select PERF_EVENTS -# select HAVE_USER_RETURN_NOTIFIER -# config NO_BOOTMEM -# config ARCH_SUPPORTS_DEBUG_PAGEALLOC -# config HUGETLB_PAGE_SIZE_VARIABLE - - # Please note: TILE-Gx support is not yet finalized; this is # the preliminary support. TILE-Gx drivers are only provided # with the alpha or beta test versions for Tilera customers. @@ -220,7 +209,7 @@ config FORCE_MAX_ZONEORDER choice depends on !TILEGX - prompt "Memory split" if EMBEDDED + prompt "Memory split" if EXPERT default VMSPLIT_3G ---help--- Select the desired split between kernel and user memory. diff --git a/arch/tile/Kconfig.debug b/arch/tile/Kconfig.debug index a81f0fbf7e6..9bc161a02c7 100644 --- a/arch/tile/Kconfig.debug +++ b/arch/tile/Kconfig.debug @@ -3,7 +3,7 @@ menu "Kernel hacking" source "lib/Kconfig.debug" config EARLY_PRINTK - bool "Early printk" if EMBEDDED && DEBUG_KERNEL + bool "Early printk" if EXPERT && DEBUG_KERNEL default y help Write kernel log output directly via the hypervisor console. diff --git a/arch/tile/configs/tile_defconfig b/arch/tile/configs/tile_defconfig index 919c54afd98..0fe54445fda 100644 --- a/arch/tile/configs/tile_defconfig +++ b/arch/tile/configs/tile_defconfig @@ -3,7 +3,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="usr/contents.txt" -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y CONFIG_MODULES=y diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common index 049d048b070..e351e14b433 100644 --- a/arch/um/Kconfig.common +++ b/arch/um/Kconfig.common @@ -3,14 +3,10 @@ config DEFCONFIG_LIST option defconfig_list default "arch/$ARCH/defconfig" -# UML uses the generic IRQ subsystem -config GENERIC_HARDIRQS - bool - default y - config UML bool default y + select HAVE_GENERIC_HARDIRQS config MMU bool diff --git a/arch/um/Kconfig.um b/arch/um/Kconfig.um index f8d1d0d47fe..90a438acbfa 100644 --- a/arch/um/Kconfig.um +++ b/arch/um/Kconfig.um @@ -120,9 +120,6 @@ config SMP If you don't know what to do, say N. -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 diff --git a/arch/um/defconfig b/arch/um/defconfig index 564f3de65b4..9f7634f08cf 100644 --- a/arch/um/defconfig +++ b/arch/um/defconfig @@ -133,7 +133,7 @@ CONFIG_SYSFS_DEPRECATED=y # CONFIG_BLK_DEV_INITRD is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y -# CONFIG_EMBEDDED is not set +# CONFIG_EXPERT is not set CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 36ed2e2c896..d5ed94d30aa 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -627,11 +627,11 @@ config APB_TIMER as it is off-chip. APB timers are always running regardless of CPU C states, they are used as per CPU clockevent device when possible. -# Mark as embedded because too many people got it wrong. +# Mark as expert because too many people got it wrong. # The code disables itself when not needed. config DMI default y - bool "Enable DMI scanning" if EMBEDDED + bool "Enable DMI scanning" if EXPERT ---help--- Enabled scanning of DMI to identify machine quirks. Say Y here unless you have verified that your setup is not @@ -639,7 +639,7 @@ config DMI BIOS code. config GART_IOMMU - bool "GART IOMMU support" if EMBEDDED + bool "GART IOMMU support" if EXPERT default y select SWIOTLB depends on X86_64 && PCI && AMD_NB @@ -889,7 +889,7 @@ config X86_THERMAL_VECTOR depends on X86_MCE_INTEL config VM86 - bool "Enable VM86 support" if EMBEDDED + bool "Enable VM86 support" if EXPERT default y depends on X86_32 ---help--- @@ -1073,7 +1073,7 @@ endchoice choice depends on EXPERIMENTAL - prompt "Memory split" if EMBEDDED + prompt "Memory split" if EXPERT default VMSPLIT_3G depends on X86_32 ---help--- @@ -1135,7 +1135,7 @@ config ARCH_DMA_ADDR_T_64BIT def_bool X86_64 || HIGHMEM64G config DIRECT_GBPAGES - bool "Enable 1GB pages for kernel pagetables" if EMBEDDED + bool "Enable 1GB pages for kernel pagetables" if EXPERT default y depends on X86_64 ---help--- @@ -1369,7 +1369,7 @@ config MATH_EMULATION config MTRR def_bool y - prompt "MTRR (Memory Type Range Register) support" if EMBEDDED + prompt "MTRR (Memory Type Range Register) support" if EXPERT ---help--- On Intel P6 family processors (Pentium Pro, Pentium II and later) the Memory Type Range Registers (MTRRs) may be used to control @@ -1435,7 +1435,7 @@ config MTRR_SANITIZER_SPARE_REG_NR_DEFAULT config X86_PAT def_bool y - prompt "x86 PAT support" if EMBEDDED + prompt "x86 PAT support" if EXPERT depends on MTRR ---help--- Use PAT attributes to setup page level cache control. @@ -1539,7 +1539,7 @@ config KEXEC_JUMP code in physical address mode via KEXEC config PHYSICAL_START - hex "Physical address where the kernel is loaded" if (EMBEDDED || CRASH_DUMP) + hex "Physical address where the kernel is loaded" if (EXPERT || CRASH_DUMP) default "0x1000000" ---help--- This gives the physical address where the kernel is loaded. @@ -1934,13 +1934,19 @@ config PCI_MMCONFIG depends on X86_64 && PCI && ACPI config PCI_CNB20LE_QUIRK - bool "Read CNB20LE Host Bridge Windows" - depends on PCI + bool "Read CNB20LE Host Bridge Windows" if EXPERT + default n + depends on PCI && EXPERIMENTAL help Read the PCI windows out of the CNB20LE host bridge. This allows PCI hotplug to work on systems with the CNB20LE chipset which do not have ACPI. + There's no public spec for this chipset, and this functionality + is known to be incomplete. + + You should say N unless you know you need this. + config DMAR bool "Support for DMA Remapping Devices (EXPERIMENTAL)" depends on PCI_MSI && ACPI && EXPERIMENTAL @@ -2062,13 +2068,14 @@ config OLPC bool "One Laptop Per Child support" select GPIOLIB select OLPC_OPENFIRMWARE + depends on !X86_64 && !X86_PAE ---help--- Add support for detecting the unique features of the OLPC XO hardware. config OLPC_XO1 tristate "OLPC XO-1 support" - depends on OLPC && PCI + depends on OLPC && MFD_CS5535 ---help--- Add support for non-essential features of the OLPC XO-1 laptop. diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 15588a0ef46..283c5a6a03a 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -424,7 +424,7 @@ config X86_DEBUGCTLMSR depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486 || M386) && !UML menuconfig PROCESSOR_SELECT - bool "Supported processor vendors" if EMBEDDED + bool "Supported processor vendors" if EXPERT ---help--- This lets you choose what x86 vendor support code your kernel will include. diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index 45143bbcfe5..615e18810f4 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -31,7 +31,7 @@ config X86_VERBOSE_BOOTUP see errors. Disable this if you want silent bootup. config EARLY_PRINTK - bool "Early printk" if EMBEDDED + bool "Early printk" if EXPERT default y ---help--- Write kernel log output directly into the VGA buffer or to a serial @@ -138,7 +138,7 @@ config DEBUG_NX_TEST config DOUBLEFAULT default y - bool "Enable doublefault exception handler" if EMBEDDED + bool "Enable doublefault exception handler" if EXPERT depends on X86_32 ---help--- This option allows trapping of rare doublefault exceptions that diff --git a/arch/x86/include/asm/cacheflush.h b/arch/x86/include/asm/cacheflush.h index 63e35ec9075..62f084478f7 100644 --- a/arch/x86/include/asm/cacheflush.h +++ b/arch/x86/include/asm/cacheflush.h @@ -1,48 +1,8 @@ #ifndef _ASM_X86_CACHEFLUSH_H #define _ASM_X86_CACHEFLUSH_H -/* Keep includes the same across arches. */ -#include <linux/mm.h> - /* Caches aren't brain-dead on the intel. */ -static inline void flush_cache_all(void) { } -static inline void flush_cache_mm(struct mm_struct *mm) { } -static inline void flush_cache_dup_mm(struct mm_struct *mm) { } -static inline void flush_cache_range(struct vm_area_struct *vma, - unsigned long start, unsigned long end) { } -static inline void flush_cache_page(struct vm_area_struct *vma, - unsigned long vmaddr, unsigned long pfn) { } -#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 -static inline void flush_dcache_page(struct page *page) { } -static inline void flush_dcache_mmap_lock(struct address_space *mapping) { } -static inline void flush_dcache_mmap_unlock(struct address_space *mapping) { } -static inline void flush_icache_range(unsigned long start, - unsigned long end) { } -static inline void flush_icache_page(struct vm_area_struct *vma, - struct page *page) { } -static inline void flush_icache_user_range(struct vm_area_struct *vma, - struct page *page, - unsigned long addr, - unsigned long len) { } -static inline void flush_cache_vmap(unsigned long start, unsigned long end) { } -static inline void flush_cache_vunmap(unsigned long start, - unsigned long end) { } - -static inline void copy_to_user_page(struct vm_area_struct *vma, - struct page *page, unsigned long vaddr, - void *dst, const void *src, - unsigned long len) -{ - memcpy(dst, src, len); -} - -static inline void copy_from_user_page(struct vm_area_struct *vma, - struct page *page, unsigned long vaddr, - void *dst, const void *src, - unsigned long len) -{ - memcpy(dst, src, len); -} +#include <asm-generic/cacheflush.h> #ifdef CONFIG_X86_PAT /* diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 4fab24de26b..6e6e7558e70 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -32,5 +32,6 @@ extern void arch_unregister_cpu(int); DECLARE_PER_CPU(int, cpu_state); +int __cpuinit mwait_usable(const struct cpuinfo_x86 *); #endif /* _ASM_X86_CPU_H */ diff --git a/arch/x86/include/asm/jump_label.h b/arch/x86/include/asm/jump_label.h index f52d42e8058..574dbc22893 100644 --- a/arch/x86/include/asm/jump_label.h +++ b/arch/x86/include/asm/jump_label.h @@ -14,7 +14,7 @@ do { \ asm goto("1:" \ JUMP_LABEL_INITIAL_NOP \ - ".pushsection __jump_table, \"a\" \n\t"\ + ".pushsection __jump_table, \"aw\" \n\t"\ _ASM_PTR "1b, %l[" #label "], %c0 \n\t" \ ".popsection \n\t" \ : : "i" (key) : : label); \ diff --git a/arch/x86/include/asm/numa_32.h b/arch/x86/include/asm/numa_32.h index a37229011b5..b0ef2b449a9 100644 --- a/arch/x86/include/asm/numa_32.h +++ b/arch/x86/include/asm/numa_32.h @@ -1,6 +1,8 @@ #ifndef _ASM_X86_NUMA_32_H #define _ASM_X86_NUMA_32_H +extern int numa_off; + extern int pxm_to_nid(int pxm); extern void numa_remove_cpu(int cpu); diff --git a/arch/x86/include/asm/numa_64.h b/arch/x86/include/asm/numa_64.h index 5ae87285a50..0493be39607 100644 --- a/arch/x86/include/asm/numa_64.h +++ b/arch/x86/include/asm/numa_64.h @@ -40,6 +40,7 @@ extern void __cpuinit numa_remove_cpu(int cpu); #ifdef CONFIG_NUMA_EMU #define FAKE_NODE_MIN_SIZE ((u64)32 << 20) #define FAKE_NODE_MIN_HASH_MASK (~(FAKE_NODE_MIN_SIZE - 1UL)) +void numa_emu_cmdline(char *); #endif /* CONFIG_NUMA_EMU */ #else static inline void init_cpu_to_node(void) { } diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h index 8ee45167e81..3788f4649db 100644 --- a/arch/x86/include/asm/percpu.h +++ b/arch/x86/include/asm/percpu.h @@ -414,8 +414,6 @@ do { \ #define this_cpu_xchg_1(pcp, nval) percpu_xchg_op(pcp, nval) #define this_cpu_xchg_2(pcp, nval) percpu_xchg_op(pcp, nval) #define this_cpu_xchg_4(pcp, nval) percpu_xchg_op(pcp, nval) -#define this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) -#define this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) #define irqsafe_cpu_add_1(pcp, val) percpu_add_op((pcp), val) #define irqsafe_cpu_add_2(pcp, val) percpu_add_op((pcp), val) @@ -432,8 +430,6 @@ do { \ #define irqsafe_cpu_xchg_1(pcp, nval) percpu_xchg_op(pcp, nval) #define irqsafe_cpu_xchg_2(pcp, nval) percpu_xchg_op(pcp, nval) #define irqsafe_cpu_xchg_4(pcp, nval) percpu_xchg_op(pcp, nval) -#define irqsafe_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) -#define irqsafe_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) #ifndef CONFIG_M386 #define __this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val) @@ -475,11 +471,15 @@ do { \ #define this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) #define this_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val) #define this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val) +#define this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) +#define this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) #define irqsafe_cpu_add_8(pcp, val) percpu_add_op((pcp), val) #define irqsafe_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val) #define irqsafe_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) #define irqsafe_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val) +#define irqsafe_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) +#define irqsafe_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) #endif /* This is not atomic against other CPUs -- CPU preemption needs to be off */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 53fd1d5a1fe..45636cefa18 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -761,10 +761,11 @@ extern void select_idle_routine(const struct cpuinfo_x86 *c); extern void init_c1e_mask(void); extern unsigned long boot_option_idle_override; -extern unsigned long idle_halt; -extern unsigned long idle_nomwait; extern bool c1e_detected; +enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, + IDLE_POLL, IDLE_FORCE_MWAIT}; + extern void enable_sep_cpu(void); extern int sysenter_setup(void); diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index ec881c6bfee..b3a71137983 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -509,6 +509,7 @@ int acpi_gsi_to_irq(u32 gsi, unsigned int *irq) return 0; } +EXPORT_SYMBOL_GPL(acpi_gsi_to_irq); int acpi_isa_irq_to_gsi(unsigned isa_irq, u32 *gsi) { diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c index 7c9ab59653e..51ef31a89be 100644 --- a/arch/x86/kernel/apb_timer.c +++ b/arch/x86/kernel/apb_timer.c @@ -313,14 +313,16 @@ static void apbt_setup_irq(struct apbt_dev *adev) if (adev->irq == 0) return; + irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT); + irq_set_affinity(adev->irq, cpumask_of(adev->cpu)); + /* APB timer irqs are set up as mp_irqs, timer is edge type */ + __set_irq_handler(adev->irq, handle_edge_irq, 0, "edge"); + if (system_state == SYSTEM_BOOTING) { - irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT); - irq_set_affinity(adev->irq, cpumask_of(adev->cpu)); - /* APB timer irqs are set up as mp_irqs, timer is edge type */ - __set_irq_handler(adev->irq, handle_edge_irq, 0, "edge"); if (request_irq(adev->irq, apbt_interrupt_handler, - IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, - adev->name, adev)) { + IRQF_TIMER | IRQF_DISABLED | + IRQF_NOBALANCING, + adev->name, adev)) { printk(KERN_ERR "Failed request IRQ for APBT%d\n", adev->num); } diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 7283e98deaa..ec2c19a7b8e 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -45,6 +45,7 @@ static const struct _cache_table __cpuinitconst cache_table[] = { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */ { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */ { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */ + { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */ { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */ { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */ { 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */ @@ -66,6 +67,7 @@ static const struct _cache_table __cpuinitconst cache_table[] = { 0x45, LVL_2, MB(2) }, /* 4-way set assoc, 32 byte line size */ { 0x46, LVL_3, MB(4) }, /* 4-way set assoc, 64 byte line size */ { 0x47, LVL_3, MB(8) }, /* 8-way set assoc, 64 byte line size */ + { 0x48, LVL_2, MB(3) }, /* 12-way set assoc, 64 byte line size */ { 0x49, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */ { 0x4a, LVL_3, MB(6) }, /* 12-way set assoc, 64 byte line size */ { 0x4b, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */ @@ -87,6 +89,7 @@ static const struct _cache_table __cpuinitconst cache_table[] = { 0x7c, LVL_2, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */ { 0x7d, LVL_2, MB(2) }, /* 8-way set assoc, 64 byte line size */ { 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */ + { 0x80, LVL_2, 512 }, /* 8-way set assoc, 64 byte line size */ { 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */ { 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */ { 0x84, LVL_2, MB(1) }, /* 8-way set assoc, 32 byte line size */ diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c index e12246ff5aa..6f8c5e9da97 100644 --- a/arch/x86/kernel/cpu/mcheck/therm_throt.c +++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c @@ -59,6 +59,7 @@ struct thermal_state { /* Callback to handle core threshold interrupts */ int (*platform_thermal_notify)(__u64 msr_val); +EXPORT_SYMBOL(platform_thermal_notify); static DEFINE_PER_CPU(struct thermal_state, thermal_state); diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index d6fb146c0d8..df20723a6a1 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -234,6 +234,7 @@ unsigned __kprobes long oops_begin(void) bust_spinlocks(1); return flags; } +EXPORT_SYMBOL_GPL(oops_begin); void __kprobes oops_end(unsigned long flags, struct pt_regs *regs, int signr) { diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c index 0c2b7ef7a34..294f26da0c0 100644 --- a/arch/x86/kernel/e820.c +++ b/arch/x86/kernel/e820.c @@ -14,6 +14,7 @@ #include <linux/bootmem.h> #include <linux/pfn.h> #include <linux/suspend.h> +#include <linux/acpi.h> #include <linux/firmware-map.h> #include <linux/memblock.h> diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c index 48ff6dcffa0..9974d21048f 100644 --- a/arch/x86/kernel/irq_32.c +++ b/arch/x86/kernel/irq_32.c @@ -129,8 +129,7 @@ void __cpuinit irq_ctx_init(int cpu) irqctx = page_address(alloc_pages_node(cpu_to_node(cpu), THREAD_FLAGS, THREAD_ORDER)); - irqctx->tinfo.task = NULL; - irqctx->tinfo.exec_domain = NULL; + memset(&irqctx->tinfo, 0, sizeof(struct thread_info)); irqctx->tinfo.cpu = cpu; irqctx->tinfo.preempt_count = HARDIRQ_OFFSET; irqctx->tinfo.addr_limit = MAKE_MM_SEG(0); @@ -140,10 +139,8 @@ void __cpuinit irq_ctx_init(int cpu) irqctx = page_address(alloc_pages_node(cpu_to_node(cpu), THREAD_FLAGS, THREAD_ORDER)); - irqctx->tinfo.task = NULL; - irqctx->tinfo.exec_domain = NULL; + memset(&irqctx->tinfo, 0, sizeof(struct thread_info)); irqctx->tinfo.cpu = cpu; - irqctx->tinfo.preempt_count = 0; irqctx->tinfo.addr_limit = MAKE_MM_SEG(0); per_cpu(softirq_ctx, cpu) = irqctx; diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 09c08a1c706..e764fc05d70 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -14,6 +14,7 @@ #include <linux/utsname.h> #include <trace/events/power.h> #include <linux/hw_breakpoint.h> +#include <asm/cpu.h> #include <asm/system.h> #include <asm/apic.h> #include <asm/syscalls.h> @@ -22,11 +23,6 @@ #include <asm/i387.h> #include <asm/debugreg.h> -unsigned long idle_halt; -EXPORT_SYMBOL(idle_halt); -unsigned long idle_nomwait; -EXPORT_SYMBOL(idle_nomwait); - struct kmem_cache *task_xstate_cachep; EXPORT_SYMBOL_GPL(task_xstate_cachep); @@ -327,7 +323,7 @@ long sys_execve(const char __user *name, /* * Idle related variables and functions */ -unsigned long boot_option_idle_override = 0; +unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; EXPORT_SYMBOL(boot_option_idle_override); /* @@ -386,6 +382,8 @@ void default_idle(void) else local_irq_enable(); current_thread_info()->status |= TS_POLLING; + trace_power_end(smp_processor_id()); + trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); } else { local_irq_enable(); /* loop is done by the caller */ @@ -443,8 +441,6 @@ EXPORT_SYMBOL_GPL(cpu_idle_wait); */ void mwait_idle_with_hints(unsigned long ax, unsigned long cx) { - trace_power_start(POWER_CSTATE, (ax>>4)+1, smp_processor_id()); - trace_cpu_idle((ax>>4)+1, smp_processor_id()); if (!need_resched()) { if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLUSH_MONITOR)) clflush((void *)¤t_thread_info()->flags); @@ -471,6 +467,8 @@ static void mwait_idle(void) __sti_mwait(0, 0); else local_irq_enable(); + trace_power_end(smp_processor_id()); + trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); } else local_irq_enable(); } @@ -503,17 +501,16 @@ static void poll_idle(void) * * idle=mwait overrides this decision and forces the usage of mwait. */ -static int __cpuinitdata force_mwait; #define MWAIT_INFO 0x05 #define MWAIT_ECX_EXTENDED_INFO 0x01 #define MWAIT_EDX_C1 0xf0 -static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) +int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) { u32 eax, ebx, ecx, edx; - if (force_mwait) + if (boot_option_idle_override == IDLE_FORCE_MWAIT) return 1; if (c->cpuid_level < MWAIT_INFO) @@ -633,9 +630,10 @@ static int __init idle_setup(char *str) if (!strcmp(str, "poll")) { printk("using polling idle threads.\n"); pm_idle = poll_idle; - } else if (!strcmp(str, "mwait")) - force_mwait = 1; - else if (!strcmp(str, "halt")) { + boot_option_idle_override = IDLE_POLL; + } else if (!strcmp(str, "mwait")) { + boot_option_idle_override = IDLE_FORCE_MWAIT; + } else if (!strcmp(str, "halt")) { /* * When the boot option of idle=halt is added, halt is * forced to be used for CPU idle. In such case CPU C2/C3 @@ -644,8 +642,7 @@ static int __init idle_setup(char *str) * the boot_option_idle_override. */ pm_idle = default_idle; - idle_halt = 1; - return 0; + boot_option_idle_override = IDLE_HALT; } else if (!strcmp(str, "nomwait")) { /* * If the boot option of "idle=nomwait" is added, @@ -653,12 +650,10 @@ static int __init idle_setup(char *str) * states. In such case it won't touch the variable * of boot_option_idle_override. */ - idle_nomwait = 1; - return 0; + boot_option_idle_override = IDLE_NOMWAIT; } else return -1; - boot_option_idle_override = 1; return 0; } early_param("idle", idle_setup); diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c index 4b9befa0e34..8d128783af4 100644 --- a/arch/x86/kernel/process_32.c +++ b/arch/x86/kernel/process_32.c @@ -57,8 +57,6 @@ #include <asm/syscalls.h> #include <asm/debugreg.h> -#include <trace/events/power.h> - asmlinkage void ret_from_fork(void) __asm__("ret_from_fork"); /* @@ -113,8 +111,6 @@ void cpu_idle(void) stop_critical_timings(); pm_idle(); start_critical_timings(); - trace_power_end(smp_processor_id()); - trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); } tick_nohz_restart_sched_tick(); preempt_enable_no_resched(); diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 4c818a73839..bd387e8f73b 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -51,8 +51,6 @@ #include <asm/syscalls.h> #include <asm/debugreg.h> -#include <trace/events/power.h> - asmlinkage extern void ret_from_fork(void); DEFINE_PER_CPU(unsigned long, old_rsp); @@ -141,10 +139,6 @@ void cpu_idle(void) pm_idle(); start_critical_timings(); - trace_power_end(smp_processor_id()); - trace_cpu_idle(PWR_EVENT_EXIT, - smp_processor_id()); - /* In many cases the interrupt that ended idle has already called exit_idle. But some idle loops can be woken up without interrupt. */ diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 763df77343d..0cbe8c0b35e 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1402,8 +1402,9 @@ static inline void mwait_play_dead(void) unsigned int highest_subcstate = 0; int i; void *mwait_ptr; + struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); - if (!cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_MWAIT)) + if (!(cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c))) return; if (!cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLSH)) return; diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 823f79a17ad..ffe5755caa8 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -464,7 +464,7 @@ unsigned long native_calibrate_tsc(void) tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); /* hpet or pmtimer available ? */ - if (!hpet && !ref1 && !ref2) + if (ref1 == ref2) continue; /* Check, whether the sampling was disturbed by an SMI */ @@ -935,7 +935,7 @@ static void tsc_refine_calibration_work(struct work_struct *work) tsc_stop = tsc_read_refs(&ref_stop, hpet); /* hpet or pmtimer available ? */ - if (!hpet && !ref_start && !ref_stop) + if (ref_start == ref_stop) goto out; /* Check, whether the sampling was disturbed by an SMI */ diff --git a/arch/x86/lguest/Kconfig b/arch/x86/lguest/Kconfig index 38718041efc..6e121a2a49e 100644 --- a/arch/x86/lguest/Kconfig +++ b/arch/x86/lguest/Kconfig @@ -2,6 +2,7 @@ config LGUEST_GUEST bool "Lguest guest support" select PARAVIRT depends on X86_32 + select VIRTUALIZATION select VIRTIO select VIRTIO_RING select VIRTIO_CONSOLE diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c index 4996cf5f73a..eba687f0cc0 100644 --- a/arch/x86/lguest/boot.c +++ b/arch/x86/lguest/boot.c @@ -824,7 +824,7 @@ static void __init lguest_init_IRQ(void) for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) { /* Some systems map "vectors" to interrupts weirdly. Not us! */ - __get_cpu_var(vector_irq)[i] = i - FIRST_EXTERNAL_VECTOR; + __this_cpu_write(vector_irq[i], i - FIRST_EXTERNAL_VECTOR); if (i != SYSCALL_VECTOR) set_intr_gate(i, interrupt[i - FIRST_EXTERNAL_VECTOR]); } diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c index 787c52ca49c..ebf6d7887a3 100644 --- a/arch/x86/mm/numa.c +++ b/arch/x86/mm/numa.c @@ -2,6 +2,28 @@ #include <linux/topology.h> #include <linux/module.h> #include <linux/bootmem.h> +#include <asm/numa.h> +#include <asm/acpi.h> + +int __initdata numa_off; + +static __init int numa_setup(char *opt) +{ + if (!opt) + return -EINVAL; + if (!strncmp(opt, "off", 3)) + numa_off = 1; +#ifdef CONFIG_NUMA_EMU + if (!strncmp(opt, "fake=", 5)) + numa_emu_cmdline(opt + 5); +#endif +#ifdef CONFIG_ACPI_NUMA + if (!strncmp(opt, "noacpi", 6)) + acpi_numa = -1; +#endif + return 0; +} +early_param("numa", numa_setup); /* * Which logical CPUs are on which nodes diff --git a/arch/x86/mm/numa_64.c b/arch/x86/mm/numa_64.c index 1e72102e80c..95ea1551eeb 100644 --- a/arch/x86/mm/numa_64.c +++ b/arch/x86/mm/numa_64.c @@ -30,7 +30,6 @@ s16 apicid_to_node[MAX_LOCAL_APIC] __cpuinitdata = { [0 ... MAX_LOCAL_APIC-1] = NUMA_NO_NODE }; -int numa_off __initdata; static unsigned long __initdata nodemap_addr; static unsigned long __initdata nodemap_size; @@ -263,6 +262,11 @@ static struct bootnode nodes[MAX_NUMNODES] __initdata; static struct bootnode physnodes[MAX_NUMNODES] __cpuinitdata; static char *cmdline __initdata; +void __init numa_emu_cmdline(char *str) +{ + cmdline = str; +} + static int __init setup_physnodes(unsigned long start, unsigned long end, int acpi, int amd) { @@ -670,24 +674,6 @@ unsigned long __init numa_free_all_bootmem(void) return pages; } -static __init int numa_setup(char *opt) -{ - if (!opt) - return -EINVAL; - if (!strncmp(opt, "off", 3)) - numa_off = 1; -#ifdef CONFIG_NUMA_EMU - if (!strncmp(opt, "fake=", 5)) - cmdline = opt + 5; -#endif -#ifdef CONFIG_ACPI_NUMA - if (!strncmp(opt, "noacpi", 6)) - acpi_numa = -1; -#endif - return 0; -} -early_param("numa", numa_setup); - #ifdef CONFIG_NUMA static __init int find_near_online_node(int node) diff --git a/arch/x86/mm/srat_32.c b/arch/x86/mm/srat_32.c index f16434568a5..ae96e7b8051 100644 --- a/arch/x86/mm/srat_32.c +++ b/arch/x86/mm/srat_32.c @@ -59,7 +59,6 @@ static struct node_memory_chunk_s __initdata node_memory_chunk[MAXCHUNKS]; static int __initdata num_memory_chunks; /* total number of memory chunks */ static u8 __initdata apicid_to_pxm[MAX_APICID]; -int numa_off __initdata; int acpi_numa __initdata; static __init void bad_srat(void) diff --git a/arch/x86/pci/broadcom_bus.c b/arch/x86/pci/broadcom_bus.c index 0846a5bbbfb..ab8269b0da2 100644 --- a/arch/x86/pci/broadcom_bus.c +++ b/arch/x86/pci/broadcom_bus.c @@ -9,6 +9,7 @@ * option) any later version. */ +#include <linux/acpi.h> #include <linux/delay.h> #include <linux/dmi.h> #include <linux/pci.h> @@ -25,12 +26,14 @@ static void __devinit cnb20le_res(struct pci_dev *dev) u8 fbus, lbus; int i; +#ifdef CONFIG_ACPI /* - * The x86_pci_root_bus_res_quirks() function already refuses to use - * this information if ACPI _CRS was used. Therefore, we don't bother - * checking if ACPI is enabled, and just generate the information - * for both the ACPI _CRS and no ACPI cases. + * We should get host bridge information from ACPI unless the BIOS + * doesn't support it. */ + if (acpi_os_get_root_pointer()) + return; +#endif info = &pci_root_info[pci_root_num]; pci_root_num++; diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index f7c8a399978..5fe75026ecc 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -22,6 +22,7 @@ unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 | unsigned int pci_early_dump_regs; static int pci_bf_sort; +static int smbios_type_b1_flag; int pci_routeirq; int noioapicquirk; #ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS @@ -185,6 +186,39 @@ static int __devinit set_bf_sort(const struct dmi_system_id *d) return 0; } +static void __devinit read_dmi_type_b1(const struct dmi_header *dm, + void *private_data) +{ + u8 *d = (u8 *)dm + 4; + + if (dm->type != 0xB1) + return; + switch (((*(u32 *)d) >> 9) & 0x03) { + case 0x00: + printk(KERN_INFO "dmi type 0xB1 record - unknown flag\n"); + break; + case 0x01: /* set pci=bfsort */ + smbios_type_b1_flag = 1; + break; + case 0x02: /* do not set pci=bfsort */ + smbios_type_b1_flag = 2; + break; + default: + break; + } +} + +static int __devinit find_sort_method(const struct dmi_system_id *d) +{ + dmi_walk(read_dmi_type_b1, NULL); + + if (smbios_type_b1_flag == 1) { + set_bf_sort(d); + return 0; + } + return -1; +} + /* * Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus) */ @@ -213,6 +247,13 @@ static const struct dmi_system_id __devinitconst pciprobe_dmi_table[] = { }, #endif /* __i386__ */ { + .callback = find_sort_method, + .ident = "Dell System", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"), + }, + }, + { .callback = set_bf_sort, .ident = "Dell PowerEdge 1950", .matches = { diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c index 9f9bfb705cf..87e6c832311 100644 --- a/arch/x86/pci/irq.c +++ b/arch/x86/pci/irq.c @@ -589,7 +589,8 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route case PCI_DEVICE_ID_INTEL_ICH10_1: case PCI_DEVICE_ID_INTEL_ICH10_2: case PCI_DEVICE_ID_INTEL_ICH10_3: - case PCI_DEVICE_ID_INTEL_PATSBURG_LPC: + case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0: + case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1: r->name = "PIIX/ICH"; r->get = pirq_piix_get; r->set = pirq_piix_set; diff --git a/arch/x86/platform/olpc/olpc-xo1.c b/arch/x86/platform/olpc/olpc-xo1.c index f5442c03abc..127775696d6 100644 --- a/arch/x86/platform/olpc/olpc-xo1.c +++ b/arch/x86/platform/olpc/olpc-xo1.c @@ -1,6 +1,7 @@ /* * Support for features of the OLPC XO-1 laptop * + * Copyright (C) 2010 Andres Salomon <dilinger@queued.net> * Copyright (C) 2010 One Laptop per Child * Copyright (C) 2006 Red Hat, Inc. * Copyright (C) 2006 Advanced Micro Devices, Inc. @@ -12,8 +13,6 @@ */ #include <linux/module.h> -#include <linux/pci.h> -#include <linux/pci_ids.h> #include <linux/platform_device.h> #include <linux/pm.h> @@ -22,9 +21,6 @@ #define DRV_NAME "olpc-xo1" -#define PMS_BAR 4 -#define ACPI_BAR 5 - /* PMC registers (PMS block) */ #define PM_SCLK 0x10 #define PM_IN_SLPCTL 0x20 @@ -57,65 +53,67 @@ static void xo1_power_off(void) outl(0x00002000, acpi_base + PM1_CNT); } -/* Read the base addresses from the PCI BAR info */ -static int __devinit setup_bases(struct pci_dev *pdev) +static int __devinit olpc_xo1_probe(struct platform_device *pdev) { - int r; + struct resource *res; - r = pci_enable_device_io(pdev); - if (r) { - dev_err(&pdev->dev, "can't enable device IO\n"); - return r; - } + /* don't run on non-XOs */ + if (!machine_is_olpc()) + return -ENODEV; - r = pci_request_region(pdev, ACPI_BAR, DRV_NAME); - if (r) { - dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", ACPI_BAR); - return r; + res = platform_get_resource(pdev, IORESOURCE_IO, 0); + if (!res) { + dev_err(&pdev->dev, "can't fetch device resource info\n"); + return -EIO; } - r = pci_request_region(pdev, PMS_BAR, DRV_NAME); - if (r) { - dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", PMS_BAR); - pci_release_region(pdev, ACPI_BAR); - return r; + if (!request_region(res->start, resource_size(res), DRV_NAME)) { + dev_err(&pdev->dev, "can't request region\n"); + return -EIO; } - acpi_base = pci_resource_start(pdev, ACPI_BAR); - pms_base = pci_resource_start(pdev, PMS_BAR); + if (strcmp(pdev->name, "cs5535-pms") == 0) + pms_base = res->start; + else if (strcmp(pdev->name, "cs5535-acpi") == 0) + acpi_base = res->start; + + /* If we have both addresses, we can override the poweroff hook */ + if (pms_base && acpi_base) { + pm_power_off = xo1_power_off; + printk(KERN_INFO "OLPC XO-1 support registered\n"); + } return 0; } -static int __devinit olpc_xo1_probe(struct platform_device *pdev) +static int __devexit olpc_xo1_remove(struct platform_device *pdev) { - struct pci_dev *pcidev; - int r; - - pcidev = pci_get_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, - NULL); - if (!pdev) - return -ENODEV; - - r = setup_bases(pcidev); - if (r) - return r; + struct resource *r; - pm_power_off = xo1_power_off; + r = platform_get_resource(pdev, IORESOURCE_IO, 0); + release_region(r->start, resource_size(r)); - printk(KERN_INFO "OLPC XO-1 support registered\n"); - return 0; -} + if (strcmp(pdev->name, "cs5535-pms") == 0) + pms_base = 0; + else if (strcmp(pdev->name, "cs5535-acpi") == 0) + acpi_base = 0; -static int __devexit olpc_xo1_remove(struct platform_device *pdev) -{ pm_power_off = NULL; return 0; } -static struct platform_driver olpc_xo1_driver = { +static struct platform_driver cs5535_pms_drv = { + .driver = { + .name = "cs5535-pms", + .owner = THIS_MODULE, + }, + .probe = olpc_xo1_probe, + .remove = __devexit_p(olpc_xo1_remove), +}; + +static struct platform_driver cs5535_acpi_drv = { .driver = { - .name = DRV_NAME, + .name = "cs5535-acpi", .owner = THIS_MODULE, }, .probe = olpc_xo1_probe, @@ -124,12 +122,23 @@ static struct platform_driver olpc_xo1_driver = { static int __init olpc_xo1_init(void) { - return platform_driver_register(&olpc_xo1_driver); + int r; + + r = platform_driver_register(&cs5535_pms_drv); + if (r) + return r; + + r = platform_driver_register(&cs5535_acpi_drv); + if (r) + platform_driver_unregister(&cs5535_pms_drv); + + return r; } static void __exit olpc_xo1_exit(void) { - platform_driver_unregister(&olpc_xo1_driver); + platform_driver_unregister(&cs5535_acpi_drv); + platform_driver_unregister(&cs5535_pms_drv); } MODULE_AUTHOR("Daniel Drake <dsd@laptop.org>"); diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index 7e8d3bc80af..50542efe45f 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -1194,7 +1194,7 @@ asmlinkage void __init xen_start_kernel(void) per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0]; local_irq_disable(); - early_boot_irqs_off(); + early_boot_irqs_disabled = true; memblock_init(); diff --git a/arch/x86/xen/irq.c b/arch/x86/xen/irq.c index 9d30105a0c4..6a6fe893964 100644 --- a/arch/x86/xen/irq.c +++ b/arch/x86/xen/irq.c @@ -126,7 +126,7 @@ static const struct pv_irq_ops xen_irq_ops __initdata = { #endif }; -void __init xen_init_irq_ops() +void __init xen_init_irq_ops(void) { pv_irq_ops = xen_irq_ops; x86_init.irqs.intr_init = xen_init_IRQ; diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c index 7575e55cd52..5e92b61ad57 100644 --- a/arch/x86/xen/mmu.c +++ b/arch/x86/xen/mmu.c @@ -201,6 +201,7 @@ xmaddr_t arbitrary_virt_to_machine(void *vaddr) offset = address & ~PAGE_MASK; return XMADDR(((phys_addr_t)pte_mfn(*pte) << PAGE_SHIFT) + offset); } +EXPORT_SYMBOL_GPL(arbitrary_virt_to_machine); void make_lowmem_page_readonly(void *vaddr) { diff --git a/arch/x86/xen/p2m.c b/arch/x86/xen/p2m.c index 8f2251d2a3f..ddc81a06edb 100644 --- a/arch/x86/xen/p2m.c +++ b/arch/x86/xen/p2m.c @@ -237,7 +237,25 @@ void __init xen_build_dynamic_phys_to_machine(void) p2m_top[topidx] = mid; } - p2m_top[topidx][mididx] = &mfn_list[pfn]; + /* + * As long as the mfn_list has enough entries to completely + * fill a p2m page, pointing into the array is ok. But if + * not the entries beyond the last pfn will be undefined. + * And guessing that the 'what-ever-there-is' does not take it + * too kindly when changing it to invalid markers, a new page + * is allocated, initialized and filled with the valid part. + */ + if (unlikely(pfn + P2M_PER_PAGE > max_pfn)) { + unsigned long p2midx; + unsigned long *p2m = extend_brk(PAGE_SIZE, PAGE_SIZE); + p2m_init(p2m); + + for (p2midx = 0; pfn + p2midx < max_pfn; p2midx++) { + p2m[p2midx] = mfn_list[pfn + p2midx]; + } + p2m_top[topidx][mididx] = p2m; + } else + p2m_top[topidx][mididx] = &mfn_list[pfn]; } m2p_override_init(); diff --git a/arch/xtensa/configs/common_defconfig b/arch/xtensa/configs/common_defconfig index 1d230ee081b..b90038e40dd 100644 --- a/arch/xtensa/configs/common_defconfig +++ b/arch/xtensa/configs/common_defconfig @@ -32,7 +32,7 @@ CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set -# CONFIG_EMBEDDED is not set +# CONFIG_EXPERT is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set diff --git a/arch/xtensa/configs/iss_defconfig b/arch/xtensa/configs/iss_defconfig index 7368164843b..0234cd198c5 100644 --- a/arch/xtensa/configs/iss_defconfig +++ b/arch/xtensa/configs/iss_defconfig @@ -55,7 +55,7 @@ CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set diff --git a/arch/xtensa/configs/s6105_defconfig b/arch/xtensa/configs/s6105_defconfig index bb84fbc9921..095cd808416 100644 --- a/arch/xtensa/configs/s6105_defconfig +++ b/arch/xtensa/configs/s6105_defconfig @@ -55,7 +55,7 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y +CONFIG_EXPERT=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set |