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Throughout Linux code big LITTLE is written as "bL". We have used "bl" instead
of "bL". Lets fix it.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reported-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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This is already done by: cpufreq_frequency_table_cpuinfo()
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Some platforms might read frequency table from cluster nodes in DT, as they
might not have specific hardware for that. For them, this patch adds a generic
big LITTLE cpufreq driver.
Freqs passed from DT must be in KHz and DT node should be like:
cluster0: cluster@0 {
reg = <0>;
freqs = <500000 600000 700000 800000>;
}
cluster1: cluster@1 {
reg = <1>;
freqs = <900000 1000000 1100000 1200000>;
}
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Currently, we need to add entry for any new platform using this driver in
compatible list of arm_big_little.c driver. Which is not good.
Lets make this driver independent of slave drivers. Now, slave drivers would be
calling register routine of arm_big_little.c driver and would pass ops as
parameter.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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This adds pr_debugs at various places in driver to understand its behavior
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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We already have clock framework support for vexpress spc controller. So, no
longer need to call spc specific routines from arm_big_little driver.
Finally this driver is generic now, with zero dependency on vexpress.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Every platform have different way to get available frequencies from boot
loaders. Vexpress platform gets this information from SPC controller.
This patch separates out platform specific part for getting cpufreq table from
arm big LITTLE cpufreq driver. Every platform can pass this information from
their own stubs to this driver.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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This driver shouldn't have any dependency on Vexpress Platform and so can be
converted into generic big LITTLE platform's cpufreq driver. All dependencies
which are currently there would be removed by other patches.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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cpu_topology symbol is needed if we build vexpress_bL_cpufreq
as an module
Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
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__cpufreq_driver_target() already validates the requested frequency
against the min and max bounds specified in the policy, so there is
to need to check it again.
This patch removes the bounds check from
vexpress_cpufreq_set_target().
Signed-off-by: Dave Martin <dave.martin@linaro.org>
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Signed-off-by: Dave Martin <dave.martin@linaro.org>
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As the SPC driver now take frequency as the input parameter for get/set
performance routines, change the cpufreq driver to reflect the same.
With this change Linux no longer rely on DT for freq -> perf index
mapping.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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The maximum size of a cpu_freq driver is CPUFREQ_NAME_LEN (16)
and the previous name was longer than this, leading to incorrect
output with:
$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_driver
Reported-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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The cpufreq driver requires SPC hardware, so check for its presence
before initialising the driver. This enables the cpufreq driver to
safely exist in kernels run on hardware without SPC support.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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If there are no CPU frequencies in the device tree for the current
cluster, then vexpress_cpufreq_of_init() passes a null pointer to
cpufreq_frequency_table_cpuinfo(), which it then dereferences.
This patch tests for this situation and cleanly returns and error
instead.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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This patch adds support for CPU frequency scaling on ARM vexpress based
big.LITTLE platforms. The driver reads the frequencies from the device tree.
This driver depends on Serial Power Controller(SPC) for setting operating
performance points(OPPs). Ensure that SPC driver is built to avoid run-time
errors.
To support big.LITTLE topology, the frequencies are read from FDT and
registered seperately per-cluster. To achieve this the CPU topology is
used to set the affected/related CPUs in terms of their OPP dependencies.
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
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This patch enables ARCH_HAS_CPUFREQ for Versatile Express platforms in order
to support CPU frequency scaling.
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
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clk-spc depends on spc and when spc is not present in DT (ex: on fast models),
we must not register clk-spc.
Signed-off-by: Mark Hambleton <mark.hambleton@broadcom.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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This patch adds spc clock controller. In Vexpress cpu cluster clock is controlled via
spc controller and so it must be present in clk framework.
vexpress_clk_[of_]register_spc() registers cluster clocks with and without DT.
These are added as root clocks without any parents and their names are
"cluster[0|1|..]".
Now, platform must add clocks of all the cpus below these clusters. cpufreq
driver would get cpu clock and will do clk_get[set]_rate() on cpu clock, which
will then pass it to cluster clocks. And finally spc will get programmed.
This patch doesn't add non-DT clocks for clusters and cpus as i don't see a user
of that for now.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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To deal with the I-cache discrepancy between Cortex-A15 and Cortex-A7,
let's assume aliasing I-cache in both cases.
Note: this might need to be refined i.e. detect a big.LITTLE system
somehow by probing all CPUs not only the boot one.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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The cpuidle code requires SPC hardware, so check for its presence
before initialising. This enables the cpuidle code to safely exist
in kernels run on hardware without SPC support.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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TC2 test-chip integrates power management circuitry and firmware that
allows to remove voltage from both (A7 and A15) clusters when they are
idle or more generically when the system is forced into shutdown mode.
All CPUs in a cluster share the same voltage source so they cannot be
shutdown independently. In order to take advantage of TC2 power
management capabilities this patch implements a multi-cluster aware
CPU idle implementation. It is based on coupled C-state concept provided
by this code:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-April/097084.html
CPUs that are part of the same cluster are coupled using the mask
provided by the MPIDR at boot. Once all CPUs hit the coupled barrier the
primary CPU in the cluster (the one with MPIDR[7:0] == 0) waits for
secondaries to clean their L1 and enter wfi. Then it cleans all cache
levels, exits cluster coherency and starts the procedure to shutdown the
respective cluster. All wake-up IRQ sources are enabled by default.
Deep shutdown states for clusters are not enabled by default.
To enabled them:
A15 cluster
echo 0 > /sys/kernel/debug/idle_debug/enable_idle
A7 cluster
echo 1 > /sys/kernel/debug/idle_debug/enable_idle
Tested thoroughly using lookbusy to modulate system load and trigger idle
states entry/exit.
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The patch "ARM: kernel: fix MPIDR cpu_{suspend}/{resume} usage"
uses the BFC assembler instruction but this isn't available
on ARMv6 CPUs, which breaks compilation when building kernels which
support both SMP and ARMv6, e.g. omap2plus_defconifg.
Fix this by using a BIC instruction instead.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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The current version of cpu_{suspend}/{resume} relies on the 8 LSBs of
the MPIDR register to index the context pointer saved and restored on
CPU shutdown. This approach breaks as soon as platforms with populated
MPIDR affinity levels 1 and 2 are deployed, since the MPIDR cannot be
considered a linear index anymore.
There are multiple solutions to this problem, each with pros and cons.
This patch changes cpu_{suspend}/{resume} so that the CPU logical id
is used to retrieve an index into the context pointers array.
Performance is impacted on both save and restore paths. On save path
the CPU logical id has to be retrieved from thread_info; since caches
are on, the performance hit should be neglectable. In the resume code
path the MMU is off and so are the caches. The patch adds a trivial for
loop that polls the cpu_logical_map array scanning the present MPIDRs and
retrieves the actual CPU logical index. Since everything runs out of
strongly ordered memory the perfomance hit in the resume code path must
be measured and thought over; it worsens as the number of CPUs increases
since it is a linear search (but can be improved).
On the up side, the logical index approach is by far the easiest solution in
terms of coding and make dynamic changes to the cpu mapping trivial at
run-time.
Any change to the cpu_logical_map (ie in-kernel switcher) at run time must be
cleaned from the caches since this data has to be retrieved with the MMU
off, when caches are not searched.
Tested on TC2 and fast models.
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Move the private set_auxcr/get_auxcr functions from
drivers/cpuidle/cpuidle-calxeda.c so they can be used across platforms.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
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This patch adds the 'psci' kernel command line option. Secure firmware cannot
yet add a psci device node in the dt to indicate whether it supports psci or
not. So in the current dt, the psci device node is present by default. The
probe function will always indicate that the secure firmware implements psci
irrespective of the address space linux runs in as the same device tree will
be used in either case. Hence a kernel cmdline option is required to choose
either the native or psci power api backend depending upon the address space
linux is running in.
Specifying 'psci=enable' in the cmdline will allow Linux running in the
non-secure address space to use the same dt but use the psci backend instead
of the native backend. It effectively overrides the presence of the native
implementation by ensuring registration of the psci backend. Linux running in
the secure address space will use the native backend for power management when
'psci=disable' in the cmdline (also the default value i.e. psci backend is
disabled by default) or the psci node in the dt is absent.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
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This patch adds a probe function to check if the secure firmware has an
implementation of the Power State Coordination Interface.
'bL_platform_power_ops' will be implemented by:
a. a native backend when Linux runs in secure world
b. a psci backend which relies on the secure firmware to implement the
power ops
presence of b. will be indicated by the psci device node in the device tree.
The device node is expected to be populated by the secure firmware if it
supports psci. If the native backend detects a psci node then it bails out
allowing the psci backend to be registered.
Also a dummy 'psci_probe' function is added for the case when psci support
is not included. This prevents the build from breaking for tc2 and the
rtsm platforms.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
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This patch adds a possible error code of the cpu_on psci api. It
indicates that the cpu specified in the cpu_on call is up and running
(e.g. the firmware still has not seen the preceding cpu_off call).
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
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This patch defines constants to allow callers of the psci 'suspend'
& 'off' calls specify supported affinity levels.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
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SPC controller driver has already populated frequency table from firmware and
not its time to share it with other frameworks like: cpufreq. This patch
provides interface to get freq table from spc driver.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Not only the pointed data, but the pointer as well has to be flushed
out of the cache.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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vexpress_spc_check_loaded()
Even if it is initialized via early_INITCALL(), there are other pieces
of code that also have to be initialized with early_initcall() and
the relative call ordering may not always be satisfied.
So try to initialize the SPC code when vexpress_spc_check_loaded() is
called if that has not been done yet.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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Both SPC OPP and COMMS request takes ~3-5ms at max with CPU
wakeup enabled. The OPP change takes ~900us and COMMS ~200us if
wakeup are disabled. Since all the operations are serialised in the
firmware and CA7 wakeup takes ~2ms max, this could affect other SPC
request when they occur at the same time.
Further an SPC request could start just before jiffie is about to be
updated. In order to handle any of these cases, this patch changes
timeout value to 20ms.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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The latest firmware has the following protocol for PWC_STATUS update
to communicate status/faults:
CA15 DVFS request: 0x0001 complete, 0x0002 error
CA7 DVFS request: 0x0010 complete, 0x0020 error
SPC_SYS_CFG request: 0x0100 complete, 0x0200 error
This patch updates the driver to handle the error conditions based on
the above protocol.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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This patch changes the input parameter of spc_get/spc_set_perf
routines to frequency instead of performance index as expected
by the firmware. The SPC driver now has the list of frequencies
supported by the firmware, so it can map the requested frequency
to the right performance index.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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This patch adds support to read the SPC virtual registers that store
the OPPs through SYS_CFG interface. This helps in avoiding to rely on
DT for frequency to performanace index as expected by firmware.
It can also be used to get other information from the firware.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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In order to compare the given cluster id with A15, the A15_CONF is read
everytime. Instead read the A15 cluster id once during initialisation
and store the same for all future references.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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The SCC/SPC offsets defined in spc driver are scattered a bit.
Just reordering them for better readability.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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This patch initializes the SPC driver before smp initialization is done.
The driver is required to be able to use the power api to bring up
secondary cpus. Hence its availability is mandatory at this stage.
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This patch ensures that the SPC registers written by the power api
are read back to ensure that the changes have reflected. This is
done to workaround any delays caused by the slow nature of the SPC
interface e.g. the wfi signal being asserted to the SPC before the
changes to the SPC registers have taken effect.
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Otherwise any concurrent call could reset the completion block
while it is being waited for by a previous call.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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Picked wholesale in the IKS tree from ARM.
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Non-local variables used by the CCI and SPC management functions
called by tc2_pm_power_down() after disabling the cache must be
flushed out to main memory in advance, otherwise incoherency of
those values may occur if they are sitting in the cache of some
other CPU when tc2_pm_power_down() executes.
This patch adds the appropriate flushing to the CCI and SPC drivers
to ensure that the relevant data is available in RAM ahead of time.
Because this creates a dependency on arch-specific cacheflushing
functions, this patch also makes ARM_CCI and ARM_SPC depend on ARM
(pending a proper tidyup of those drivers).
Signed-off-by: Dave Martin <dave.martin@linaro.org>
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To enable drivers which use SPC functions to safely exist in kernels
which are run on hardware without SPC hardware, they need a method of
detecting its presence. The new function vexpress_spc_check_loaded()
provides this.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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The TC2 core tile integrates a logic block that provides the interface
between the dual cluster test-chip and the M3 microcontroller that carries
out power management. The logic block, called SPC, contains several
memory mapped registers to control among other things low-power states,
operating points and reset control.
This patch provides a driver that enables run-time control of features
implemented by the SPC control logic.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
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This patch provides the new kernel infrastructure needed by versatile
express boards. Drivers are moved to drivers/misc/vexpress directory,
where Kconfig and Makefile are created. A coalesced include file is
created to cater for all versatile express required function declarations.
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This static function generates a build warning as it's unused.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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CCI400 has a set of counters that can be used to profile different
transations at CCI master and slave interfaces. These counters can
observe different kinds of transations passing through the CCI and
provide a system-level view of activity.
This patch adds support for CCI PMU by extending the existing CCI
driver.
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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