Age | Commit message (Collapse) | Author |
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Using late_initcall is too late for IKS.
Requested-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Conflicts:
arch/arm/mach-vexpress/Kconfig
arch/arm/mach-vexpress/Makefile
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Conflicts:
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Add a new 'smp_init' hook to machine_desc so platforms can specify a
function to be used to setup smp ops instead of having a statically
defined value. The hook must return true when smp_ops are initialized.
If false the static mdesc->smp_ops will be used by default.
Add the definition of "bool" by including the linux/types.h file to
asm/mach/arch.h and make it self-contained.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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The BIG_LITTLE config option is independent from the MCPM one.
Semantically, they cover different things. MCPM can be used on non
b.L systems for example.
Signed-of-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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The functions in mcpm_entry.c are mostly intended for use during
scary cache and coherency disabling sequences, or do other things
which confuse trace ... like powering a CPU down and not
returning. Similarly for the backend code.
For simplicity, this patch just makes whole files notrace.
There should be more than enough traceable points on the paths to
these functions, but we can be more fine-grained later if there is
a need for it.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
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mcpm-merge-nico
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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This patch adds a psci device node to allow the ospm subsystems on the
TC2 to work with a psci backend implemented in the secure firmware. The
function offsets start from 1 instead of 0 as thats whats the current
secure firmware implements.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
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This patch introduces a shim layer for the TC2 platform which converts
'bL_platform_power_ops' routines to their psci counterparts. The psci
counterparts are implemented by the secure firmware. The shim layer
is used only when Linux is running in non-secure world and the secure
firmware implements psci.
It also introduces the use of a reference count to allow a power up call
to go ahead of a power down call.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
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This patch allows the vexpress 'tc2' native backend to probe
the dt for presence of the psci backend. If present then the native
implementation of the 'bL_platform_power_ops' is not used.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
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This patch adds constants in a tc2 specific header file to prevent
use of hard coded values for specifying the number of cpus and
clusters.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
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On TC2, all CPUs in a cluster are woken up when an IRQ event triggers for a
CPU in a cluster in shutdown state.
This patch puts spuriously woken CPUs back in reset by checking the
pending IRQ status in the SPC wake-up interrupt status register; if the
CPU has no pending IRQ routed to it, the core reexecutes wfi and it is put
in reset by FW straight away.
Tested-by: Viresh Kumar <viresh.kumar2@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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The low-level layer is now called "mcpm".
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Change the init code for cpuidle-tc2 to check for a
compatible node in the devicetree of "arm,generic"
in preparation for moving it to driver/cpuidle.
Rename functions / variable from tc2_ to bl_.
Signed-off-by: mark hambleton <mahamble@broadcom.com>
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Use the bL_cpu_suspend method instead of bL_cpu_power_down.
This allows for the driver to become usable on non SPC based platform
such as RTSM if vexpress_spc_check_loaded() is removed.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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The functions in mcpm_entry.c are mostly intended for use during
scary cache and coherency disabling sequences, or do other things
which confuse trace ... like powering a CPU down and not
returning. Similarly for the backend code.
For simplicity, this patch just makes whole files notrace.
There should be more than enough traceable points on the paths to
these functions, but we can be more fine-grained later if there is
a need for it.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
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This is simplistic for the moment as the expected residency is used to
prevent the shutting down of L2 and the cluster if the residency for
the last man is lower than 5 ms. To make this right, the residency
end time for each CPU would need to be recorded and taken into account.
On a suspend, the firmware mailbox address has to be set prior entering
low power mode.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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On TC2 testchip the GIC CPU IF must be disabled before powering down a
core since a pending IRQ might cause wfi completion and the processor
would exit wfi state while power controller is taking action to reset or
power up the CPU upon IRQ reception.
This patch adds code that disables the GIC CPU IF in TC2 specific
power API methods.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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This should be queued right before 'Revert "ARM: common: add GIC bybass disable
on GIC CPU IF save function"'.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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Signed-off-by: Nicolas Pitre <nico@linaro.org>
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The functions in mcpm_entry.c are mostly intended for use during
scary cache and coherency disabling sequences, or do other things
which confuse trace ... like powering a CPU down and not
returning. Similarly for the backend code.
For simplicity, this patch just makes whole files notrace.
There should be more than enough traceable points on the paths to
these functions, but we can be more fine-grained later if there is
a need for it.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
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This patch allows the vexpress 'rtsm' native backend to probe
the dt for presence of the psci backend. If present then the native
implementation of the 'bL_platform_power_ops' is not used.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Add the required code to properly handle race free platform coherency exit
to the DCSCB power down method.
The power_up_setup callback is used to enable the CCI interface for
the cluster being brought up. This must be done in assembly before
the kernel environment is entered.
Thanks to Achin Gupta and Nicolas Pitre for their help and
contributions.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
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If 4 CPUs are assumed, the A15x1-A7x1 model configuration would never
shut down the initial cluster as the 0xf reset bit mask will never be
observed. Let's construct this mask based on the provided information
in the DCSCB config register for the number of CPUs per cluster.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
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It is possible for a CPU to be told to power up before it managed
to power itself down. Solve this race with a usage count as mandated
by the API definition.
Signed-off-by: nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
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This adds basic CPU and cluster reset controls on RTSM for the
A15x4-A7x4 model configuration using the Dual Cluster System
Configuration Block (DCSCB).
The cache coherency interconnect (CCI) is not handled yet.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
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All the calls to gic_secondary_init() pass 0 as the first argument.
Since this function is called on each CPU when starting, it can be done
in a platform-independent way via a CPU notifier registered by the GIC
code.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Tested-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
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Previously, the gic_handle_cascade_irq() function was calling the
ARM-specific do_bad_IRQ() function which calls handle_bad_irq() after
acquiring the desk->lock. Locking the cascaded IRQ desc is not needed
for error reporting, so just call handle_bad_irq() directly.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
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These functions have been introduced by commit 10a8c383 (irq: introduce
entry and exit functions for chained handlers) in asm/mach/irq.h. This
patch moves them to linux/irqchip/chained_irq.h so that generic irqchip
drivers do not rely on architecture specific header files.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
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This patch prepares the removal of <asm/mach/irq.h> include in the
GIC and VIC irqchip drivers.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
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Currently ARM_DT_BL_CPUFREQ gets enabled by default which causes a
kernel-oops on Arndale board. Forcing this to only when BIG_LITTLE is
enabled fixes following issue.
Unable to handle kernel paging request at virtual address ffffffd0
pgd = c0004000
[ffffffd0] *pgd=6f7fe821, *pte=00000000, *ppte=00000000
Internal error: Oops: 17 [#2] PREEMPT SMP THUMB2
Modules linked in:
CPU: 0 Tainted: G D (3.8.0-rc4+ #2)
PC is at kthread_data+0xa/0x10
LR is at wq_worker_sleeping+0xf/0xa4
pc : [<c0035726>] lr : [<c0032273>] psr: a00000b3
sp : ef0adb98 ip : 00000001 fp : ef0a6080
r10: c1bb7140 r9 : c05cd140 r8 : ef0ac000
r7 : ef0adbb8 r6 : ef0a6080 r5 : 00000000 r4 : b0000000
r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : ef0a6080
Flags: NzCv IRQs off FIQs on Mode SVC_32 ISA Thumb Segment user
Control: 50c5387d Table: 6e4c806a DAC: 55555555
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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