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Macro name for spi controller driver has been modified, so update default
board file accordingly.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
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The serial TX IRQ is not simply (RX IRQ + 1) on some Blackfin chips,
so move the values to the platform resources.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
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The default for the Blackfin SPI driver is 8 bits and dma disabled,
so many of the bfin5xx_spi_chip resources are redundant. So punt
those parts.
Further, drivers should themselves be declaring 16 bit transfers,
so for those that do, and for the ones which no longer do 16 bit
transfers, drop the bfin5xx_spi_chip resources.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The SPORT/UART driver doesn't use the secondary channel pins, so don't
try and request them thus keeping other drivers from using them.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Move all the pin settings out of the Kconfig and into the platform
resources (MII vs RMII). This clean up also lets us push out the
phy settings so that board porters may control the layout.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The num_chipselect field for on-chip Blackfin SPI buses is supposed to
be 1 larger than the number of actual CSs available. This is because
the hardware starts counting at 1 and not 0. There is a field for "CS0",
but it is marked as "reserved" everywhere.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Harald Krapfenbauer <harald.krapfenbauer@bluetechnix.at>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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