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2013-02-21Merge branch 'mips-next-3.9' of ↵Ralf Baechle
git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
2013-02-19MIPS: ath79: add clock setup code for the QCA955X SoCsGabor Juhos
The patch adds code to get various clock frequencies from the PLLs used in the QCA955x SoCs. Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com> Cc: Giori, Kathy <kgiori@qca.qualcomm.com> Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4945/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-10-01MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLsGabor Juhos
Besides the CPU and DDR PLLs, the CPU and DDR frequencies can be derived from other PLLs in the SRIF block on the AR934x SoCs. The current code does not checks if the SRIF PLLs are used and this can lead to incorrectly calculated CPU/DDR frequencies. Fix it by calculating the frequencies from SRIF PLLs if those are used on a given board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: <stable@vger.kernel.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4324/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-10-01MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934xGabor Juhos
The current dividers in the code are wrong and this leads to broken CPU frequency calculation on boards where the fractional part is used. For example, if the SoC is running from a 40MHz reference clock, refdiv=1, nint=14, outdiv=0 and nfrac=31 the real frequency is 579.375MHz but the current code calculates 569.687MHz instead. Because the system time is indirectly related to the CPU frequency the broken computation causes drift in the system time. The correct divider is 2^6 for the CPU PLL and 2^10 for the DDR PLL. Use the correct values to fix the issue. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: stable@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4305/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-15MIPS: ath79: add clock initialization code for AR934XGabor Juhos
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> Cc: linux-mips@linux-mips.org Cc: mcgrof@infradead.org Patchwork: https://patchwork.linux-mips.org/patch/3507/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: ath79: add AR933X specific clock initGabor Juhos
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Kathy Giori <kgiori@qca.qualcomm.com> Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com> Patchwork: https://patchwork.linux-mips.org/patch/2522/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-01-18MIPS: Add initial support for the Atheros AR71XX/AR724X/AR931X SoCsGabor Juhos
This patch adds initial support for various Atheros SoCs based on the MIPS 24Kc core. The following models are supported at the moment: - AR7130 - AR7141 - AR7161 - AR9130 - AR9132 - AR7240 - AR7241 - AR7242 The current patch contains minimal support only, but the resulting kernel can boot into user-space with using of an initramfs image on various boards which are using these SoCs. Support for more built-in devices and individual boards will be implemented in further patches. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1947/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>