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2014-06-18clk: Fix slab corruption in clk_unregister()Stephen Boyd
commit 874f224cc52d64c912087e68e3724be95ad80ee7 upstream. When a clock is unregsitered, we iterate over the list of children and reparent them to NULL (i.e. orphan list). While iterating the list, we should use the safe iterators because the children list for this clock is changing when we reparent the children to NULL. Failure to iterate safely can lead to slab corruption like this: ============================================================================= BUG kmalloc-128 (Not tainted): Poison overwritten ----------------------------------------------------------------------------- Disabling lock debugging due to kernel taint INFO: 0xed0c4900-0xed0c4903. First byte 0x0 instead of 0x6b INFO: Allocated in clk_register+0x20/0x1bc age=297 cpu=2 pid=70 __slab_alloc.isra.39.constprop.42+0x410/0x454 kmem_cache_alloc_trace+0x200/0x24c clk_register+0x20/0x1bc devm_clk_register+0x34/0x68 0xbf0000f0 platform_drv_probe+0x18/0x48 driver_probe_device+0x94/0x360 __driver_attach+0x94/0x98 bus_for_each_dev+0x54/0x88 bus_add_driver+0xe8/0x204 driver_register+0x78/0xf4 do_one_initcall+0xc4/0x17c load_module+0x19ac/0x2294 SyS_init_module+0xa4/0x110 ret_fast_syscall+0x0/0x48 INFO: Freed in clk_unregister+0xd4/0x140 age=23 cpu=2 pid=73 __slab_free+0x38/0x41c clk_unregister+0xd4/0x140 release_nodes+0x164/0x1d8 __device_release_driver+0x60/0xb0 driver_detach+0xb4/0xb8 bus_remove_driver+0x5c/0xc4 SyS_delete_module+0x148/0x1d8 ret_fast_syscall+0x0/0x48 INFO: Slab 0xeec50b90 objects=25 used=0 fp=0xed0c5400 flags=0x4080 INFO: Object 0xed0c48c0 @offset=2240 fp=0xed0c4a00 Bytes b4 ed0c48b0: 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a ZZZZZZZZZZZZZZZZ Object ed0c48c0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ed0c48d0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ed0c48e0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ed0c48f0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ed0c4900: 00 00 00 00 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b ....kkkkkkkkkkkk Object ed0c4910: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ed0c4920: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ed0c4930: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b a5 kkkkkkkkkkkkkkk. Redzone ed0c4940: bb bb bb bb .... Padding ed0c49e8: 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a ZZZZZZZZZZZZZZZZ Padding ed0c49f8: 5a 5a 5a 5a 5a 5a 5a 5a ZZZZZZZZ CPU: 3 PID: 75 Comm: mdev Tainted: G B 3.14.0-11033-g2054ba5ca781 #35 [<c0014be0>] (unwind_backtrace) from [<c0012240>] (show_stack+0x10/0x14) [<c0012240>] (show_stack) from [<c04b74a0>] (dump_stack+0x70/0xbc) [<c04b74a0>] (dump_stack) from [<c00f7a78>] (check_bytes_and_report+0xbc/0x100) [<c00f7a78>] (check_bytes_and_report) from [<c00f7c48>] (check_object+0x18c/0x218) [<c00f7c48>] (check_object) from [<c00f7efc>] (__free_slab+0x104/0x144) [<c00f7efc>] (__free_slab) from [<c04b6668>] (__slab_free+0x3dc/0x41c) [<c04b6668>] (__slab_free) from [<c014c008>] (load_elf_binary+0x88/0x12b4) [<c014c008>] (load_elf_binary) from [<c0105a44>] (search_binary_handler+0x78/0x18c) [<c0105a44>] (search_binary_handler) from [<c0106fc0>] (do_execve+0x490/0x5dc) [<c0106fc0>] (do_execve) from [<c0036b8c>] (____call_usermodehelper+0x134/0x168) [<c0036b8c>] (____call_usermodehelper) from [<c000f048>] (ret_from_fork+0x14/0x2c) FIX kmalloc-128: Restoring 0xed0c4900-0xed0c4903=0x6b Fixes: fcb0ee6a3d33 (clk: Implement clk_unregister) Cc: Jiada Wang <jiada_wang@mentor.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-06-18clk: Fix double free due to devm_clk_register()Stephen Boyd
commit 293ba3b4a4fd54891b900f2911d1a57e1ed4a843 upstream. Now that clk_unregister() frees the struct clk we're unregistering we'll free memory twice: first we'll call kfree() in __clk_release() with an address kmalloc doesn't know about and second we'll call kfree() in the devres layer. Remove the allocation of struct clk in devm_clk_register() and let clk_release() handle it. This fixes slab errors like: ============================================================================= BUG kmalloc-128 (Not tainted): Invalid object pointer 0xed08e8d0 ----------------------------------------------------------------------------- Disabling lock debugging due to kernel taint INFO: Slab 0xeec503f8 objects=25 used=15 fp=0xed08ea00 flags=0x4081 CPU: 2 PID: 73 Comm: rmmod Tainted: G B 3.14.0-11032-g526e9c764381 #34 [<c0014be0>] (unwind_backtrace) from [<c0012240>] (show_stack+0x10/0x14) [<c0012240>] (show_stack) from [<c04b74dc>] (dump_stack+0x70/0xbc) [<c04b74dc>] (dump_stack) from [<c00f6778>] (slab_err+0x74/0x84) [<c00f6778>] (slab_err) from [<c04b6278>] (free_debug_processing+0x2cc/0x31c) [<c04b6278>] (free_debug_processing) from [<c04b6300>] (__slab_free+0x38/0x41c) [<c04b6300>] (__slab_free) from [<c03931bc>] (clk_unregister+0xd4/0x140) [<c03931bc>] (clk_unregister) from [<c02fb774>] (release_nodes+0x164/0x1d8) [<c02fb774>] (release_nodes) from [<c02f8698>] (__device_release_driver+0x60/0xb0) [<c02f8698>] (__device_release_driver) from [<c02f9080>] (driver_detach+0xb4/0xb8) [<c02f9080>] (driver_detach) from [<c02f8480>] (bus_remove_driver+0x5c/0xc4) [<c02f8480>] (bus_remove_driver) from [<c008c9b8>] (SyS_delete_module+0x148/0x1d8) [<c008c9b8>] (SyS_delete_module) from [<c000ef80>] (ret_fast_syscall+0x0/0x48) FIX kmalloc-128: Object at 0xed08e8d0 not freed Fixes: fcb0ee6a3d33 (clk: Implement clk_unregister) Cc: Jiada Wang <jiada_wang@mentor.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-06-18clk: vexpress: NULL dereference on error pathDan Carpenter
commit 6b4ed8b00e93bd31f24a25f59ed8d1b808d0cc00 upstream. If the allocation fails then we dereference the NULL in the error path. Just return directly. Fixes: ed27ff1db869 ('clk: Versatile Express clock generators ("osc") driver') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-06-18clk: tegra: Fix wrong value written to PLLE_AUXTuomas Tynkkynen
commit d2c834abe2b39a2d5a6c38ef44de87c97cbb34b4 upstream. The value written to PLLE_AUX was incorrect due to a wrong variable being used. Without this fix SATA does not work. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: improved changelog] Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-06-18clk: tegra: remove non-existent clocksStephen Warren
commit 9ba71705706aa83bcd7f9b74ae2d167da934c951 upstream. The Tegra124 clock driver currently provides 3 clocks that don't actually exist; 2 for NAND and one for UART5/UARTE. Delete these. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-06-18clk: s2mps11: Fix possible NULL pointer dereferenceKrzysztof Kozlowski
commit 238e14055da87d0d012257788e39fe0df3a82226 upstream. If parent device does not have of_node set the s2mps11_clk_parse_dt() returned NULL. This NULL was later passed to of_clk_add_provider() which dereferenced it in pr_debug() call. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-06-18CLK: TI: OMAP4/5/DRA7: Remove gpmc_fck from dummy clocksFlorian Vaussard
commit 8559087f0e9722a95df43fa5968bd1ee42bcf540 upstream. When arch/arm/mach-omap2/gpmc.c calls clk_get(..., "fck"), it will get a dummy clock and try to use it. As the rate is configured to zero, this will result in several divisions by zero, and misconfigured timings, with devices on the bus being lost in the La La Land. It is better to remove gpmc_fck from the dummy clocks, so that gpmc.c can fail gracefully. Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-04-16clk: hisi: remove static variableHaojian Zhuang
Remove the static variable. So these common clock register helper could be used in more SoCs. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-04-16clk: hip04: add clock driverHaojian Zhuang
Now only fixed rate clocks are appended into the clock driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-04-16clk: hisi: assign missing clk to tableHaojian Zhuang
The fixed rate and fixed factor clock isn't registered to clk table. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-04-16ARM: hs: add clk-hi3716Zhangfei Gao
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Zhang Mingjun <zhang.mingjun@linaro.org>
2014-04-16clk: hisilicon: add hi3620_mmc_clksZhangfei Gao
Suggest by Arnd: abstract mmc tuning as clock behavior, also because different soc have different tuning method and registers. hi3620_mmc_clks is added to handle mmc clock specifically on hi3620. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
2014-04-16exynos: driver raw read and write endian fixVictor Kamensky
Need to use endian neutral functions to read/write LE h/w registers. I.e instead of __raw_read[lw] and _raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first just read/write register with memory barrier, the second will byteswap it if host operates in BE mode. This patch covers drivers used by arndale board where all changes are trivial, sed like replacement of __raw_xxx functions with xxx_relaxed variant. Literally this sed program was used to make the change: s|__raw_readl|readl_relaxed|g s|__raw_writel|writel_relaxed|g s|__raw_readw|readw_relaxed|g s|__raw_writew|writew_relaxed|g Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-04-16clk: exynos5420: Enable Gate for sclk_usbphy3*Vivek Gautam
sclk_usbphy3* are the operational clocks used by USB 3.0 PHY on exynos5420 platform, but the same are not handled by the phy-samsung-usb3 driver. So enable the gates for these sclk_usbphy3* for now to make USB 3.0 ports present on smdk5420 working. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
2014-04-15Merge branch 'tracking-armlt-juno' into integration-linaro-vexpressJon Medhurst
Conflicts: arch/arm64/kernel/debug-monitors.c
2014-04-09clk: Add support for oscillators that can be controlled via the SCPI interface.Liviu Dudau
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2014-03-31clk: bcm21664: use common clock frameworkAlex Elder
Define the set of CCUs and provided clocks sufficient to satisfy the needs of all the existing clock references for BCM21664. Replace the "fake" fixed-rate clocks used previously with "real" ones. Note that only the minimal set of these clocks and CCUs is defined here. More clock definitions will need to be added as required by the addition of additional drivers. Signed-off-by: Alex Elder <elder@linaro.org>
2014-03-31clk: bcm281xx: move compatible string definitionsAlex Elder
The Broadcom 281xx clock code uses a #define for the compatible string for it's clock control units (CCUs). Rather than defining those in the C source file, define them in the header file that's shared by both the code and the device tree source file (along with all the clock ids). Signed-off-by: Alex Elder <elder@linaro.org>
2014-03-31clk: bcm281xx: define a bus clockAlex Elder
Define the bus clock "bsc3_apb". This bus clock has to be managed using the CCU policy mechanism, so add the definitions required for that to the clock and its CCU. This one bus clock in particular is defined because it is needed by peripheral clock "bsc3". Our boot loader does not properly activate "bsc3_apb", and as a result, "bsc3" isn't able to function properly. With "bsc3_apb" specified as a prerequisite clock for "bsc3", the latter works correctly. For now only this one bus clock is defined, because it allows correct operation of "bsc3". Others can be added later as needed (and this patch serves to show how that's done). Signed-off-by: Alex Elder <elder@linaro.org>
2014-03-31clk: bcm281xx: add bus clock supportAlex Elder
Add bus clock support. A bus clock has a subset of the components present in a peripheral clock (again, all optional): a gate; CCU policy management bits; and if needed, bits to control hysteresis. Signed-off-by: Alex Elder <elder@linaro.org>
2014-03-31clk: bcm281xx: implement prerequisite clocksAlex Elder
Allow a clock to specify a "prerequisite" clock. The prerequisite clock must be initialized before the clock that depends on it. A prerequisite clock is defined initially by its name; as that clock gets initialized the name gets replaced with a pointer to its clock structure pointer. In order to allow getting a reference to a clock by its name we call clkdev_add() for each clock as it gets set up. A new clk_lookup structure is added to the kona_clk type for this purpose. Rework the KONA_CLK() macro, and define a new KONA_CLK_PREREQ() variant that allows a prerequisite clock to be specified. There exist clocks that could specify more than one prequisite, but almost all clocks only ever use one. We can add support for more than one if we find we need it at some point. Signed-off-by: Alex Elder <elder@linaro.org>
2014-03-31clk: bcm281xx: add an initialized flagAlex Elder
Add a flag that tracks whether a clock has already been initialized. This will be used by the next patch to avoid initializing a clock more than once when it's listed as a prerequisite. Signed-off-by: Alex Elder <elder@linaro.org>
2014-03-31clk: bcm281xx: add clock hysteresis supportAlex Elder
Add support for clock gate hysteresis control. For now, if it's defined for a clock, it's enabled. Signed-off-by: Alex Elder <elder@linaro.org>
2014-03-31clk: bcm281xx: add clock policy supportAlex Elder
Add support for CCU policy engine control, and also for setting the mask bits for bus clocks that require a policy change to get activated. This includes adding validity checking framework for CCUs, to validate the policy fields if defined. Signed-off-by: Alex Elder <elder@linaro.org>
2014-03-31clk: bcm281xx: define CCU clock data staticallyAlex Elder
Rather than "manually" setting up each CCU's clock entries at run time, define a flexible array of generic Kona clock structures within the CCU structure itself. Each of these entries contains generic kona clock information (like its CCU pointer and clock framework initialization data). Each also has a pointer to a structure contianing clock type-dependent initialization data (like register definitions). Since we'll iterate over these arrays we need to be sure they have slots for all potential clock index values. (E.g. for the root CCU we must have at least BCM281XX_ROOT_CCU_CLOCK_COUNT slots.) To ensure this we always define an extra entry and fill it using the special initializer LAST_KONA_CLK. Just about everything we need to know about a clock can be defined statically. As a result, kona_clk_setup() can be changed to take just a kona_clk structure as its argument, and peri_clk_setup() can be simplified. With the information pre-defined we are also able to handle most clock setup genericially. We can do away with the CCU-specific callback functions that previously were needed to set up the entries in CCU's clock array. Move the definition of the ccu_data structure down in "clk-kona.h" to avoid a forward dependency. Signed-off-by: Alex Elder <elder@linaro.org>
2014-03-31clk: bcm281xx: initialize CCU structures staticallyAlex Elder
We know up front how many CCU's we'll support, so there's no need to allocate their data structures dynamically. Define a macro KONA_CCU_COMMON() to simplify the initialization of many of the fields in a ccu_data structure. Pass the address of a statically defined CCU structure to kona_dt_ccu_setup() rather than having that function allocate one. We also know at build time how many clocks a given CCU will provide, though the number of of them for each CCU is different. Record the number of clocks we need in the CCU's clk_onecell_data struct (which is used when we register the CCU with the common clock code as a clock provider). Rename that struct field "clk_data" (because "data" alone gets a little confusing). Use the known clock count to move the allocation of each CCU's clocks array into ccu_clks_setup() rather than having each CCU's setup callback function do it. (The real motivation behind all of this is that we'll be doing some static initialization of some additional CCU-specific data soon.) Signed-off-by: Alex Elder <elder@linaro.org>
2014-03-31clk: bcm281xx: change some symbol namesAlex Elder
As I developed the bcm281xx clock code I understood there were restrictions on device tree "compatible" strings names, and as a result "bcm11351" was used in places despite the part family being more properly called "bcm281xx". This can be a little confusing. In some cases I went to far and needlessly named things using "bcm11351" when that was not necessary. This patch remedies this. It renames the symbol used to define the "compatible" string (but not its value) so it uses "BCM281XX". Similarly, the name names provided to the CLK_OF_DECLARE() macro are changed, hoping to minimize the number of places that the confusing "11351" string is used. Signed-off-by: Alex Elder <elder@linaro.org>
2014-03-31clk: bcm281xx: use init_data.name for clock nameAlex Elder
Use the init_data.name field to hold the name of a Kona clock rather than duplicating it. Signed-off-by: Alex Elder <elder@linaro.org>
2014-03-31clk: bcm281xx: warn if ccu_wait_bit() failsAlex Elder
Don't let a failure of ccu_wait_bit() go unnoticed. Signed-off-by: Alex Elder <elder@linaro.org>
2014-03-31clk: support hardware-specific debugfs entriesAlex Elder
Add a new clk_ops->debug_init method to allow a clock hardware driver to populate the clock's debugfs directory with entries beyond those common for every clock. Signed-off-by: Alex Elder <elder@linaro.org>
2014-03-31Merge branch 'armsoc/for-3.15/drivers' of ↵Alex Elder
https://github.com/broadcom/mach-bcm into wip/llct-capri-support-1
2014-03-08Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds
git://git.linaro.org/people/mike.turquette/linux Pull clk driver fix from Mike Turquette: "Single fix for a clock driver merged in 3.14-rc1. Without this fix the CPU frequency cannot be scaled" * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: clk: shmobile: rcar-gen2: Use kick bit to allow Z clock frequency change
2014-03-05clk: shmobile: rcar-gen2: Use kick bit to allow Z clock frequency changeBenoit Cousson
The Z clock frequency change is effective only after setting the kick bit located in the FRQCRB register. Without that, the CA15 CPUs clock rate will never change. Fix that by checking if the kick bit is cleared and enable it to make the clock rate change effective. The bit is cleared automatically upon completion. Signed-off-by: Benoit Cousson <bcousson+renesas@baylibre.com> Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26clk:at91: Fix memory leak in of_at91_clk_master_setup()Masanari Iida
cppcheck detected following error [clk-master.c:245]: (error) Memory leak: characteristics The original code forgot to free characteristics when irq_of_parse_and_map() failed. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Acked-by Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26clk: nomadik: fix multiplatform problemLinus Walleij
The Nomadik debugfs screws up multiplatform boots if debugfs is enabled on the multiplatform image, since it's a simple initcall that is unconditionally executed and reads from certain memory locations. Fix this by checking that the driver has been properly initialized, so a base offset to the Nomadik SRC controller exists, before proceeding to register debugfs files. Reported-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-24clk: Correct handling of NULL clk in __clk_{get, put}Sylwester Nawrocki
Ensure clk->kref is dereferenced only when clk is not NULL. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-24Merge branch 'clk-tegra-more-fixes-3.14' of ↵Mike Turquette
git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes Fixes stray access to undefined registers, use of wrong clock parents & running clocks at wrong rates. All of these issues cause regressions in the form of boards that are unable to boot or crash and die horrible deaths.
2014-02-24clk: bcm281xx: don't disable unused peripheral clocksAlex Elder
Add the CLK_IGNORE_UNUSED flag when setting up a peripheral clock. This prevents unused clocks from getting disabled, and by doing this we can use the common clock code even before we've resolved all the spots that need to get a reference to their clock. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-24clk: bcm281xx: add initial clock framework supportAlex Elder
Add code for device tree support of clocks in the BCM281xx family of SoCs. Machines in this family use peripheral clocks implemented by "Kona" clock control units (CCUs). (Other Broadcom SoC families use Kona style CCUs as well, but support for them is not yet upstream.) A BCM281xx SoC has multiple CCUs, each of which manages a set of clocks on the SoC. A Kona peripheral clock is composite clock that may include a gate, a parent clock multiplexor, and zero, one or two dividers. There is a variety of gate types, and many gates implement hardware-managed gating (often called "auto-gating"). Most dividers divide their input clock signal by an integer value (one or more). There are also "fractional" dividers which allow division by non-integer values. To accomodate such dividers, clock rates and dividers are generally maintained by the code in "scaled" form, which allows integer and fractional dividers to be handled in a uniform way. If present, the gate for a Kona peripheral clock must be enabled when a change is made to its multiplexor or one of its dividers. Additionally, dividers and multiplexors have trigger registers which must be used whenever the divider value or selected parent clock is changed. The same trigger is often used for a divider and multiplexor, and a BCM281xx peripheral clock occasionally has two triggers. The gate, dividers, and parent clock selector are treated in this code as "components" of a peripheral clock. Their functionality is implemented directly--e.g. the common clock framework gate implementation is not used for a Kona peripheral clock gate. (This has being considered though, and the intention is to evolve this code to leverage common code as much as possible.) The source code is divided into three general portions: drivers/clk/bcm/clk-kona.h drivers/clk/bcm/clk-kona.c These implement the basic Kona clock functionality, including the clk_ops methods and various routines to manipulate registers and interpret their values. This includes some functions used to set clocks to a desired initial state (though this feature is only partially implemented here). drivers/clk/bcm/clk-kona-setup.c This contains generic run-time initialization code for data structures representing Kona CCUs and clocks. This encapsulates the clock structure initialization that can't be done statically. Note that there is a great deal of validity-checking code here, making explicit certain assumptions in the code. This is mostly useful for adding new clock definitions and could possibly be disabled for production use. drivers/clk/bcm/clk-bcm281xx.c This file defines the specific CCUs used by BCM281XX family SoCs, as well as the specific clocks implemented by each. It declares a device tree clock match entry for each CCU defined. include/dt-bindings/clock/bcm281xx.h This file defines the selector (index) values used to identify a particular clock provided by a CCU. It consists entirely of C preprocessor constants, to be used by both the C source and device tree source files. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-20clk: tegra124: remove gr2d and gr3d clocksPeter De Schrijver
Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the vic03 and gpu clocks respectively. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-02-20clk: tegra: Fix vic03 mux indexPeter De Schrijver
The vic03 mux uses a linear mapping. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-02-18Merge branch 'for_3.14-rcx/clk-fixes' of ↵Mike Turquette
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into clk-fixes
2014-02-18Merge tag 'mvebu-clk-fixes-3.14' of git://git.infradead.org/linux-mvebu into ↵Mike Turquette
clk-fixes mvebu clock fixes for v3.14 - kirkwood, dove, armada-xp, armada-370 - force clock init order broken by sorting DT ocp nodes by address - fixes boot failures on affected platforms
2014-02-18clk: shmobile: rcar-gen2: Fix qspi divisorLaurent Pinchart
The qspi clock divisor is incorrectly set to twice the value it should have, possibly because it has been computed based on PLL1 as the clock parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal frequencies, not the divisor values). Fix it. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-18clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocksLaurent Pinchart
The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as their parent, not the main clock. Fix it. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-17clk: tegra: use max divider if divider overflowsAndrew Bresticker
When requesting a rate less than the minimum clock rate for a divider, use the maximum divider value instead of bailing out with an error. This matches the behavior of the generic clock divider. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: cclk_lp has a pllx/2 dividerAndrew Bresticker
When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that the clk_super driver is aware of this. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker
The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with 6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114 and Tegra124 to use these clocks instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: fix host1x clock on Tegra124Mark Zhang
The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents. Change thte id to tegra_clk_host1x_8 so that the correct clock gets registered. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: PLLD2 fixes for hdmiDavid Ung
Set correct pll_d2_out0 divider and correct the p div values for pll_d2. Signed-off-by: David Ung <davidu@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
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