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path: root/drivers/gpu/drm/radeon/cik.c
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2013-11-18drm/radeon/cik: Add macrotile mode array queryMichel Dänzer
This is required to properly calculate the tiling parameters in userspace. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-15drm/radeon: use a single doorbell for cik kms computeAndrew Lewycky
A single doorbell page is plenty for cik kms compute. Use a single page and manage doorbell allocation by individual doorbells rather than pages. Identify doorbells by their index rather than byte offset. Signed-off-by: Andrew Lewycky <Andrew.Lewycky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-15drm/radeon: disable CIK CP semaphores for nowChristian König
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-11-15drm/radeon: allow semaphore emission to failChristian König
To workaround bugs and/or certain limits it's sometimes useful to fall back to waiting on fences. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-11-08drm/radeon: update cik_get_csb_buffer for hawaiiAlex Deucher
Set the PA_SC_RASTER_CONFIG[_1] registers for hawaii. The rest is the same as the other asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08drm/radeon: update firmware loading for hawaiiAlex Deucher
This just updates the firmware loading functions to look for the appropriate firmware files for hawaii. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08drm/radeon: update rb setup for hawaiiAlex Deucher
The formula needs to be adjusted since there are 4 RBs per SH rather than 2 as on previous asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08drm/radeon: add golden register settings for hawaiiAlex Deucher
The golden register settings are optimal settings for certain registers from the hardware team. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08drm/radeon: update cik_tiling_mode_table_init() for hawaiiAlex Deucher
Hawaii uses a different tiling configuration. Add support for it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08drm/radeon: minor updates to cik.c for hawaiiAlex Deucher
Skip programming a register that was removed and adjust the mask of the VM client status. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08drm/radeon: update cik_gpu_init() for hawaiiAlex Deucher
This adds the hawaii asic specific configuration details. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08Merge tag 'drm-intel-fixes-2013-11-07' of ↵Dave Airlie
git://people.freedesktop.org/~danvet/drm-intel into drm-next Bit a bit -fixes pull request in the merge window than usual dua to two feauture-y things: - Display CRCs are now enabled on all platforms, including the odd DP case on gm45/vlv. Since this is a testing-only feature it should ever hurt, but I figured it'll help with regression-testing -fixes. So I left it in and didn't postpone it to 3.14. - Display power well refactoring from Imre. Would have caused major pain conflict with the bdw stage 1 patches if I'd postpone this to -next. It's only an relatively small interface rework, so shouldn't cause pain. It's also been in my tree since almost 3 weeks already. That accounts for about two thirds of the pull, otherwise just bugfixes: - vlv backlight fix from Jesse/Jani - vlv vblank timestamp fix from Jesse - improved edp detection through vbt from Ville (fixes a vlv issue) - eDP vdd fix from Paulo - fixes for dvo lvds on i830M - a few smaller things all over Note: This contains a backmerge of v3.12. Since the -internal branch always applied on top of -nightly I need that unified base to merge bdw patches. So you'll get a conflict with radeon connector props when pulling this (and nouveau/master will also conflict a bit when Ben doesn't rebase). The backmerge itself only had conflicts in drm/i915. There's also a tiny conflict between Jani's backlight fix and your sysfs lifetime fix in drm-next. * tag 'drm-intel-fixes-2013-11-07' of git://people.freedesktop.org/~danvet/drm-intel: (940 commits) drm/i915/vlv: use per-pipe backlight controls v2 drm/i915: make backlight functions take a connector drm/i915: move opregion asle request handling to a work queue drm/i915/vlv: use PIPE_START_VBLANK interrupts on VLV drm/i915: Make intel_dp_is_edp() less specific drm/i915: Give names to the VBT child device type bits drm/i915/vlv: enable HDA display audio for Valleyview2 drm/i915/dvo: call ->mode_set callback only when the port is running drm/i915: avoid unclaimed registers when capturing the error state drm/i915: Enable DP port CRC for the "auto" source on g4x/vlv drm/i915: scramble reset support for DP port CRC on vlv drm/i915: scramble reset support for DP port CRC on g4x drm/i916: add "auto" pipe CRC source ... Conflicts: MAINTAINERS drivers/gpu/drm/i915/intel_panel.c drivers/gpu/drm/nouveau/core/subdev/mc/base.c drivers/gpu/drm/radeon/atombios_encoders.c drivers/gpu/drm/radeon/radeon_connectors.c
2013-11-01drm/radeon: drop CP page table updates & cleanup v2Christian König
The DMA ring seems to be stable now. v2: remove pt_ring_index as well Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-01drm/radeon: don't use PACKET2 on CIKMarek Olšák
It is said to cause hangs. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-01drm/radeon: fix endian handling in rlc buffer setupAlex Deucher
The buffers needs to be in little endian format. Noticed-by: Sylvain BERTRAND <sylware@legeek.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-01drm/radeon: implement blit copy callback for CIKAlex Deucher
Uses the CP ring rather than the DMA ring. Useful for debugging and benchmarking. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-01drm/radeon: add a connector property for ditherAlex Deucher
Allows you to enable dither in the display hardware when the monitor supports lower a lower bpc than the current framebuffer format. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-01drm/radeon: Add support for programming the FMT blocksAlex Deucher
The FMT blocks control how data is sent from the backend of the display pipe to to monitor. Proper set up of the FMT blocks are required for 30bpp formats. Additionally, dithering can be enabled on for better display with 18 and 24bpp displays. The exception is LVDS/eDP which atom takes care of in the SelectCRTC_Source table. For now just enable truncation until we test dithering more. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-10-18drm/radeon: make missing smc ucode non-fatal (CI)Alex Deucher
Prevent driver load problems if the smc is missing. bug: https://bugzilla.kernel.org/show_bug.cgi?id=63011 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-10-18drm/radeon: stop the leaks in cik_ib_testChristian König
Stop leaking IB memory and scratch register space when the test fails. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-10-09drm/radeon: improve soft reset on CIKAlex Deucher
Disable CG/PG before resetting. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-24drm/radeon/cik: fix overflow in vram fetchAlex Deucher
Missing ULL when calculating the amount of vram leads to an overflow when the amount of vram is >= 4G. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-09-20drm/radeon/cik: Fix encoding of number of banks in tiling configuration infoMichel Dänzer
There are multiple valid values, not just 0 or 1. Required to properly support 2D tiling in the userspace drivers. Cc: stable@vger.kernel.org Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-20drm/radeon/cik: Fix printing of client name on VM protection faultMichel Dänzer
The string is encoded from the MSB to the LSB of the register. Cc: stable@vger.kernel.org Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-11drm/radeon: fix typo in PG flagsAlex Deucher
s/CG/PG/ in the GFX powergating flag name. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-11drm/radeon/cik: update gpu_init for an additional berlin gpuAlex Deucher
Sets the right paramters for the new pci id. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-09-11drm/radeon: add spinlocks for indirect register accesssAlex Deucher
This adds spinlocks to protect access to other indirect register apertures. These indirect spaces are used pretty infrequently and we haven't had an reported problems, but better safe than sorry. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-11drm/radeon/cik: properly handle internal cp intsAlex Deucher
The internal cp interrupts need to be enabled and disabled at specific times in order clockgating to work properly. This patch changes the handling of the CP_INT_CNTL register to respect the current state of the internal CP interrupts when making changes to the other interrupts in CP_INT_CNTL. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-02Merge branch 'drm-next-3.12' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie
into drm-next Alex writes: This is the radeon drm-next request. Big changes include: - support for dpm on CIK parts - support for ASPM on CIK parts - support for berlin GPUs - major ring handling cleanup - remove the old 3D blit code for bo moves in favor of CP DMA or sDMA - lots of bug fixes [airlied: fix up a bunch of conflicts from drm_order removal] * 'drm-next-3.12' of git://people.freedesktop.org/~agd5f/linux: (898 commits) drm/radeon/dpm: make sure dc performance level limits are valid (CI) drm/radeon/dpm: make sure dc performance level limits are valid (BTC-SI) (v2) drm/radeon: gcc fixes for extended dpm tables drm/radeon: gcc fixes for kb/kv dpm drm/radeon: gcc fixes for ci dpm drm/radeon: gcc fixes for si dpm drm/radeon: gcc fixes for ni dpm drm/radeon: gcc fixes for trinity dpm drm/radeon: gcc fixes for sumo dpm drm/radeonn: gcc fixes for rv7xx/eg/btc dpm drm/radeon: gcc fixes for rv6xx dpm drm/radeon: gcc fixes for radeon_atombios.c drm/radeon: enable UVD interrupts on CIK drm/radeon: fix init ordering for r600+ drm/radeon/dpm: only need to reprogram uvd if uvd pg is enabled drm/radeon: check the return value of uvd_v1_0_start in uvd_v1_0_init drm/radeon: split out radeon_uvd_resume from uvd_v4_2_resume radeon kms: fix uninitialised hotplug work usage in r100_irq_process() drm/radeon/audio: set up the sads on DCE3.2 asics drm/radeon: fix handling of variable sized arrays for router objects ... Conflicts: drivers/gpu/drm/i915/i915_dma.c drivers/gpu/drm/i915/i915_gem_dmabuf.c drivers/gpu/drm/i915/intel_pm.c drivers/gpu/drm/radeon/cik.c drivers/gpu/drm/radeon/ni.c drivers/gpu/drm/radeon/r600.c
2013-08-30drm/radeon: enable UVD interrupts on CIKChristian König
The same as on evergreen. Signed-off-by: Christian König <christian.koenig@amd.com> Reported-by: FrankR Huang <FrankR.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-08-30drm/radeon: fix init ordering for r600+Alex Deucher
The vram scratch buffer needs to be initialized before the mc is programmed otherwise we program 0 as the GPU address of the default GPU fault page. In most cases we put vram at zero anyway and reserve a page for the legacy vga buffer so in practice this shouldn't cause any problems, but better to make it correct. Was changed in: 6fab3febf6d949b0a12b1e4e73db38e4a177a79e Reported-by: FrankR Huang <FrankR.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-08-30drm/radeon: split out radeon_uvd_resume from uvd_v4_2_resumeAlex Deucher
For powergating, we just need to re-init the registers, there is no need to restore the uvd BOs. This just adds needless work when powergating uvd for playback while the system is on. We only need to restore the uvd BOs on an actual resume from suspend or when the driver loads. This fixes multi-stream UVD playback on KB systems. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2013-08-30drm/radeon: fill in gpu_init for berlin GPU coresAlex Deucher
This fills in the GPU specific details for berlin GPU cores so that the driver will work with them. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-08-30drm/radeon: update line buffer allocation for dce8Alex Deucher
We need to allocate line buffer to each display when setting up the watermarks. Failure to do so can lead to a blank screen. This fixes blank screen problems on dce8 asics. Based on an initial fix from: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-08-30drm/radeon/cik: properly set up the clearstate buffer for pg (v2)Alex Deucher
The format of the clearstate buffer used for pg (powergating) changed between NI and SI. This formats it properly for what the hardware expects on SI+. v2: fix addresses Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: fixes for gfx clockgating on CIKAlex Deucher
Clockgating requires signalling between the CP and the RLC to work properly. Resetting the CP block in the CP resume code messed up the internal coordination between the blocks. Removing the reset allows gfx clockgating to work properly. However, when gfx clock gating is enabled, there is a strange interaction with dpm which causes the chip to stay in the high performance level all the time, so leave gfx clockgating disabled for now. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: restructure cg/pg on cik (v2)Alex Deucher
- use new cg/pg flags for finer grained clock and powergating control - restructure the cg/pg code so it can be called from other components such as dpm v2: fix build breakage from rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add audio support for DCE6/8 GPUs (v12)Alex Deucher
Similar to DCE4/5, but supports multiple audio pins which can be assigned per afmt block. v2: rework the driver to handle more than one audio pin. v3: try different dto reg v4: properly program dto v5 (ck): change dto programming order v6: program speaker allocation block v7: rebase v8: rebase on Rafał's changes v9: integrated Rafał's comments, update to latest drm_edid_to_speaker_allocation API v10: add missing line break in error message v11: add back audio enabled messages v12: fix copy paste typo in r600_audio_enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Rafał Miłecki <zajec5@gmail.com>
2013-08-30drm/radeon: separate DMA codeChristian König
Similar to separating the UVD code, just put the DMA functions into separate files. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: separate UVD code v3Christian König
Our different hardware blocks are actually completely separated, so it doesn't make much sense any more to structure the code by pure chipset generations. Start restructuring the code by separating our the UVD block. v2: updated commit message v3: rebased and restructurized start/stop functions for kv dpm. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: remove special handling for the DMA ringChristian König
Now that we have callbacks for [rw]ptr handling we can remove the special handling for the DMA rings and use the callbacks instead. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: rework UVD writeback & [rw]ptr handlingChristian König
The hardware just doesn't support this correctly. Disable it before we accidentally write anywhere we shouldn't. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: implement UVD powergating for KB/KVAlex Deucher
Powergate the UVD block when not in use to save power. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: restructure UVD code to handle UVD PG (v2)Alex Deucher
When we PG (powergate) UVD, we need to re-initialize it before we can use it again. v2: rebase on UVD stop fixes Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add dpm support for CI dGPUs (v2)Alex Deucher
This adds dpm support for btc asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen switching Set radeon.dpm=1 to enable. v2: remove unused radeon_atombios.c changes, make missing smc ucode non-fatal Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/kms: add dpm support for KB/KVAlex Deucher
This adds dpm support for KB/KV asics. This includes: - dynamic engine clock scaling - dynamic voltage scaling - power containment - shader power scaling Set radeon.dpm=1 to enable. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add get_temperature() callbacks for CIK (v2)Alex Deucher
This added support for the on-chip thermal sensors on CIK asics. v2: fix register offset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/cik: add rlc helpers for DPMAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: implement clock and power gating for CIK (v3)Alex Deucher
Only the APUs support power gating. v2: disable cgcg for now v3: workaround hw issue in mgcg Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: convert SI,CIK to use sumo_rlc functionsAlex Deucher
and remove duplicate si_rlc functions. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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