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path: root/drivers/mtd/devices/m25p80.c
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2014-01-27mtd: m25p80: Set rx_nbits for Quad SPI transfersGeert Uytterhoeven
When using the Quad Read opcode, SPI masters still use Single SPI transfers, as spi_transfer.rx_nbits defaults to SPI_NBITS_SINGLE. Use SPI_NBITS_QUAD to fix this. While an earlier version of commit 3487a63955c34ea508bcf4ca5131ddd953876e2d ("drivers: mtd: m25p80: add quad read support") did this correctly, it was forgotten in the version that got merged. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-01-27mtd: m25p80: Enable Quad SPI read transfers for s25fl512sGeert Uytterhoeven
Spansion s25fl512s supports Quad SPI transfers, hence set the M25P80_QUAD_READ flag. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-01-20mtd: m25p80: assign default read commandBrian Norris
In the following commit (in -next): commit 8552b439aba7f32063755d23f79ca27b4d0a3115 drivers: mtd: m25p80: convert "bool" read check into an enum We converted the boolean 'fast_read' property to become an enum 'flash_read', but at the same time, we changed the conditional path so that it doesn't choose a default value in some cases (technically, we choose the correct default simply by virtue of devm_kzalloc(), which zeroes this out to be a NORMAL read operation, but still...). Fix this by setting a default for the 'else' clause. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Sourav Poddar <sourav.poddar@ti.com> Acked-by: Marek Vasut <marex@denx.de>
2014-01-16mtd: m25p80: Use OPCODE_QUAD_READ_4B for 4-byte addressingGeert Uytterhoeven
commit 3487a63955c34ea508bcf4ca5131ddd953876e2d ("drivers: mtd: m25p80: add quad read support") in -next added both the 3-byte OPCODE_QUAD_READ and the 4-byte OPCODE_QUAD_READ_4B, but incorrectly uses OPCODE_QUAD_READ for both 3-byte and 4-byte addressing. Use OPCODE_QUAD_READ_4B in the 4-byte case to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-01-03mtd: m25p80: add support for m25px16Igor Grinberg
Add support for Micron m25px16 spi flash chip. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-01-03drivers: mtd: m25p80: add quad read supportSourav Poddar
Some flash also support quad read mode. Adding support for quad read mode in m25p80 for Spansion and Macronix flash. [Tweaked by Brian] With this patch, quad-read support will override fast-read and normal-read, if the SPI controller and flash chip both support it. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-01-03drivers: mtd: m25p80: convert "bool" read check into an enumSourav Poddar
This is a cleanup prior to adding quad read support. This will facilitate easy addition of more read commands check under an enum rather that defining a separate bool for it. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2013-11-06mtd: m25p80: fixup device removal failure pathBrian Norris
Device removal should fail if MTD unregistration fails. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de>
2013-11-06mtd: m25p80: add support for Macronix mx25l3255eBrian Norris
A new 32Mbit SPI NOR flash from Macronix. Nothing special. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de>
2013-11-06mtd: m25p80: remove 'disabled' device checkBrian Norris
It seems like the following commit was never necessary commit 5f949137952020214cd167093dd7be448f21c079 Author: Shaohui Xie <Shaohui.Xie@freescale.com> Date: Fri Oct 14 15:49:00 2011 +0800 mtd: m25p80: don't probe device which has status of 'disabled' because it duplicates the code in of_platform_device_create_pdata() which ensures that 'disabled' nodes are never instantiated. Also, drop the __maybe_unused. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: <devicetree@vger.kernel.org>
2013-11-06mtd: m25p80: remove M25PXX_USE_FAST_READ KconfigBrian Norris
Remove the compile-time option for FAST_READ, since we have run-time support for detecting it. This refactors the logic for enabling fast-read, such that for DT-enabled devices, we honor the "m25p,fast-read" property but for non-DT devices, we default to using FAST_READ whenever the flash device supports it. Normal READ and FAST_READ differ only in the following: * FAST_READ supports SPI higher clock frequencies [1] * number of dummy cycles; FAST_READ requires 8 dummy cycles (whereas READ requires 0) to allow the flash sufficient setup time, even when running at higher clock speeds Thus, for flash chips which support FAST_READ, there is otherwise no limiting reason why we cannot use the FAST_READ opcode instead of READ. It simply allows the SPI controller to run at higher clock rates. So theoretically, nobody should be needing the compile-time option anyway. [1] I have a Spansion S25FL128S datasheet which says: "The maximum operating clock frequency for the READ command is 50 MHz." And: "The maximum operating clock frequency for FAST READ command is 133 MHz." Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2013-11-06mtd: m25p80: re-align ID entriesBrian Norris
No change in the table data. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Sourav Poddar <sourav.poddar@ti.com>
2013-11-06mtd: m25p80: remove obsolete FIXMEBrian Norris
The FIXME and NOTE have already been fixed (we have FAST_READ support). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Sourav Poddar <sourav.poddar@ti.com> Acked-by: Marek Vasut <marex@denx.de>
2013-11-06mtd: m25p80: fix allocation sizeBrian Norris
This patch fixes two memory errors: 1. During a probe failure (in mtd_device_parse_register?) the command buffer would not be freed. 2. The command buffer's size is determined based on the 'fast_read' boolean, but the assignment of fast_read is made after this allocation. Thus, the buffer may be allocated "too small". To fix the first, just switch to the devres version of kzalloc. To fix the second, increase MAX_CMD_SIZE unconditionally. It's not worth saving a byte to fiddle around with the conditions here. This problem was reported by Yuhang Wang a while back. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reported-by: Yuhang Wang <wangyuhang2014@gmail.com> Reviewed-by: Sourav Poddar <sourav.poddar@ti.com> Cc: <stable@vger.kernel.org>
2013-11-06mtd: m25p80: Add support for Micron N25Q512A memoryPriyanka Jain
Micron N25Q512A is a spi flash memory with following features: -64MB size, 1.8V, Mulitple I/O, 4KB Sector erase memory. -Memory is organised as 1024(64KB) main sectors. -Each sector is divided into 256 pages. -Register set/Opcodes are similar to other N25Q family products. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2013-10-27mtd: m25p80: Add support for ESMT F25L32PAFlavio Silveira
This flashchip is used in D-Link DIR-610 A1 router board and maybe several others, yet is not kernel upstream. So add support for it according to datasheet [0], making it easier to support other boards using this flashchip in the future. [0] http://www.esmt.com.tw/DB/manager/upload/F25L32PA.pdf Signed-off-by: Flavio Silveira <fggs@terra.com.br> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2013-09-27mtd: m25p80: Fix 4 byte addressing mode for Micron devices.Elie De Brauwer
According to the datasheet for Micron n25q256a (N25Q256A13ESF40F) 4-byte addressing mode should be entered as follows: <quote> To enter or exit the 4-byte address mode, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. (Note: The WRITE ENABLE command must NOT be executed on the N25Q256A83ESF40x and N25Q256A83E1240x devices.) S# must be driven LOW. The effect of the command is immediate; after the command has been executed, the write enable latch bit is cleared to 0. </quote> Micron's portable way to perform this for all types of Micron flash is to first issue a write enable, then switch the addressing mode followed by a write disable to avoid leaving the flash in a write- able state. Signed-off-by: Elie De Brauwer <eliedebrauwer@email.com> [Brian: reworked a bit] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-30mtd: chips: Add support for PMC SPI Flash chips in m25p80.cMichel Stempin
Add support for PMC (now Chingis, part of ISSI) Pm25LV512 (512 Kib), Pm25LV010 (1 Mib) and Pm25LQ032 (32 Mib) SPI Flash chips. This patch addresses two generations of PMC SPI Flash chips: - Pm25LV512 and Pm25LV010: these have 4KiB sectors and 32KiB blocks. The 4KiB sector erase uses a non-standard opcode (0xd7). They do not support JEDEC RDID (0x9f), and so they can only be detected by matching their name string with pre-configured platform data. Because of the cascaded acquisitions, the datasheet is no longer available on the current manufacturer's website, although it is still commonly used in some recent wireless routers (<https://forum.openwrt.org/viewtopic.php?pid=186360#p186360>). The only public datasheet available seems to be on GeoCities: <http://www.geocities.jp/scottle556/pdf/Pm25LV512-010.pdf> - Pm25LQ032: a newer generation flash, with 4KiB sectors and 64KiB blocks. It uses the standard erase and JEDEC read-ID opcodes. Manufacturer's datasheet is here: <http://www.chingistek.com/img/Product_Files/Pm25LQ032C%20datasheet%20v1.6.1.pdf> This patch is resent in order to take into account both Brian Norris remarks and this upstream patch: commit e534ee4f9ca29fdb38eea4b0c53f2154fbd8c1ee Author: Krzysztof Mazur <krzysiek@podlesie.net> Date: Fri Feb 22 15:51:05 2013 +0100 mtd: m25p80: introduce SST_WRITE flag for SST byte programming Not all SST devices implement the SST byte programming command. Some devices (like SST25VF064C) implement only standard m25p80 page write command. Now SPI flash devices that need sst_write() are explicitly marked with new SST_WRITE flag and the decision to use sst_write() is based on this flag instead of manufacturer id. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr> [Brian: fixed conflict] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-30mtd: m25p80: add support for mr25h10Markus Niebel
This adds support for the Everspin mr25h10 MRAM chip to the m25p80 driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-30mtd: m25p80: make CONFIG_M25PXX_USE_FAST_READ safe to enableSascha Hauer
This patch adds a flag to struct flash_info indicating that fast_read is not supported. This now gives the following logic when determing whether to enable fastread: If the flash chip does not support fast_read, then disable it. Otherwise: 1) enable fast_read if device node contains m25p,fast-read 2) enable fast_read if forced in Kconfig This makes enabling CONFIG_M25PXX_USE_FAST_READ a safe option since we no longer enable the fast_read option unconditionally. For now fast_read is disabled for the everspin mr25h256 and the catalyst devices. Others may need the flag aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-30mtd: m25p80: Pass flags through CAT25_INFO macroSascha Hauer
The flags may have to be overwritten, so add them to the CAT25_INFO macro. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-30mtd: m25p80: remove unnecessary ifdefSascha Hauer
of_property_read_bool properly compiles away, no need to ifdef this for non DT builds. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-30mtd: m25p80: Micron SPI uses Macronix-style 4-byte addressingBrian Norris
For SPI NOR flash that are larger than 128Mbit (16MiB), we need 4 bytes of address space to reach the entire flash; however, the original SPI flash protocol used only 3 bytes for the address. So far, the practice for handling this has been either to use new command opcodes that are defined to use 4 bytes for their address, or to use special mode-switching command to configure all traditionally-3-byte-address commands to take 4 bytes instead. Macronix and Spansion developed two incompatible methods for entering/exiting "4-byte address mode." Micron flash uses the Macronix method (OPCODE_{EN4B,EX4B}), not the Spansion method. This patch solves addressing issues on Micron n25q256a and provides the ability to support other future Micron SPI flash >16MiB. Quoting a Micron representative: "Majority of our NOR that needs 4-byte addressing (256Mb or 32MB and higher) enter and exit 4byte through B7h and E9h commands. The N25Q256A7xxx and N25Q512A7xxx parts do not support 4-byte addressing mode via B7h or E9h command." They further clarified that those that don't support the enter/exit opcodes (B7h/E9h) are manufactured specifically to come up by default in 4-byte mode. We don't need to treat those parts any diffently, as they will discard the EN4B opcode as a no-op. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-30mtd: devices: use dev_get_platdata()Jingoo Han
Use the wrapper function for retrieving the platform data instead of accessing dev->platform_data directly. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-05mtd: devices: added the 16MiB winbond deviceGirish K S
Added a 16MiB winbond devce to the device list erase size = 64KiB and number of blocks = 256. Signed-off-by: Girish K S <ks.giri@samsung.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-05mtd: m25p80: correct EN4B/EX4B commentBrian Norris
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-05mtd: m25p80: utilize dedicated 4-byte addressing commandsBrian Norris
Traditionally, the command set used by SPI flash only supported a 3-byte address. However, large SPI flash (>= 32MiB, or 256Mib) require 4 bytes to address the entire flash. Most manufacturers have supplied a mode switch (via a "bank register writer", or a "enable 4-byte mode" command), which tells the flash to expect 4 address cycles from now on, instead of 3. This mode remains until power is cut, the reset line is triggered (on packages where present), or a command is sent to reset the flash or to reset the 3-byte addressing mode. As an alternative, some flash manufacturers have developed a new command set that accept a full 4-byte address. They can be used orthogonally to any of the modes; that is, they can be used when the flash is in either 3-byte or 4-byte address mode. Now, there are a number of reasons why the "stateful" 4-byte address mode switch may not be acceptable. For instance, some SoC's perform a dumb boot sequence in which they only send 3-byte read commands to the flash. However, if an unexpected reset occurs, the flash chip cannot be guaranteed to return to its 3-byte mode. Thus, the SoC controller and flash will not understand each other. (One might consider hooking up the aforementioned reset pin to the system reset line so that any system reset will reset the flash to 3-byte mode, but some packages do not provide this pin. And in some other packages, one must choose between having a reset pin and having enough pins for 4-output QSPI support. It is an error prone process choosing a flash that will support a hardware reset pin!) This patch provides support for the new stateless command set, so that we can avoid the problems that come with a stateful addressing mode change. The flash can be left in "3-byte mode" while still accessing the entire flash. Note that Spansion supports this command set on all its large flash (e.g, S25FL512S), and Macronix has begun supporting this command set on some new flash (e.g., MX25L25635F). For the moment, I don't know how to differentiate the Macronix that don't support this command set (e.g., MX25L25635E) from those that do, so this patch only supports Spansion. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-05mtd: m25p80: use spi_get_drvdata() and spi_set_drvdata()Jingoo Han
Use the wrapper functions for getting and setting the driver data using spi_device instead of using dev_{get|set}_drvdata with &spi->dev, so we can directly pass a struct spi_device. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-04-05mtd: m25p80: add entry for w25q128Rafał Miłecki
This device was reported over a year ago on OpenWrt mailing list in the thread [OpenWrt-Devel] RedBoot partition table with winbond m25q128vb (unfortunately, I can't find message id). Macpaul seemed to have problems with partition driver, but it seems the device was working OK. Reported-by: Macpaul Lin <macpaul@gmail.com> Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-04-05mtd: m25p80: add support for SST25VF064CKrzysztof Mazur
Signed-off-by: Krzysztof Mazur <krzysiek@podlesie.net> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-04-05mtd: m25p80: introduce SST_WRITE flag for SST byte programmingKrzysztof Mazur
Not all SST devices implement the SST byte programming command. Some devices (like SST25VF064C) implement only standard m25p80 page write command. Now SPI flash devices that need sst_write() are explicitly marked with new SST_WRITE flag and the decision to use sst_write() is based on this flag instead of manufacturer id. Signed-off-by: Krzysztof Mazur <krzysiek@podlesie.net> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-04-05mtd: m25p80: n25q064 is Micron, not Intel/NumonyxBrian Norris
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-04-05mtd: m25p80: add support for EON EN25QH256Daniel Schwierzeck
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-04-05mtd: m25p80: add support for Macronix MX66L51235LDaniel Schwierzeck
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-02-04mtd: chips: Add support for GigaDevice GD25Q32/GD25Q64 SPI Flash in m25p80.cMichel Stempin
Add support for GigaDevice GD25Q32 32 Mbit (4 MB) SPI Flash (see datasheet: http://www.gigadevice.com/UserFiles/GD25Q32_Rev0.2(1).pdf) used in Hame MPR-A1 and clones, and for GigaDevice GD25Q64 64 Mbit (8 MB) SPI Flash used in Hame MPR-A2 devices (datasheet: http://www.gigadevice.com/UserFiles/GD25Q64.pdf). Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2013-02-04mtd: m25p80: Flash protection support for STmicro chipsAustin Boyle
This patch adds generic support for flash protection on STmicro chips. On chips with less than 3 protection bits, the unused bits are don't cares and so can be written anyway. The lock function will only change the protection bits if it would not unlock other areas. Similarly, the unlock function will not lock currently unlocked areas. Tested on the m25p64. Signed-off-by: Austin Boyle <Austin.Boyle@aviatnet.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2012-12-03mtd: m25p80: modify info for Micron N25Q128Liming Wang
Micron N25Q128 has two types of flash: - One is for 1.8v supply voltage, prefixed with "n25q128a11" and the jedec code is 0x20bb18. - Another is for 3v supply voltage, prefixed with "n25q128a13" and the jedec code is 0x20ba18. So modify the original type info and add another type for Micron N25Q128. Signed-off-by: Liming Wang <walimisdev@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2012-11-22mtd: remove use of __devexitBill Pemberton
CONFIG_HOTPLUG is going away as an option so __devexit is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2012-11-22mtd: remove use of __devinitBill Pemberton
CONFIG_HOTPLUG is going away as an option so __devinit is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2012-11-22mtd: remove use of __devexit_pBill Pemberton
CONFIG_HOTPLUG is going away as an option so __devexit_p is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2012-11-22mtd: m25p80: add support for the Winbond w25q80bl chipStephen Warren
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2012-11-15mtd: m25p80: add support for the windbond w25q256 chipMatthieu CASTET
Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2012-11-15mtd: m25p80: Make fast read configurable via DTMarek Vasut
Add DT property "m25p,fast-read" that signalises the particular chip supports "fast read" opcode. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2012-09-29mtd: m25p80: Disable 4KiB erase for s25sl032p, s25sl064pMarek Vasut
Quoting from the datasheet for S25FL064P, rev. 05, Nov 18 2011, § 9.17: "A 64 kB[sic] sector erase (D8h) command issued on 4 kB or 8 kB erase sectors will erase all sectors in the specified 64 kB region. However, please note that a 4 kB sector erase (20h) or 8 kB sector erase (40h) command will not work on a 64 kB sector." Referring further to Table 8.1 and Table 8.2, it is clearly seen that most of the sectors are 64KiB; therefore disable this 4KiB erase support since it's valid only on first/last sectors. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: m25p80: add support for the EON EN25Q64 chipGabor Juhos
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: m25p80: add support for Micron N25Q128Jan Luebbe
Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: m25p80: add support for Micron N25Q256AVivien Didelot
The manufacturer datasheet can be found on the Micron website, under the name n25q_256mb_3v_65nm.pdf: http://www.micron.com/search?source=ps&q=n25q_256mb_3v_65nm Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: m25p80: Fix the Spansion chip detectionMarek Vasut
Due to the implementation of the following loop at the end of jedec_probe(): 776 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) { 777 info = (void *)m25p_ids[tmp].driver_data; 778 if (info->jedec_id == jedec) { 779 if (info->ext_id != 0 && info->ext_id != ext_jedec) 780 continue; 781 return &m25p_ids[tmp]; 782 } 783 } In particular line 779 in the above numbering, the chips with ext_id != 0 must be ordered first in the list of chips (m25p_ids[]). Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: m25p80: add support for Spansion s25sl064p chipMarek Vasut
Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-07-17mtd: m25p80: Add support for serial flash STM/Micron N25Q032Knut Wohlrab
Signed-off-by: Knut Wohlrab <knut.wohlrab@de.bosch.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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