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notifiers
Cpufreq driver must be unregistered/registered on switcher on/off to get correct
freq tables for all cpus. This patch does it.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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This patch adds IKS (In Kernel Switcher) support to cpufreq driver. This creates
separate freq table for A7-A15 cpu pair. A7 frequency is virtualized and is
halved, so that it touches boundaries with A7 frequencies.
Based on Earlier Work from Sudeep.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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cpufreq_stat has registered notifiers with both cpufreq and cpu core. It adds
cpu/cpu0/cpufreq/stats/ directory with a notifier of cpufreq CPUFREQ_NOTIFY and
removes this directory with a notifier to cpu core.
On bL_switcher enable/disable, cpufreq drivers notifiers gets called and they
call cpufreq_unregister(), followed by cpufreq_register(). For unregister stats
directories per cpu aren't removed, because cpu never went to dead state and cpu
notifier isn't called.
When cpufreq_register() is called, we try to add these directories again and
that simply fails, as directories were already present.
Fix these issues by registering cpufreq_stats too with bL_switcher notifiers, so
that they get unregistered and registered on switcher enable/disable.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Conflicts:
arch/arm/mach-vexpress/Makefile
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Conflicts:
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Vexpress depends on motherboard firmware + spc for getting opp table. This patch
adds Vexpress glue driver for ARM big LITTLE parent driver.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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This patch adds spc clock controller. In Vexpress cpu cluster clock is controlled via
spc controller and so it must be present in clk framework.
vexpress_clk_[of_]register_spc() registers cluster clocks with and without DT.
These are added as root clocks without any parents and their names are
"cluster[0|1|..]".
Now, platform must add clocks of all the cpus below these clusters. cpufreq
driver would get cpu clock and will do clk_get[set]_rate() on cpu clock, which
will then pass it to cluster clocks. And finally spc will get programmed.
This patch doesn't add non-DT clocks for clusters and cpus as i don't see a user
of that for now.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Using late_initcall is too late for IKS.
Requested-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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The low-level layer is now called "mcpm".
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Change the init code for cpuidle-tc2 to check for a
compatible node in the devicetree of "arm,generic"
in preparation for moving it to driver/cpuidle.
Rename functions / variable from tc2_ to bl_.
Signed-off-by: mark hambleton <mahamble@broadcom.com>
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This should be queued right before 'Revert "ARM: common: add GIC bybass disable
on GIC CPU IF save function"'.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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Move the private set_auxcr/get_auxcr functions from
drivers/cpuidle/cpuidle-calxeda.c so they can be used across platforms.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
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The TC2 versatile express core tile integrates a logic block that provides the
interface between the dual cluster test-chip and the M3 microcontroller that
carries out power management. The logic block, called Serial Power Controller
(SPC), contains several memory mapped registers to control among other things
low-power states, operating points and reset control.
This patch provides a driver that enables run-time control of features
implemented by the SPC control logic.
The driver also provides a bridge interface through the vexpress config
infrastructure. Operations allowing to read/write operating points are
made to go via the same interface as configuration transactions so that
all requests to M3 are serialized.
Device tree bindings documentation for the SPC component is provided with
the patchset.
Cc: Samuel Ortiz <sameo@linux.intel.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
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The introduction of Serial Power Controller (SPC) requires the vexpress
config interface to change slightly since the SPC memory mapped interface
can be used as configuration bus but also for operating points
programming and retrieval. The helper that allocates the bridge functions
requires an additional parameter allowing to request component specific
functions that need not be initialized through device tree bindings but
just using simple look-up and statically defined constants.
This patch introduces the necessary changes to the vexpress config layer
to cater for the new vexpress bridge interface requirements.
Cc: Samuel Ortiz <sameo@linux.intel.com>
Cc: Achin Gupta <achin.gupta@arm.com>
Cc: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
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CCI400 has a set of counters that can be used to profile different
transations at CCI master and slave interfaces. These counters can
observe different kinds of transations passing through the CCI and
provide a system-level view of activity.
This patch adds support for CCI PMU by extending the existing CCI
driver.
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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This is a hack to enable the old CCI PMU patches to be used with the new
CCI driver. The CCI PMU is (mis)represented by a separate node in TC2
device-tree.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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This provides cci_enable_port_for_self(). This is the counterpart to
cci_disable_port_by_cpu(self).
This is meant to be called from the MCPM machine specific power_up_setup
callback code when the appropriate affinity level needs to be initialized.
The code therefore has to be position independent as the MMU is still off
and it cannot rely on any stack space.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Dave Martin <dave.martin@linaro.org>
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On ARM multi-cluster systems coherency between cores running on
different clusters is managed by the cache-coherent interconnect (CCI).
It allows broadcasting of TLB invalidates and memory barriers and it
guarantees cache coherency at system level through snooping of slave
interfaces connected to it.
This patch enables the basic infrastructure required in Linux to handle and
programme the CCI component.
Non-local variables used by the CCI management functions called by power
down function calls after disabling the cache must be flushed out to main
memory in advance, otherwise incoherency of those values may occur if they
are sitting in the cache of some other CPU when power down functions
execute. Driver code ensures that relevant data structures are flushed
from inner and outer caches after the driver probe is completed.
CCI slave port resources are linked to set of CPUs through bus masters
phandle properties that link the interface resources to masters node in
the device tree.
Documentation describing the CCI DT bindings is provided with the patch.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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The patch removes a compiler warning when casting the ioaddr pointer to
(unsigned int) in the smc_probe() function of the smc91x.c driver. The
casting is now done to (unsigned long).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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The amba-clcd device can be configured to use either DMA or, when this
feature is not available, an ioremapped frambuffer in static ram.
In the case of the latter, we must take care not to pass ioremapped
addresses to dma_common_mmap, since this expects only addresses from
dma_mmap_coherent, which reside in the kernel linear mapping.
This patch reworks the fb initialisation code so that either DMA or IO
implementations of the mmap/remove functions are chosen as appropriate.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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This patch hides the dma_(alloc|free)_writecombine() calls behind macros
to allow the amba-clcd.c to be used on architectures that do not provide
this DMA API. With this patch, the *_writecombine() API is only used on
ARM (AArch32).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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This check was attempting to ensure only one clcd device in the
device-tree was probed, however the check fails in the valid case where
the device is a child of another device and the 'reg' value is a offset
from the start of that other device, not an absolute address. This
occurs on vexpress with the motherboard clcd being a child of iofga.
For now, we will just have to rely on there only being one display
device specified in device-tree.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Add support to parse the display configuration from device tree.
If the board does not provide platform specific functions in the struct
clcd_board contained with the amba device info, then defaults are provided
by the driver.
The device tree configuration can either ask for a DMA setup or provide a
framebuffer address to be remapped into the driver.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
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This reworks HDLCD initialisation to mirror how CLCD does this, in
particular to prepare the clock immediately after it has been got which
ensures that we don't try and enable clocks before they were prepared,
e.g. in the former clk_enable after register_framebuffer().
The reason this issue wasn't noticed before is that we have been
setting CONFIG_FRAMEBUFFER_CONSOLE and this caused
register_framebuffer() to trigger the creation of a console which calls
hdlcd_set_par(), which in turn was preparing and enabling the clock.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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This option can be used with Android to push the graphics subsystem into a
different composition strategy which is more effective when used on hardware
where the framebuffer memory is not cacheable.
Signed-off-by: Chris Redpath <chris.redpath@arm.com>
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Signed-off-by: Chris Redpath <chris.redpath@arm.com>
Reviewed-By: Liviu Dudau <liviu.dudau@arm.com>
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During TC2 integration a bad config option resulted in HDLCD memory reads
not being serviced often enough. This lead to unsightly screen blanking.
These options allow the developer to count the number of underruns and
to control the color used by HDLCD when an underrun prevents accessing
pixel data. The combination of these two options allow easy diagnosis
of HDLCD underrun conditions.
Signed-off-by: Chris Redpath <chris.redpath@arm.com>
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Change color byte location in 32-bit word from argb to abgr to match
the assumption made in Android when 32-bit color displays are used.
Signed-off-by: Chris Redpath <chris.redpath@arm.com>
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Add a shortcut when set_par is called to only change the yoffset. Android is
doing that instead of calling pan_display to flip the framebuffer.
Signed-off-by: Chris Redpath <chris.redpath@arm.com>
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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The ARM HDLCD device is now found in various new Versatile Express coretiles.
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
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The driver can be used on either arm or arm64 platforms, but
the latter doesn't have any platform-specific configuration
options, so it must be possible to manually enable the driver.
As the gpiolib is optional for arm64 arch, the gpio/led code
must be compiled conditionally.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
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The driver can be used on either arm or arm64 platforms, but
the latter doesn't have any platform-specific configuration
options, so it must be possible to manually enable the driver.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
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The new arm64 architecture has no idea of platform or machine, so
it doesn't have to define ARCH_VEXPRESS configuration option at
all. To allow user to select the drivers at all, make it depend
on ARM64 as well.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
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Previously all the clocks were reported as "osc". Now it will be
something like "/dcc/osc@0".
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
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The driver uses symbols from fbmem.c so if CONFIG_FB is not
selected we get build errors like:
drivers/built-in.o: In function `vexpress_dvi_fb_select':
:(.text+0x1b6c): undefined reference to `lock_fb_info'
:(.text+0x1ba0): undefined reference to `registered_fb'
Note, this is only a partial solution because we still have a
problem if CONFIG_FB is selected as a module.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Versatile Express' DVI video output can be connected to one the three
sources - motherboard's CLCD controller or a video signal generated
by one of the daughterboards.
This driver configures the muxer FPGA so the output displays content
of one of the framebuffers in the system (0 by default, can be changed
by user writing to the "fb" sysfs attribute of the muxfpga device).
It will also set up the display formatter mode and keep it up
to date with mode changes requested by the user (eg. with fbset
tool).
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
Pull SCSI fixes from James Bottomley:
"This is a set of seven bug fixes. Several fcoe fixes for locking
problems, initiator issues and a VLAN API change, all of which could
eventually lead to data corruption, one fix for a qla2xxx locking
problem which could lead to multiple completions of the same request
(and subsequent data corruption) and a use after free in the ipr
driver. Plus one minor MAINTAINERS file update"
(only six bugfixes in this pull, since I had already pulled the fcoe API
fix directly from Robert Love)
* tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi:
[SCSI] ipr: Avoid target_destroy accessing memory after it was freed
[SCSI] qla2xxx: Fix for locking issue between driver ISR and mailbox routines
MAINTAINERS: Fix fcoe mailing list
libfc: extend ex_lock to protect all of fc_seq_send
libfc: Correct check for initiator role
libfcoe: Fix Conflicting FCFs issue in the fabric
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