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Using late_initcall is too late for IKS.
Requested-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Conflicts:
arch/arm/mach-vexpress/Kconfig
arch/arm/mach-vexpress/Makefile
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The low-level layer is now called "mcpm".
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Change the init code for cpuidle-tc2 to check for a
compatible node in the devicetree of "arm,generic"
in preparation for moving it to driver/cpuidle.
Rename functions / variable from tc2_ to bl_.
Signed-off-by: mark hambleton <mahamble@broadcom.com>
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This should be queued right before 'Revert "ARM: common: add GIC bybass disable
on GIC CPU IF save function"'.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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All the calls to gic_secondary_init() pass 0 as the first argument.
Since this function is called on each CPU when starting, it can be done
in a platform-independent way via a CPU notifier registered by the GIC
code.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Tested-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
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Previously, the gic_handle_cascade_irq() function was calling the
ARM-specific do_bad_IRQ() function which calls handle_bad_irq() after
acquiring the desk->lock. Locking the cascaded IRQ desc is not needed
for error reporting, so just call handle_bad_irq() directly.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
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These functions have been introduced by commit 10a8c383 (irq: introduce
entry and exit functions for chained handlers) in asm/mach/irq.h. This
patch moves them to linux/irqchip/chained_irq.h so that generic irqchip
drivers do not rely on architecture specific header files.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
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This patch prepares the removal of <asm/mach/irq.h> include in the
GIC and VIC irqchip drivers.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
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Currently ARM_DT_BL_CPUFREQ gets enabled by default which causes a
kernel-oops on Arndale board. Forcing this to only when BIG_LITTLE is
enabled fixes following issue.
Unable to handle kernel paging request at virtual address ffffffd0
pgd = c0004000
[ffffffd0] *pgd=6f7fe821, *pte=00000000, *ppte=00000000
Internal error: Oops: 17 [#2] PREEMPT SMP THUMB2
Modules linked in:
CPU: 0 Tainted: G D (3.8.0-rc4+ #2)
PC is at kthread_data+0xa/0x10
LR is at wq_worker_sleeping+0xf/0xa4
pc : [<c0035726>] lr : [<c0032273>] psr: a00000b3
sp : ef0adb98 ip : 00000001 fp : ef0a6080
r10: c1bb7140 r9 : c05cd140 r8 : ef0ac000
r7 : ef0adbb8 r6 : ef0a6080 r5 : 00000000 r4 : b0000000
r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : ef0a6080
Flags: NzCv IRQs off FIQs on Mode SVC_32 ISA Thumb Segment user
Control: 50c5387d Table: 6e4c806a DAC: 55555555
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Throughout Linux code big LITTLE is written as "bL". We have used "bl" instead
of "bL". Lets fix it.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reported-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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This is already done by: cpufreq_frequency_table_cpuinfo()
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Some platforms might read frequency table from cluster nodes in DT, as they
might not have specific hardware for that. For them, this patch adds a generic
big LITTLE cpufreq driver.
Freqs passed from DT must be in KHz and DT node should be like:
cluster0: cluster@0 {
reg = <0>;
freqs = <500000 600000 700000 800000>;
}
cluster1: cluster@1 {
reg = <1>;
freqs = <900000 1000000 1100000 1200000>;
}
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Currently, we need to add entry for any new platform using this driver in
compatible list of arm_big_little.c driver. Which is not good.
Lets make this driver independent of slave drivers. Now, slave drivers would be
calling register routine of arm_big_little.c driver and would pass ops as
parameter.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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This adds pr_debugs at various places in driver to understand its behavior
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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We already have clock framework support for vexpress spc controller. So, no
longer need to call spc specific routines from arm_big_little driver.
Finally this driver is generic now, with zero dependency on vexpress.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Every platform have different way to get available frequencies from boot
loaders. Vexpress platform gets this information from SPC controller.
This patch separates out platform specific part for getting cpufreq table from
arm big LITTLE cpufreq driver. Every platform can pass this information from
their own stubs to this driver.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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This driver shouldn't have any dependency on Vexpress Platform and so can be
converted into generic big LITTLE platform's cpufreq driver. All dependencies
which are currently there would be removed by other patches.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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__cpufreq_driver_target() already validates the requested frequency
against the min and max bounds specified in the policy, so there is
to need to check it again.
This patch removes the bounds check from
vexpress_cpufreq_set_target().
Signed-off-by: Dave Martin <dave.martin@linaro.org>
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Signed-off-by: Dave Martin <dave.martin@linaro.org>
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As the SPC driver now take frequency as the input parameter for get/set
performance routines, change the cpufreq driver to reflect the same.
With this change Linux no longer rely on DT for freq -> perf index
mapping.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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The maximum size of a cpu_freq driver is CPUFREQ_NAME_LEN (16)
and the previous name was longer than this, leading to incorrect
output with:
$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_driver
Reported-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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The cpufreq driver requires SPC hardware, so check for its presence
before initialising the driver. This enables the cpufreq driver to
safely exist in kernels run on hardware without SPC support.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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If there are no CPU frequencies in the device tree for the current
cluster, then vexpress_cpufreq_of_init() passes a null pointer to
cpufreq_frequency_table_cpuinfo(), which it then dereferences.
This patch tests for this situation and cleanly returns and error
instead.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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This patch adds support for CPU frequency scaling on ARM vexpress based
big.LITTLE platforms. The driver reads the frequencies from the device tree.
This driver depends on Serial Power Controller(SPC) for setting operating
performance points(OPPs). Ensure that SPC driver is built to avoid run-time
errors.
To support big.LITTLE topology, the frequencies are read from FDT and
registered seperately per-cluster. To achieve this the CPU topology is
used to set the affected/related CPUs in terms of their OPP dependencies.
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
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clk-spc depends on spc and when spc is not present in DT (ex: on fast models),
we must not register clk-spc.
Signed-off-by: Mark Hambleton <mark.hambleton@broadcom.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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This patch adds spc clock controller. In Vexpress cpu cluster clock is controlled via
spc controller and so it must be present in clk framework.
vexpress_clk_[of_]register_spc() registers cluster clocks with and without DT.
These are added as root clocks without any parents and their names are
"cluster[0|1|..]".
Now, platform must add clocks of all the cpus below these clusters. cpufreq
driver would get cpu clock and will do clk_get[set]_rate() on cpu clock, which
will then pass it to cluster clocks. And finally spc will get programmed.
This patch doesn't add non-DT clocks for clusters and cpus as i don't see a user
of that for now.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Move the private set_auxcr/get_auxcr functions from
drivers/cpuidle/cpuidle-calxeda.c so they can be used across platforms.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
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SPC controller driver has already populated frequency table from firmware and
not its time to share it with other frameworks like: cpufreq. This patch
provides interface to get freq table from spc driver.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Not only the pointed data, but the pointer as well has to be flushed
out of the cache.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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vexpress_spc_check_loaded()
Even if it is initialized via early_INITCALL(), there are other pieces
of code that also have to be initialized with early_initcall() and
the relative call ordering may not always be satisfied.
So try to initialize the SPC code when vexpress_spc_check_loaded() is
called if that has not been done yet.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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Both SPC OPP and COMMS request takes ~3-5ms at max with CPU
wakeup enabled. The OPP change takes ~900us and COMMS ~200us if
wakeup are disabled. Since all the operations are serialised in the
firmware and CA7 wakeup takes ~2ms max, this could affect other SPC
request when they occur at the same time.
Further an SPC request could start just before jiffie is about to be
updated. In order to handle any of these cases, this patch changes
timeout value to 20ms.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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The latest firmware has the following protocol for PWC_STATUS update
to communicate status/faults:
CA15 DVFS request: 0x0001 complete, 0x0002 error
CA7 DVFS request: 0x0010 complete, 0x0020 error
SPC_SYS_CFG request: 0x0100 complete, 0x0200 error
This patch updates the driver to handle the error conditions based on
the above protocol.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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This patch changes the input parameter of spc_get/spc_set_perf
routines to frequency instead of performance index as expected
by the firmware. The SPC driver now has the list of frequencies
supported by the firmware, so it can map the requested frequency
to the right performance index.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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This patch adds support to read the SPC virtual registers that store
the OPPs through SYS_CFG interface. This helps in avoiding to rely on
DT for frequency to performanace index as expected by firmware.
It can also be used to get other information from the firware.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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In order to compare the given cluster id with A15, the A15_CONF is read
everytime. Instead read the A15 cluster id once during initialisation
and store the same for all future references.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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The SCC/SPC offsets defined in spc driver are scattered a bit.
Just reordering them for better readability.
Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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This patch initializes the SPC driver before smp initialization is done.
The driver is required to be able to use the power api to bring up
secondary cpus. Hence its availability is mandatory at this stage.
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This patch ensures that the SPC registers written by the power api
are read back to ensure that the changes have reflected. This is
done to workaround any delays caused by the slow nature of the SPC
interface e.g. the wfi signal being asserted to the SPC before the
changes to the SPC registers have taken effect.
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Otherwise any concurrent call could reset the completion block
while it is being waited for by a previous call.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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Picked wholesale in the IKS tree from ARM.
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Non-local variables used by the CCI and SPC management functions
called by tc2_pm_power_down() after disabling the cache must be
flushed out to main memory in advance, otherwise incoherency of
those values may occur if they are sitting in the cache of some
other CPU when tc2_pm_power_down() executes.
This patch adds the appropriate flushing to the CCI and SPC drivers
to ensure that the relevant data is available in RAM ahead of time.
Because this creates a dependency on arch-specific cacheflushing
functions, this patch also makes ARM_CCI and ARM_SPC depend on ARM
(pending a proper tidyup of those drivers).
Signed-off-by: Dave Martin <dave.martin@linaro.org>
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