From 14c58eb64503ece63d442904b4383f7b2ff3763d Mon Sep 17 00:00:00 2001 From: Show Liu Date: Thu, 14 Aug 2014 23:56:19 +0800 Subject: mali r4p0: adjust the mali r4p0 config parameters for arndale octa board --- arch/arm/boot/dts/exynos5420.dtsi | 6 +- arch/arm/mach-exynos/include/mach/asv-5250.h | 21 + arch/arm/mach-exynos/include/mach/asv-exynos.h | 127 ++++ arch/arm/mach-exynos/include/mach/asv-exynos542x.h | 687 +++++++++++++++++++++ arch/arm/mach-exynos/include/mach/pmu.h | 36 ++ arch/arm/plat-samsung/include/plat/cpu.h | 13 + drivers/gpu/arm/midgard/mali_kbase_context.c | 4 + drivers/gpu/arm/midgard/mali_kbase_device.c | 26 + drivers/gpu/arm/midgard/mali_kbase_jm.c | 2 +- drivers/gpu/arm/midgard/mali_kbase_js_policy_cfs.c | 6 +- drivers/gpu/arm/midgard/mali_kbase_mem.h | 1 + drivers/gpu/arm/midgard/mali_kbase_pm.h | 20 + drivers/gpu/arm/midgard/mali_kbase_pm_metrics.c | 40 ++ .../arndale_octa/mali_kbase_config_arndale_octa.c | 641 +++++++------------ include/dt-bindings/clock/exynos5420.h | 6 +- 15 files changed, 1204 insertions(+), 432 deletions(-) create mode 100644 arch/arm/mach-exynos/include/mach/asv-5250.h create mode 100644 arch/arm/mach-exynos/include/mach/asv-exynos.h create mode 100644 arch/arm/mach-exynos/include/mach/asv-exynos542x.h create mode 100644 arch/arm/mach-exynos/include/mach/pmu.h diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 8e99992cdea..77580cfe5d3 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -641,12 +641,12 @@ }; mali { - compatible = "arm,malit6xx"; + compatible = "arm,mali-midgard"; reg = <0x11800000 0x5000>; interrupts = <0 219 0>, <0 74 0>, <0 117 0>; interrupt-names = "JOB", "MMU", "GPU"; - clocks = <&clock 501>, <&clock 500>; - clock-names = "g3d", "aclk_g3d"; + clocks = <&clock 501>, <&clock 641>, <&clock 642>, <&clock 1>, <&clock 9>; + clock-names = "g3d", "aclk_g3d", "mout_vpll", "ext_xtal", "fout_vpll"; }; hdmi@14530000 { diff --git a/arch/arm/mach-exynos/include/mach/asv-5250.h b/arch/arm/mach-exynos/include/mach/asv-5250.h new file mode 100644 index 00000000000..3c57f5e6b9e --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/asv-5250.h @@ -0,0 +1,21 @@ +/* linux/arch/arm/mach-exynos/include/mach/asv-5250.h + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS5 - ASV support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_ASV_H +#define __ASM_ARCH_ASV_H __FILE__ + +extern unsigned int exynos_result_of_asv; +extern unsigned int exynos_result_mif_asv; +extern bool exynos_lot_id; +extern bool exynos_lot_is_nzvpu; + +#endif /* __ASM_ARCH_ASV_H */ diff --git a/arch/arm/mach-exynos/include/mach/asv-exynos.h b/arch/arm/mach-exynos/include/mach/asv-exynos.h new file mode 100644 index 00000000000..1084c54b9af --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/asv-exynos.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2013 Samsung Electronics co., ltd. + * http://www.samsung.com/ + * + * EXYNOS5 - Adaptive Supply Voltage Header File + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. +*/ + +#ifndef __ASM_ARCH_NEW_ASV_H +#define __ASM_ARCH_NEW_ASV_H + +#define ASV_GRP_NR(_id) _id##_ASV_GRP_NR +#define DVFS_LEVEL_NR(_id) _id##_DVFS_LEVEL_NR +#define MAX_VOLT(_id) _id##_MAX_VOLT +#define MAX_VOLT_VER(_id, _ver) _id##_MAX_VOLT_##_ver + +#define ABB_X060 0 +#define ABB_X065 1 +#define ABB_X070 2 +#define ABB_X075 3 +#define ABB_X080 4 +#define ABB_X085 5 +#define ABB_X090 6 +#define ABB_X095 7 +#define ABB_X100 8 +#define ABB_X105 9 +#define ABB_X110 10 +#define ABB_X115 11 +#define ABB_X120 12 +#define ABB_X125 13 +#define ABB_X130 14 +#define ABB_X135 15 +#define ABB_X140 16 +#define ABB_X145 17 +#define ABB_X150 18 +#define ABB_X155 19 +#define ABB_X160 20 +#define ABB_BYPASS 255 + +#define ABB_INIT 0x80000080 +#define ABB_INIT_BYPASS 0x80000000 +#define LOT_ID_LEN 5 + +static inline void set_abb(void __iomem *target_reg, unsigned int target_value) +{ + unsigned int tmp; + + if (target_value == ABB_BYPASS) + tmp = ABB_INIT_BYPASS; + else + tmp = (ABB_INIT | target_value); + + __raw_writel(tmp , target_reg); +} + +enum asv_type_id { + ID_ARM, + ID_KFC, + ID_INT, + ID_MIF, + ID_G3D, + ID_MIF_SRAM, + ID_G3D_SRAM, +}; + +/* define Struct for ASV common */ +struct asv_common { + char lot_name[LOT_ID_LEN]; + unsigned int ids_value; + unsigned int hpm_value; + unsigned int (*init)(void); + unsigned int (*register_asv_member)(void); +}; + +struct asv_freq_table { + unsigned int asv_freq; + unsigned int asv_value; +}; + +/* define struct for information of each ASV type */ +struct asv_info { + struct list_head node; + enum asv_type_id asv_type; + const char *name; + const struct asv_ops *ops; + unsigned int asv_group_nr; + unsigned int dvfs_level_nr; + unsigned int result_asv_grp; + unsigned int max_volt_value; + struct asv_freq_table *asv_volt; + struct asv_freq_table *asv_abb; + struct abb_common *abb_info; +}; + +/* Struct for ABB function */ +struct abb_common { + unsigned int target_abb; + void (*set_target_abb)(struct asv_info *asv_inform); +}; + +/* Operation for ASV*/ +struct asv_ops { + unsigned int (*get_asv_group)(struct asv_common *asv_comm, + enum asv_type_id asv_type); + unsigned int (*set_asv_info)(struct asv_info *asv_inform, + bool show_value); +}; + +/* define function for common asv */ +extern void exynos_add_asv_member(struct asv_info *exynos_asv_info); +extern struct asv_info *asv_get(enum asv_type_id exynos_asv_type_id); +extern int exynos_asv_group_get(enum asv_type_id asv_type_id); +extern unsigned int get_match_volt(enum asv_type_id target_type, + unsigned int target_freq); +extern unsigned int get_match_abb(enum asv_type_id target_type, + unsigned int target_freq); +extern unsigned int set_match_abb(enum asv_type_id target_type, + unsigned int target_abb); +/* define function for initialize of SoC */ +extern int exynos542x_init_asv(struct asv_common *asv_info); + +extern bool exynos5420_is_g3d_mp6(void); + +#endif /* __ASM_ARCH_NEW_ASV_H */ diff --git a/arch/arm/mach-exynos/include/mach/asv-exynos542x.h b/arch/arm/mach-exynos/include/mach/asv-exynos542x.h new file mode 100644 index 00000000000..7261e806b9b --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/asv-exynos542x.h @@ -0,0 +1,687 @@ +/* + * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS542X - Adaptive Supply Voltage Header file + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_EXYNOS542X_ASV_H +#define __ASM_ARCH_EXYNOS542X_ASV_H + +#include + +#define EXYNOS542X_MAX_ASV_GRP_NR 15 +#define EXYNOS5420_MAX_ASV_GRP_NR 15 +#define EXYNOS5422_MAX_ASV_GRP_NR 14 + +#define EXYNOS5420_ARM_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5420_arm_asv_volt_info) +#define EXYNOS5420_ARM_MAX_VOLT 1362500 + +#define EXYNOS5420_KFC_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5420_kfc_asv_volt_info) +#define EXYNOS5420_KFC_MAX_VOLT 1312500 + +#define EXYNOS5420_G3D_MP4_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5420_g3d_mp4_asv_volt_info) +#define EXYNOS5420_G3D_MP4_MAX_VOLT 1150000 + +#define EXYNOS5420_G3D_MP6_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5420_g3d_mp6_asv_volt_info) +#define EXYNOS5420_G3D_MP6_MAX_VOLT 1200000 + +#define EXYNOS5420_INT_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5420_int_asv_volt_info) +#define EXYNOS5420_INT_MAX_VOLT 1212500 + +#define EXYNOS5420_MIF_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5420_mif_asv_volt_info) +#define EXYNOS5420_MIF_MAX_VOLT 1050000 + +#define EXYNOS5420_MIF_SRAM_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5420_mif_sram_asv_volt_info) +#define EXYNOS5420_MIF_SRAM_MAX_VOLT 1050000 + +#define EXYNOS5420_G3D_MP4_SRAM_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5420_g3d_mp4_sram_asv_volt_info) +#define EXYNOS5420_G3D_MP4_SRAM_MAX_VOLT 1050000 + +#define EXYNOS5420_G3D_MP6_SRAM_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5420_g3d_mp6_sram_asv_volt_info) +#define EXYNOS5420_G3D_MP6_SRAM_MAX_VOLT 1200000 + +#define EXYNOS5422_ARM_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5422_arm_asv_volt_info) +#define EXYNOS5422_ARM_MAX_VOLT 1362500 + +#define EXYNOS5422_KFC_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5422_kfc_asv_volt_info) +#define EXYNOS5422_KFC_MAX_VOLT 1300000 + +#define EXYNOS5422_G3D_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5422_g3d_asv_volt_info) +#define EXYNOS5422_G3D_MAX_VOLT 1025000 + +#define EXYNOS5422_INT_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5422_int_asv_volt_info) +#define EXYNOS5422_INT_MAX_VOLT 1025000 + +#define EXYNOS5422_MIF_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5422_mif_asv_volt_info) +#define EXYNOS5422_MIF_MAX_VOLT 1000000 + +#define EXYNOS5422_MIF_SRAM_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5422_mif_sram_asv_volt_info) +#define EXYNOS5422_MIF_SRAM_MAX_VOLT 1000000 + +#define EXYNOS5422_G3D_SRAM_DVFS_LEVEL_NR \ + ARRAY_SIZE(exynos5422_g3d_sram_asv_volt_info) +#define EXYNOS5422_G3D_SRAM_MAX_VOLT 1025000 + +static const unsigned int +exynos5420_refer_table_get_asv[2][EXYNOS542X_MAX_ASV_GRP_NR] = { + { 0, 11, 15, 20, 24, 29, 36, 43, 52, 63, 76, 91, 100, 110, 999 }, + { 0, 65, 69, 72, 74, 76, 78, 80, 82, 84, 87, 89, 91, 92, 999 }, +}; + +static const unsigned int +exynos5420_refer_use_table_get_asv[2][EXYNOS542X_MAX_ASV_GRP_NR] = { + { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }, + { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }, +}; + +static const unsigned int +exynos5420_arm_asv_abb_info[EXYNOS542X_MAX_ASV_GRP_NR] = { + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, +}; + +static const unsigned int +exynos5420_kfc_asv_abb_info[EXYNOS542X_MAX_ASV_GRP_NR] = { + ABB_X080, ABB_X080, ABB_X080, ABB_X080, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, +}; + +static const unsigned int +exynos5420_g3d_mp4_asv_abb_info[EXYNOS542X_MAX_ASV_GRP_NR] = { + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, +}; + +static const unsigned int +exynos5420_g3d_mp6_asv_abb_info[EXYNOS542X_MAX_ASV_GRP_NR] = { + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, +}; + +static const unsigned int +exynos5420_int_asv_abb_info[EXYNOS542X_MAX_ASV_GRP_NR] = { + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, +}; + +static const unsigned int +exynos5420_mif_asv_abb_info[EXYNOS542X_MAX_ASV_GRP_NR] = { + ABB_X130, ABB_X130, ABB_X130, ABB_X130, ABB_X130, + ABB_X130, ABB_X130, ABB_X130, ABB_X130, ABB_X130, + ABB_X130, ABB_X130, ABB_X130, ABB_X130, ABB_X130, +}; + +static const unsigned int exynos5420_arm_asv_volt_info +[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 2000000, + 1362500, 1350000, 1337500, 1325000, 1312500, + 1325000, 1312500, 1300000, 1287500, 1262500, + 1237500, 1237500, 1225000, 1212500, 1200000 }, + { 1900000, + 1300000, 1287500, 1262500, 1237500, 1225000, + 1212500, 1200000, 1187500, 1175000, 1162500, + 1150000, 1137500, 1125000, 1112500, 1112500 }, + { 1800000, + 1250000, 1250000, 1225000, 1212500, 1200000, + 1187500, 1175000, 1162500, 1150000, 1137500, + 1125000, 1112500, 1100000, 1087500, 1087500 }, + { 1700000, + 1212500, 1212500, 1187500, 1175000, 1162500, + 1150000, 1137500, 1125000, 1112500, 1100000, + 1087500, 1075000, 1062500, 1050000, 1050000 }, + { 1600000, + 1175000, 1175000, 1150000, 1137500, 1125000, + 1112500, 1100000, 1087500, 1075000, 1062500, + 1050000, 1037500, 1025000, 1012500, 1012500 }, + { 1500000, + 1137500, 1137500, 1112500, 1100000, 1087500, + 1075000, 1062500, 1050000, 1037500, 1025000, + 1012500, 1000000, 987500, 975000, 975000 }, + { 1400000, + 1112500, 1112500, 1087500, 1075000, 1062500, + 1050000, 1037500, 1025000, 1012500, 1000000, + 987500, 975000, 962500, 950000, 950000 }, + { 1300000, + 1062500, 1062500, 1037500, 1025000, 1012500, + 1000000, 987500, 975000, 962500, 950000, + 937500, 925000, 912500, 900000, 900000 }, + { 1200000, + 1037500, 1037500, 1012500, 1000000, 987500, + 975000, 962500, 950000, 937500, 925000, + 912500, 900000, 900000, 900000, 900000 }, + { 1100000, + 1012500, 1012500, 987500, 975000, 962500, + 950000, 937500, 925000, 912500, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 1000000, + 987500, 987500, 962500, 950000, 937500, + 925000, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 900000, + 962500, 962500, 937500, 925000, 912500, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 800000, + 937500, 937500, 912500, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 700000, + 912500, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 600000, + 912500, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 500000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 400000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 300000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 200000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, +}; + +static const unsigned int exynos5420_kfc_asv_volt_info +[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 1300000, + 1275000, 1262500, 1250000, 1237500, 1237500, + 1225000, 1212500, 1200000, 1187500, 1175000, + 1162500, 1150000, 1137500, 1125000, 1125000 }, + { 1200000, + 1212500, 1200000, 1187500, 1175000, 1175000, + 1162500, 1150000, 1137500, 1125000, 1112500, + 1100000, 1087500, 1075000, 1075000, 1075000 }, + { 1100000, + 1162500, 1150000, 1137500, 1125000, 1125000, + 1112500, 1100000, 1087500, 1075000, 1062500, + 1050000, 1037500, 1025000, 1025000, 1025000 }, + { 1000000, + 1112500, 1100000, 1087500, 1075000, 1075000, + 1062500, 1050000, 1037500, 1025000, 1012500, + 1000000, 987500, 975000, 975000, 975000 }, + { 900000, + 1062500, 1050000, 1037500, 1025000, 1025000, + 1012500, 1000000, 987500, 975000, 962500, + 950000, 937500, 925000, 925000, 925000 }, + { 800000, + 1025000, 1012500, 1000000, 987500, 987500, + 975000, 962500, 950000, 937500, 925000, + 912500, 912500, 912500, 912500, 912500 }, + { 700000, + 975000, 962500, 950000, 937500, 937500, + 925000, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 600000, + 937500, 925000, 912500, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 500000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 400000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 300000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 200000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, +}; + +static const unsigned int exynos5420_g3d_mp4_asv_volt_info +[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 600000, + 1025000, 1012500, 1000000, 987500, 975000, + 962500, 950000, 937500, 925000, 912500, + 900000, 887500, 875000, 862500, 850000 }, + { 533000, + 987500, 975000, 962500, 950000, 937500, + 925000, 912500, 900000, 887500, 875000, + 862500, 850000, 837500, 825000, 825000 }, + { 480000, + 950000, 937500, 925000, 912500, 900000, + 887500, 875000, 862500, 850000, 837500, + 825000, 812500, 812500, 812500, 812500 }, + { 420000, + 937500, 925000, 912500, 900000, 887500, + 875000, 862500, 850000, 837500, 825000, + 812500, 800000, 800000, 800000, 800000 }, + { 350000, + 900000, 887500, 875000, 862500, 850000, + 837500, 825000, 812500, 800000, 800000, + 800000, 800000, 800000, 800000, 800000 }, + { 266000, + 862500, 850000, 837500, 825000, 825000, + 812500, 800000, 800000, 800000, 800000, + 800000, 800000, 800000, 800000, 800000 }, + { 177000, + 862500, 850000, 837500, 825000, 825000, + 812500, 800000, 800000, 800000, 800000, + 800000, 800000, 800000, 800000, 800000 }, + { 100000, + 862500, 850000, 837500, 825000, 825000, + 812500, 800000, 800000, 800000, 800000, + 800000, 800000, 800000, 800000, 800000 }, +}; + +static const unsigned int exynos5420_g3d_mp6_asv_volt_info +[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 533000, + 1062500, 1050000, 1037500, 1025000, 1012500, + 1000000, 987500, 975000, 962500, 950000, + 937500, 925000, 912500, 900000, 900000 }, + { 480000, + 1025000, 1012500, 1000000, 987500, 975000, + 962500, 950000, 937500, 925000, 912500, + 900000, 887500, 875000, 862500, 862500 }, + { 420000, + 987500, 975000, 962500, 950000, 937500, + 925000, 912500, 900000, 887500, 875000, + 862500, 850000, 837500, 825000, 825000 }, + { 350000, + 937500, 925000, 912500, 900000, 887500, + 875000, 862500, 850000, 837500, 825000, + 812500, 800000, 800000, 800000, 800000 }, + { 266000, + 887500, 875000, 862500, 850000, 837500, + 825000, 812500, 800000, 800000, 800000, + 800000, 800000, 800000, 800000, 800000 }, + { 177000, + 850000, 837500, 825000, 812500, 800000, + 800000, 800000, 800000, 800000, 800000, + 800000, 800000, 800000, 800000, 800000 }, + { 100000, + 850000, 837500, 825000, 812500, 800000, + 800000, 800000, 800000, 800000, 800000, + 800000, 800000, 800000, 800000, 800000 }, +}; + +static const unsigned int exynos5420_int_asv_volt_info +[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 600000, + 1025000, 1012500, 1000000, 987500, 975000, + 962500, 950000, 962500, 950000, 937500, + 925000, 912500, 900000, 900000, 900000 }, + { 500000, + 962500, 950000, 937500, 925000, 912500, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000 }, + { 400000, + 950000, 937500, 925000, 912500, 912500, + 912500, 912500, 912500, 900000, 887500, + 875000, 862500, 862500, 862500, 862500 }, + { 333000, + 912500, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 887500, 875000, + 862500, 850000, 850000, 850000, 850000 }, + { 222000, + 912500, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 887500, 875000, + 862500, 850000, 850000, 850000, 850000 }, + { 111000, + 912500, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 887500, 875000, + 862500, 850000, 850000, 850000, 850000 }, + { 83000, + 912500, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 887500, 875000, + 862500, 850000, 850000, 850000, 850000 }, +}; + +static const unsigned int +exynos5420_mif_asv_volt_info[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 0, + 1000000, 1000000, 1000000, 1000000, 1000000, + 1000000, 1000000, 1000000, 1000000, 1000000, + 1000000, 1000000, 1000000, 1000000, 1000000 }, +}; + +static const unsigned int +exynos5420_mif_sram_asv_volt_info[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 0, + 1000000, 1000000, 1000000, 1000000, 1000000, + 1000000, 1000000, 1000000, 1000000, 1000000, + 1000000, 1000000, 1000000, 1000000, 1000000 }, +}; + +static const unsigned int +exynos5420_g3d_mp4_sram_asv_volt_info[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 0, + 1025000, 1025000, 1000000, 1000000, 975000, + 975000, 950000, 950000, 925000, 925000, + 900000, 900000, 900000, 900000, 900000 }, +}; + +static const unsigned int +exynos5420_g3d_mp6_sram_asv_volt_info[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 0, + 1075000, 1050000, 1050000, 1025000, 1025000, + 1000000, 1000000, 975000, 975000, 950000, + 950000, 925000, 925000, 900000, 900000 }, +}; + +static const unsigned int +exynos5422_refer_table_get_asv[2][EXYNOS542X_MAX_ASV_GRP_NR] = { + { 13, 21, 25, 30, 36, 43, 51, 65, 81, 98, 119, 135, 150, 999}, + { 55, 65, 69, 72, 74, 76, 78, 80, 82, 84, 87, 89, 92, 999}, +}; + +static const unsigned int +exynos5422_refer_use_table_get_asv[2][EXYNOS542X_MAX_ASV_GRP_NR] = { + { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, + { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, +}; + +static const unsigned int +exynos5422_arm_asv_abb_info[EXYNOS542X_MAX_ASV_GRP_NR] = { + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, +}; + +static const unsigned int +exynos5422_int_asv_abb_info[EXYNOS542X_MAX_ASV_GRP_NR] = { + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_X130, + ABB_X130, ABB_X130, ABB_X130, ABB_X130, +}; + +static const unsigned int +exynos5422_mif_asv_abb_info[EXYNOS542X_MAX_ASV_GRP_NR] = { + ABB_X130, ABB_X130, ABB_X130, ABB_X130, ABB_X130, + ABB_X130, ABB_X130, ABB_X130, ABB_X130, ABB_X130, + ABB_X130, ABB_X130, ABB_X130, ABB_X130, +}; + +static const unsigned int +exynos5422_g3d_asv_abb_info[EXYNOS542X_MAX_ASV_GRP_NR] = { + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, +}; + +static const unsigned int +exynos5422_kfc_asv_abb_info[EXYNOS542X_MAX_ASV_GRP_NR] = { + ABB_X070, ABB_X070, ABB_X070, ABB_X080, ABB_X080, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, + ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, ABB_BYPASS, +}; + +static const unsigned int exynos5422_arm_asv_volt_info +[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 2100000, + 1350000, 1350000, 1350000, 1350000, 1350000, + 1337500, 1325000, 1312500, 1300000, 1287500, + 1275000, 1262500, 1250000, 1237500 }, + { 2000000, + 1312500, 1312500, 1312500, 1300000, 1287500, + 1275000, 1262500, 1250000, 1237500, 1225000, + 1212500, 1200000, 1187500, 1175000 }, + { 1900000, + 1275000, 1262500, 1250000, 1237500, 1225000, + 1212500, 1200000, 1187500, 1175000, 1162500, + 1150000, 1137500, 1125000, 1112500 }, + { 1800000, + 1225000, 1212500, 1200000, 1187500, 1175000, + 1162500, 1150000, 1137500, 1125000, 1112500, + 1100000, 1087500, 1075000, 1062500 }, + { 1700000, + 1187500, 1175000, 1162500, 1150000, 1137500, + 1125000, 1112500, 1100000, 1087500, 1075000, + 1062500, 1050000, 1037500, 1025000 }, + { 1600000, + 1150000, 1137500, 1125000, 1112500, 1100000, + 1087500, 1075000, 1062500, 1050000, 1037500, + 1025000, 1012500, 1000000, 987500 }, + { 1500000, + 1112500, 1100000, 1087500, 1075000, 1062500, + 1050000, 1037500, 1025000, 1012500, 1000000, + 987500, 975000, 962500, 950000 }, + { 1400000, + 1087500, 1075000, 1062500, 1050000, 1037500, + 1025000, 1012500, 1000000, 987500, 975000, + 962500, 950000, 937500, 925000 }, + { 1300000, + 1062500, 1050000, 1037500, 1025000, 1012500, + 1000000, 987500, 975000, 962500, 950000, + 937500, 925000, 912500, 900000 }, + { 1200000, + 1037500, 1025000, 1012500, 1000000, 987500, + 975000, 962500, 950000, 937500, 925000, + 912500, 900000, 900000, 900000 }, + { 1100000, + 1012500, 1000000, 987500, 975000, 962500, + 950000, 937500, 925000, 912500, 900000, + 900000, 900000, 900000, 900000 }, + { 1000000, + 987500, 975000, 962500, 950000, 937500, + 925000, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 900000 }, + { 900000, + 962500, 950000, 937500, 925000, 912500, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000 }, + { 800000, + 937500, 925000, 912500, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000 }, + { 700000, + 912500, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000 }, + { 600000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000 }, + { 500000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000 }, + { 400000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000 }, + { 300000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000 }, + { 200000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000 }, +}; + +static const unsigned int exynos5422_kfc_asv_volt_info +[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 1500000, + 1300000, 1300000, 1300000, 1300000, 1300000, + 1300000, 1287500, 1275000, 1262500, 1250000, + 1237500, 1222500, 1212500, 1200000 }, + { 1400000, + 1287500, 1275000, 1262500, 1250000, 1237500, + 1225000, 1212500, 1200000, 1187500, 1175000, + 1162500, 1150000, 1137500, 1125000 }, + { 1300000, + 1237500, 1225000, 1212500, 1200000, 1187500, + 1175000, 1162500, 1150000, 1137500, 1125000, + 1112500, 1100000, 1087500, 1075000 }, + { 1200000, + 1187500, 1175000, 1162500, 1150000, 1137500, + 1125000, 1112500, 1100000, 1087500, 1075000, + 1062500, 1050000, 1037500, 1025000 }, + { 1100000, + 1150000, 1137500, 1125000, 1112500, 1100000, + 1087500, 1075000, 1062500, 1050000, 1037500, + 1025000, 1012500, 1000000, 987500 }, + { 1000000, + 1112500, 1100000, 1087500, 1075000, 1062500, + 1050000, 1037500, 1025000, 1012500, 1000000, + 987500, 975000, 962500, 950000 }, + { 900000, + 1075000, 1062500, 1050000, 1037500, 1025000, + 1012500, 1000000, 987500, 975000, 962500, + 950000, 937500, 925000, 912500 }, + { 800000, + 1037500, 1025000, 1012500, 1000000, 987500, + 975000, 962500, 950000, 937500, 925000, + 912500, 900000, 900000, 900000 }, + { 700000, + 1000000, 987500, 975000, 962500, 950000, + 937500, 925000, 912500, 900000, 900000, + 900000, 900000, 900000, 900000 }, + { 600000, + 962500, 950000, 937500, 925000, 912500, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000 }, + { 500000, + 925000, 912500, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000 }, + { 400000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000 }, + { 300000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000 }, + { 200000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000, 900000, + 900000, 900000, 900000, 900000 }, +}; + +/* + * DVFS V2.40 table for 5422 supports INT levels upto 420MHz. The 500MHz + * level has the 420MHz INT bus level voltages and will stay disabled till + * we enabled 2.1GHz support which requires a locking to the 420MHz level. + */ +static const unsigned int exynos5422_int_asv_volt_info +[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 600000, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0 }, + { 500000, + 1075000, 1062500, 1050000, 1037500, 1025000, + 1012500, 1000000, 987500, 975000, 987500, + 975000, 962500, 950000, 937500 }, + { 400000, + 962500, 950000, 937500, 925000, 912500, + 900000, 887500, 887500, 887500, 875000, + 887500, 875000, 862500, 850000 }, + { 333000, + 925000, 912500, 900000, 887500, 875000, + 862500, 850000, 850000, 850000, 850000, + 850000, 850000, 850000, 850000 }, + { 222000, + 900000, 887500, 875000, 862500, 850000, + 850000, 850000, 850000, 850000, 850000, + 850000, 850000, 850000, 850000 }, + { 111000, + 900000, 887500, 875000, 862500, 850000, + 850000, 850000, 850000, 850000, 850000, + 850000, 850000, 850000, 850000 }, + { 83000, + 850000, 850000, 850000, 850000, 850000, + 850000, 850000, 850000, 850000, 850000, + 850000, 850000, 850000, 850000 }, +}; + +static const unsigned int exynos5422_mif_asv_volt_info +[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 0, + 1000000, 1000000, 1000000, 1000000, 1000000, + 1000000, 1000000, 1000000, 1000000, 1000000, + 1000000, 1000000, 1000000, 1000000 }, +}; + +static const unsigned int exynos5422_g3d_asv_volt_info +[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 543000, + 1025000, 1012500, 1000000, 987500, 975000, + 962500, 950000, 937500, 925000, 912500, + 900000, 887500, 875000, 862500 }, + { 480000, + 975000, 962500, 950000, 937500, 925000, + 912500, 900000, 887500, 875000, 862500, + 850000, 837500, 825000, 812500 }, + { 420000, + 937500, 925000, 912500, 900000, 887500, + 875000, 862500, 850000, 837500, 825000, + 812500, 800000, 787500, 775000 }, + { 350000, + 912500, 900000, 887500, 875000, 862500, + 850000, 837500, 825000, 812500, 800000, + 787500, 775000, 775000, 775000 }, + { 266000, + 887500, 875000, 862500, 850000, 837500, + 825000, 812500, 800000, 787500, 775000, + 775000, 775000, 775000, 775000 }, + { 177000, + 825000, 812500, 800000, 787500, 775000, + 775000, 775000, 775000, 775000, 775000, + 775000, 775000, 775000, 775000 }, + { 100000, + 825000, 812500, 800000, 787500, 775000, + 775000, 775000, 775000, 775000, 775000, + 775000, 775000, 775000, 775000 }, +}; + +static const unsigned int +exynos5422_mif_sram_asv_volt_info[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 0, + 1000000, 1000000, 1000000, 1000000, 1000000, + 1000000, 1000000, 1000000, 1000000, 1000000, + 1000000, 1000000, 1000000, 1000000 }, +}; + +static const unsigned int +exynos5422_g3d_sram_asv_volt_info[][EXYNOS542X_MAX_ASV_GRP_NR + 1] = { + { 0, + 1025000, 1025000, 1000000, 1000000, 975000, + 975000, 950000, 950000, 925000, 925000, + 900000, 900000, 900000, 900000 }, +}; + +#endif /* EXYNOS542X_ASV_H */ diff --git a/arch/arm/mach-exynos/include/mach/pmu.h b/arch/arm/mach-exynos/include/mach/pmu.h new file mode 100644 index 00000000000..b2ecd902f61 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/pmu.h @@ -0,0 +1,36 @@ +/* linux/arch/arm/mach-exynos4/include/mach/pmu.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS4210 - PMU(Power Management Unit) support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_PMU_H +#define __ASM_ARCH_PMU_H __FILE__ + +#define PMU_TABLE_END NULL + +enum sys_powerdown { + SYS_AFTR, + SYS_LPA, + SYS_SLEEP, + NUM_SYS_POWERDOWN, +}; + +extern unsigned long l2x0_regs_phys; +struct exynos_pmu_conf { + void __iomem *reg; + unsigned int val[NUM_SYS_POWERDOWN]; +}; + +extern unsigned long s5p_resume_cpu_id; + +extern void exynos_sys_powerdown_conf(enum sys_powerdown mode); +extern void s3c_cpu_resume(void); + +#endif /* __ASM_ARCH_PMU_H */ diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 335beb34135..ff64dbce2af 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -47,6 +47,7 @@ extern unsigned long samsung_cpu_id; #define EXYNOS5250_SOC_ID 0x43520000 #define EXYNOS5420_SOC_ID 0xE5420000 +#define EXYNOS5422_SOC_ID 0xE5422000 #define EXYNOS5440_SOC_ID 0xE5440000 #define EXYNOS5_SOC_MASK 0xFFFFF000 @@ -69,6 +70,7 @@ IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5422, EXYNOS5422_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ @@ -150,10 +152,16 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) #if defined(CONFIG_SOC_EXYNOS5420) # define soc_is_exynos5420() is_samsung_exynos5420() +# define soc_is_exynos5422() is_samsung_exynos5422() +# define soc_is_exynos542x() (soc_is_exynos5420() || soc_is_exynos5422()) #else # define soc_is_exynos5420() 0 +# define soc_is_exynos5422() 0 +# define soc_is_exynos542x() 0 #endif +#define EXYNOS5420_REV_0 0x0 + #if defined(CONFIG_SOC_EXYNOS5440) # define soc_is_exynos5440() is_samsung_exynos5440() #else @@ -195,6 +203,7 @@ extern void s3c_init_cpu(unsigned long idcode, /* core initialisation functions */ +extern void s3c24xx_init_irq(void); extern void s5p_init_irq(u32 *vic, u32 num_vic); extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); @@ -213,6 +222,10 @@ extern void s3c24xx_init_uartdevs(char *name, struct s3c24xx_uart_resources *res, struct s3c2410_uartcfg *cfg, int no); +/* timer for 2410/2440 */ + +extern void s3c24xx_timer_init(void); + extern struct syscore_ops s3c2410_pm_syscore_ops; extern struct syscore_ops s3c2412_pm_syscore_ops; extern struct syscore_ops s3c2416_pm_syscore_ops; diff --git a/drivers/gpu/arm/midgard/mali_kbase_context.c b/drivers/gpu/arm/midgard/mali_kbase_context.c index c7083b4dcd0..545657a8535 100755 --- a/drivers/gpu/arm/midgard/mali_kbase_context.c +++ b/drivers/gpu/arm/midgard/mali_kbase_context.c @@ -217,6 +217,10 @@ void kbase_destroy_context(kbase_context *kctx) kbase_mem_allocator_term(&kctx->osalloc); WARN_ON(atomic_read(&kctx->nonmapped_pages) != 0); + + /* Purposely corrupt the traceback to see if someone keeps using it */ + kctx->jctx.tb = (void *)0xe7; + vfree(kctx); } KBASE_EXPORT_SYMBOL(kbase_destroy_context) diff --git a/drivers/gpu/arm/midgard/mali_kbase_device.c b/drivers/gpu/arm/midgard/mali_kbase_device.c index c321ebf8c01..3a370a346db 100755 --- a/drivers/gpu/arm/midgard/mali_kbase_device.c +++ b/drivers/gpu/arm/midgard/mali_kbase_device.c @@ -23,6 +23,7 @@ */ #include +#include #include #include #include @@ -284,6 +285,31 @@ void kbase_device_trace_register_access(kbase_context *kctx, kbase_reg_access_ty { unsigned long flags; spin_lock_irqsave(&kctx->jctx.tb_lock, flags); + + /* + * We've seen corruption of the low bits when tb is supposed to be + * NULL. Collect some data, print and warning, and then fix it up. + * + * Note that delays / barriers below are just throwing things at the + * wall to see what sticks--we don't know that any of them will do + * anything useful. + */ + if (kctx->jctx.tb && (u32)kctx->jctx.tb < 0x100) { + void *tb1, *tb2, *tb3, *tb4; + + tb1 = kctx->jctx.tb; + dsb(); + tb2 = kctx->jctx.tb; + udelay(5); + tb3 = ((volatile kbase_context *)kctx)->jctx.tb; + flush_cache_all(); + tb4 = kctx->jctx.tb; + + WARN(1, "tb failure: %p %p %p %p\n", tb1, tb2, tb3, tb4); + + kctx->jctx.tb = NULL; + } + if (kctx->jctx.tb) { u16 wrap_count; u16 write_offset; diff --git a/drivers/gpu/arm/midgard/mali_kbase_jm.c b/drivers/gpu/arm/midgard/mali_kbase_jm.c index c85f63ed05a..5903deaea93 100755 --- a/drivers/gpu/arm/midgard/mali_kbase_jm.c +++ b/drivers/gpu/arm/midgard/mali_kbase_jm.c @@ -212,7 +212,7 @@ void kbase_job_done_slot(kbase_device *kbdev, int s, u32 completion_code, u64 jo if (katom->event_code != BASE_JD_EVENT_JOB_CANCELLED) katom->event_code = (base_jd_event_code) completion_code; - kbase_device_trace_register_access(kctx, REG_WRITE, JOB_CONTROL_REG(JOB_IRQ_CLEAR), 1 << s); + if (kctx && kctx->jctx.tb) kbase_device_trace_register_access(kctx, REG_WRITE, JOB_CONTROL_REG(JOB_IRQ_CLEAR), 1 << s); /* Complete the job, and start new ones * diff --git a/drivers/gpu/arm/midgard/mali_kbase_js_policy_cfs.c b/drivers/gpu/arm/midgard/mali_kbase_js_policy_cfs.c index 78c0fd290b5..b049974c174 100755 --- a/drivers/gpu/arm/midgard/mali_kbase_js_policy_cfs.c +++ b/drivers/gpu/arm/midgard/mali_kbase_js_policy_cfs.c @@ -391,7 +391,7 @@ STATIC void kbasep_js_debug_check(kbasep_js_policy_cfs *policy_info, kbase_conte expect_queued = (check_flag & KBASEP_JS_CHECKFLAG_IS_QUEUED) ? MALI_TRUE : MALI_FALSE; - KBASE_DEBUG_ASSERT_MSG(expect_queued == is_queued, "Expected context %p to be %s but it was %s\n", kctx, (expect_queued) ? "queued" : "not queued", (is_queued) ? "queued" : "not queued"); + KBASE_DEBUG_ASSERT_MSG(expect_queued == is_queued, "Expected context %p to be %s but it was %s", kctx, (expect_queued) ? "queued" : "not queued", (is_queued) ? "queued" : "not queued"); } @@ -401,7 +401,7 @@ STATIC void kbasep_js_debug_check(kbasep_js_policy_cfs *policy_info, kbase_conte is_scheduled = (kbasep_list_member_of(&policy_info->scheduled_ctxs_head, &kctx->jctx.sched_info.runpool.policy_ctx.cfs.list)) ? MALI_TRUE : MALI_FALSE; expect_scheduled = (check_flag & KBASEP_JS_CHECKFLAG_IS_SCHEDULED) ? MALI_TRUE : MALI_FALSE; - KBASE_DEBUG_ASSERT_MSG(expect_scheduled == is_scheduled, "Expected context %p to be %s but it was %s\n", kctx, (expect_scheduled) ? "scheduled" : "not scheduled", (is_scheduled) ? "scheduled" : "not scheduled"); + KBASE_DEBUG_ASSERT_MSG(expect_scheduled == is_scheduled, "Expected context %p to be %s but it was %s", kctx, (expect_scheduled) ? "scheduled" : "not scheduled", (is_scheduled) ? "scheduled" : "not scheduled"); } @@ -476,7 +476,7 @@ STATIC void debug_check_core_req_variants(kbase_device *kbdev, kbasep_js_policy_ } /* Early-out on any failure */ - KBASE_DEBUG_ASSERT_MSG(found != MALI_FALSE, "Job slot %d features 0x%x not matched by core_req_variants. " "Rework core_req_variants and vairants_supported_<...>_state[] to match\n", j, job_core_req); + KBASE_DEBUG_ASSERT_MSG(found != MALI_FALSE, "Job slot %d features 0x%x not matched by core_req_variants. " "Rework core_req_variants and vairants_supported_<...>_state[] to match", j, job_core_req); } } #endif diff --git a/drivers/gpu/arm/midgard/mali_kbase_mem.h b/drivers/gpu/arm/midgard/mali_kbase_mem.h index 8cbde3210a4..20b130737c7 100755 --- a/drivers/gpu/arm/midgard/mali_kbase_mem.h +++ b/drivers/gpu/arm/midgard/mali_kbase_mem.h @@ -613,4 +613,5 @@ void kbase_wait_write_flush(kbase_context *kctx); #endif + #endif /* _KBASE_MEM_H_ */ diff --git a/drivers/gpu/arm/midgard/mali_kbase_pm.h b/drivers/gpu/arm/midgard/mali_kbase_pm.h index a9baff977dd..914ba2fcc4b 100755 --- a/drivers/gpu/arm/midgard/mali_kbase_pm.h +++ b/drivers/gpu/arm/midgard/mali_kbase_pm.h @@ -660,6 +660,26 @@ mali_error kbasep_pm_metrics_init(struct kbase_device *kbdev); */ void kbasep_pm_metrics_term(struct kbase_device *kbdev); +/** Suspend the metrics gathering framework. + * + * Stop the pm metrics timer. Usually called upon system suspend. + * Further calls to kbasep_pm_record_gpu_active() and + * kbasep_pm_record_gpu_idle() will essentially be ignored, since they will not + * be used to generate any dvfs events. + * + * @param kbdev The kbase device structure for the device (must be a valid pointer) + */ +void kbasep_pm_metrics_suspend(struct kbase_device *kbdev); + +/** Resume the metrics gathering framework. + * + * Restart the pm metrics timer. Usually called upon system resume. + * All metrics are first reset to 0, and the GPU is considered initially idle. + * + * @param kbdev The kbase device structure for the device (must be a valid pointer) + */ +void kbasep_pm_metrics_resume(struct kbase_device *kbdev); + /** Record that the GPU is active. * * This records that the GPU is now active. The previous GPU state must have been idle, the function will assert if diff --git a/drivers/gpu/arm/midgard/mali_kbase_pm_metrics.c b/drivers/gpu/arm/midgard/mali_kbase_pm_metrics.c index 50450ed6dc3..e2d404a661e 100755 --- a/drivers/gpu/arm/midgard/mali_kbase_pm_metrics.c +++ b/drivers/gpu/arm/midgard/mali_kbase_pm_metrics.c @@ -104,6 +104,46 @@ void kbasep_pm_metrics_term(kbase_device *kbdev) KBASE_EXPORT_TEST_API(kbasep_pm_metrics_term) +void kbasep_pm_metrics_suspend(kbase_device *kbdev) +{ + unsigned long flags; + KBASE_DEBUG_ASSERT(kbdev != NULL); + + spin_lock_irqsave(&kbdev->pm.metrics.lock, flags); + kbdev->pm.metrics.timer_active = MALI_FALSE; + spin_unlock_irqrestore(&kbdev->pm.metrics.lock, flags); + + hrtimer_cancel(&kbdev->pm.metrics.timer); + + kbase_pm_unregister_vsync_callback(kbdev); +} + +KBASE_EXPORT_TEST_API(kbasep_pm_metrics_suspend) + +void kbasep_pm_metrics_resume(kbase_device *kbdev) +{ + unsigned long flags; + KBASE_DEBUG_ASSERT(kbdev != NULL); + + /* reset pm.metrics */ + spin_lock_irqsave(&kbdev->pm.metrics.lock, flags); + kbdev->pm.metrics.vsync_hit = 0; + kbdev->pm.metrics.utilisation = 0; + kbdev->pm.metrics.time_period_start = ktime_get(); + kbdev->pm.metrics.time_busy = 0; + kbdev->pm.metrics.time_idle = 0; + /* Unlike at init, gpu is initially idle at resume */ + kbdev->pm.metrics.gpu_active = MALI_FALSE; + kbdev->pm.metrics.timer_active = MALI_TRUE; + spin_unlock_irqrestore(&kbdev->pm.metrics.lock, flags); + + hrtimer_start(&kbdev->pm.metrics.timer, HR_TIMER_DELAY_MSEC(kbdev->pm.platform_dvfs_frequency), HRTIMER_MODE_REL); + + kbase_pm_register_vsync_callback(kbdev); +} + +KBASE_EXPORT_TEST_API(kbasep_pm_metrics_resume) + void kbasep_pm_record_gpu_idle(kbase_device *kbdev) { unsigned long flags; diff --git a/drivers/gpu/arm/midgard/platform/arndale_octa/mali_kbase_config_arndale_octa.c b/drivers/gpu/arm/midgard/platform/arndale_octa/mali_kbase_config_arndale_octa.c index 930e0bb8363..b7fcf30c1c8 100644 --- a/drivers/gpu/arm/midgard/platform/arndale_octa/mali_kbase_config_arndale_octa.c +++ b/drivers/gpu/arm/midgard/platform/arndale_octa/mali_kbase_config_arndale_octa.c @@ -1,12 +1,15 @@ /* * - * (C) COPYRIGHT 2012 ARM Limited. All rights reserved. + * (C) COPYRIGHT ARM Limited. All rights reserved. * - * This program is free software and is provided to you under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence. + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms + * of such GNU licence. * - * A copy of the licence is included with the program, and can also be obtained from Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * A copy of the licence is included with the program, and can also be obtained + * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. * */ @@ -33,14 +36,13 @@ #include #include #include -//#include -#include <../common.h> +#include #include #include #include #include #include -#if defined(CONFIG_MALI_T6XX_DVFS) && defined(CONFIG_CPU_FREQ) +#if defined(CONFIG_MALI_MIDGARD_DVFS) && defined(CONFIG_CPU_FREQ) #include #include #endif @@ -58,7 +60,6 @@ #include #include #include -#include #include "mali_linux_dvfs_trace.h" @@ -66,7 +67,7 @@ #define MALI_DVFS_STEP 8 #define MALI_DVFS_KEEP_STAY_CNT 10 -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS #define KBASE_PM_DVFS_FREQUENCY (100) /* 100ms */ #ifdef CONFIG_CPU_FREQ #define MALI_DVFS_ASV_ENABLE @@ -81,7 +82,7 @@ #define HZ_IN_MHZ (1000000) #define MALI_RTPM_DEBUG 0 #define RUNTIME_PM_DELAY_TIME 10 -#define CONFIG_T6XX_HWVER_R0P0 1 +#define CONFIG_MIDGARD_HWVER_R0P0 1 #define G3D_ASV_VOL_OFFSET 25000 struct regulator *kbase_platform_get_regulator(void); @@ -90,14 +91,14 @@ int kbase_platform_regulator_disable(void); int kbase_platform_regulator_enable(void); int kbase_platform_get_default_voltage(struct device *dev, int *vol); int kbase_platform_get_voltage(struct device *dev, int *vol); -#if defined CONFIG_MALI_T6XX_DVFS +#if defined CONFIG_MALI_MIDGARD_DVFS static int kbase_platform_set_voltage(struct device *dev, int vol); static void kbase_platform_dvfs_set_clock(kbase_device *kbdev, int freq); static void kbase_platform_dvfs_set_level(kbase_device *kbdev, int level); static int kbase_platform_dvfs_get_level(int freq); #endif -#if defined(CONFIG_MALI_T6XX_DVFS) || defined(CONFIG_MALI_T6XX_DEBUG_SYS) +#if defined(CONFIG_MALI_MIDGARD_DVFS) || defined(CONFIG_MALI_MIDGARD_DEBUG_SYS) struct mali_dvfs_info { unsigned int voltage; unsigned int clock; @@ -109,7 +110,7 @@ struct mali_dvfs_info { static struct mali_dvfs_info *mali_dvfs_infotbl; #endif -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS /* * Governor parameters. The governor gets periodic samples of the * GPU utilisation (%busy) and maintains a weighted average over the @@ -131,13 +132,15 @@ static struct mali_dvfs_info *mali_dvfs_infotbl; /* TODO(sleffler) should be const but for voltage */ static struct mali_dvfs_info mali_dvfs_infotbl_exynos5250[MALI_DVFS_STEP] = { -/* A duumy level is added in 5250 to make 8 levels. Since, max_threshold - * value of step 6 is 100, the dvfs code will never come to dummy step 7 +/* + * A dummy level is added in 5250 and 5422 to make 8 levels. In 5250 since the + * max_threshold value of step 6 is 100, the dvfs code will never come to dummy + * step 7. */ #if (MALI_DVFS_STEP == 8) - { 912500, 100000000, 0, 60, DVFS_TIME_TO_CNT(750), DVFS_TIME_TO_CNT(2000)}, - { 925000, 160000000, 40, 75, DVFS_TIME_TO_CNT(750), DVFS_TIME_TO_CNT(2000)}, - {1025000, 266000000, 65, 85, DVFS_TIME_TO_CNT(1000), DVFS_TIME_TO_CNT(3000)}, + { 912500, 100000000, 0, 0, DVFS_TIME_TO_CNT(0), DVFS_TIME_TO_CNT(0)}, + { 925000, 160000000, 0, 0, DVFS_TIME_TO_CNT(0), DVFS_TIME_TO_CNT(0)}, + {1025000, 266000000, 0, 85, DVFS_TIME_TO_CNT(1000), DVFS_TIME_TO_CNT(3000)}, {1075000, 350000000, 65, 85, DVFS_TIME_TO_CNT(750), DVFS_TIME_TO_CNT(1500)}, {1125000, 400000000, 65, 85, DVFS_TIME_TO_CNT(750), DVFS_TIME_TO_CNT(1500)}, {1025000, 450000000, 65, 90, DVFS_TIME_TO_CNT(1000), DVFS_TIME_TO_CNT(1500)}, @@ -156,14 +159,39 @@ static struct mali_dvfs_info mali_dvfs_infotbl_exynos5420[MALI_DVFS_STEP] = { { 862500, 266000000, 65, 85, DVFS_TIME_TO_CNT(1000), DVFS_TIME_TO_CNT(3000)}, { 900000, 350000000, 65, 85, DVFS_TIME_TO_CNT(750), DVFS_TIME_TO_CNT(1500)}, { 937500, 420000000, 65, 85, DVFS_TIME_TO_CNT(750), DVFS_TIME_TO_CNT(1500)}, - { 950000, 480000000, 65, 90, DVFS_TIME_TO_CNT(1000), DVFS_TIME_TO_CNT(1500)}, - { 987500, 533000000, 75, 90, DVFS_TIME_TO_CNT(750), DVFS_TIME_TO_CNT(1500)}, + { 950000, 480000000, 65, 100, DVFS_TIME_TO_CNT(1000), DVFS_TIME_TO_CNT(1500)}, + { 987500, 533000000, 75, 100, DVFS_TIME_TO_CNT(750), DVFS_TIME_TO_CNT(1500)}, {1025000, 600000000, 75, 100, DVFS_TIME_TO_CNT(750), DVFS_TIME_TO_CNT(1500)} #else #error no table #endif }; + +static struct mali_dvfs_info mali_dvfs_infotbl_exynos5422[MALI_DVFS_STEP] = { +#if (MALI_DVFS_STEP == 8) + { 825000, 100000000, 0, 60, DVFS_TIME_TO_CNT(750), + DVFS_TIME_TO_CNT(2000)}, + { 825000, 177000000, 40, 75, DVFS_TIME_TO_CNT(750), + DVFS_TIME_TO_CNT(2000)}, + { 887500, 266000000, 65, 85, DVFS_TIME_TO_CNT(1000), + DVFS_TIME_TO_CNT(3000)}, + { 912500, 350000000, 65, 85, DVFS_TIME_TO_CNT(750), + DVFS_TIME_TO_CNT(1500)}, + { 937500, 420000000, 65, 85, DVFS_TIME_TO_CNT(750), + DVFS_TIME_TO_CNT(1500)}, + { 975000, 480000000, 65, 100, DVFS_TIME_TO_CNT(1000), + DVFS_TIME_TO_CNT(1500)}, + { 1025000, 543000000, 75, 100, DVFS_TIME_TO_CNT(750), + DVFS_TIME_TO_CNT(1500)}, + { 1025000, 543000000, 75, 100, DVFS_TIME_TO_CNT(750), + DVFS_TIME_TO_CNT(1500)}, + +#else +#error no table +#endif +}; + int kbase_platform_dvfs_init(kbase_device *kbdev); void kbase_platform_dvfs_term(void); int kbase_platform_dvfs_get_control_status(void); @@ -283,25 +311,25 @@ static const unsigned int mali_dvfs_vol_default_exynos5250[MALI_DVFS_STEP] = { static int kbase_platform_asv_set(int enable); #endif /* MALI_DVFS_ASV_ENABLE */ -#endif /* CONFIG_MALI_T6XX_DVFS */ +#endif /* CONFIG_MALI_MIDGARD_DVFS */ int kbase_platform_cmu_pmu_control(struct kbase_device *kbdev, int control); void kbase_platform_remove_sysfs_file(struct device *dev); mali_error kbase_platform_init(struct kbase_device *kbdev); -static int kbase_platform_is_power_on(void); void kbase_platform_term(struct kbase_device *kbdev); +static void kbase_platform_dvfs_set_max(kbase_device *kbdev); -#ifdef CONFIG_MALI_T6XX_DEBUG_SYS +#ifdef CONFIG_MALI_MIDGARD_DEBUG_SYS static int kbase_platform_create_sysfs_file(struct device *dev); #ifdef CONFIG_MALI_HWC_TRACE static int mali_setup_system_tracing(struct device *dev); static void mali_cleanup_system_tracing(struct device *dev); #endif /* CONFIG_MALI_HWC_TRACE */ -#endif /* CONFIG_MALI_T6XX_DEBUG_SYS */ +#endif /* CONFIG_MALI_MIDGARD_DEBUG_SYS */ -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS static struct mali_dvfs_status mali_dvfs_status_current; -#endif /* CONFIG_MALI_T6XX_DVFS */ +#endif /* CONFIG_MALI_MIDGARD_DVFS */ struct exynos_context { @@ -312,19 +340,6 @@ struct exynos_context struct clk *sclk_g3d; int t6xx_default_clock; }; -#if 0 -static kbase_io_resources io_resources_exynos5250 = -{ - .job_irq_number = EXYNOS5_JOB_IRQ_NUMBER, - .mmu_irq_number = EXYNOS5_MMU_IRQ_NUMBER, - .gpu_irq_number = EXYNOS5_GPU_IRQ_NUMBER, - .io_memory_region = - { - .start = EXYNOS5_PA_G3D, - .end = EXYNOS5_PA_G3D + (4096 * 5) - 1 - } -}; -#endif /** * Read the CPU clock speed @@ -362,10 +377,22 @@ static void pm_callback_power_off(kbase_device *kbdev) #endif /* CONFIG_PM_RUNTIME */ } +/** + * Power Management callback - suspend + */ +static void pm_callback_suspend(kbase_device *kbdev) +{ +#ifdef CONFIG_MALI_MIDGARD_DVFS + kbase_platform_dvfs_set_max(kbdev); +#endif /* CONFIG_MALI_MIDGARD_DVFS */ +} + static kbase_pm_callback_conf pm_callbacks = { .power_on_callback = pm_callback_power_on, .power_off_callback = pm_callback_power_off, + .power_suspend_callback = pm_callback_suspend, + .power_resume_callback = NULL }; /** @@ -375,12 +402,12 @@ mali_bool kbase_platform_exynos5_init(kbase_device *kbdev) { if(MALI_ERROR_NONE == kbase_platform_init(kbdev)) { -#ifdef CONFIG_MALI_T6XX_DEBUG_SYS +#ifdef CONFIG_MALI_MIDGARD_DEBUG_SYS if(kbase_platform_create_sysfs_file(kbdev->dev)) { return MALI_TRUE; } -#endif /* CONFIG_MALI_T6XX_DEBUG_SYS */ +#endif /* CONFIG_MALI_MIDGARD_DEBUG_SYS */ return MALI_TRUE; } @@ -392,9 +419,9 @@ mali_bool kbase_platform_exynos5_init(kbase_device *kbdev) */ void kbase_platform_exynos5_term(kbase_device *kbdev) { -#ifdef CONFIG_MALI_T6XX_DEBUG_SYS +#ifdef CONFIG_MALI_MIDGARD_DEBUG_SYS kbase_platform_remove_sysfs_file(kbdev->dev); -#endif /* CONFIG_MALI_T6XX_DEBUG_SYS */ +#endif /* CONFIG_MALI_MIDGARD_DEBUG_SYS */ kbase_platform_term(kbdev); } @@ -405,25 +432,16 @@ kbase_platform_funcs_conf platform_funcs = }; const kbase_attribute config_attributes_exynos5250[] = { - /*{ - KBASE_CONFIG_ATTR_MEMORY_OS_SHARED_MAX, - 2048 * 1024 * 1024UL *//* 2048MB */ - /*}, - - { - KBASE_CONFIG_ATTR_MEMORY_OS_SHARED_PERF_GPU, - KBASE_MEM_PERF_FAST - },*/ { KBASE_CONFIG_ATTR_POWER_MANAGEMENT_CALLBACKS, (uintptr_t)&pm_callbacks }, -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS { KBASE_CONFIG_ATTR_POWER_MANAGEMENT_DVFS_FREQ, KBASE_PM_DVFS_FREQUENCY /* 100ms */ }, -#endif /* CONFIG_MALI_T6XX_DVFS */ +#endif /* CONFIG_MALI_MIDGARD_DVFS */ { KBASE_CONFIG_ATTR_PLATFORM_FUNCS, (uintptr_t)&platform_funcs @@ -452,21 +470,11 @@ const kbase_attribute config_attributes_exynos5250[] = { }; const kbase_attribute config_attributes_exynos5420[] = { - /*{ - KBASE_CONFIG_ATTR_MEMORY_OS_SHARED_MAX, - 2048 * 1024 * 1024UL *//* 2048MB */ - /* TODO: Once we have 4GB available we can change this*/ - /*}, - - { - KBASE_CONFIG_ATTR_MEMORY_OS_SHARED_PERF_GPU, - KBASE_MEM_PERF_FAST - },*/ { KBASE_CONFIG_ATTR_POWER_MANAGEMENT_CALLBACKS, (uintptr_t)&pm_callbacks }, -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS { KBASE_CONFIG_ATTR_POWER_MANAGEMENT_DVFS_FREQ, KBASE_PM_DVFS_FREQUENCY /* 100ms */ @@ -500,20 +508,14 @@ const kbase_attribute config_attributes_exynos5420[] = { }; kbase_platform_config platform_config; -kbase_platform_config *kbase_get_platform_config(void) { -#if 0 + +kbase_platform_config *kbase_get_platform_config(void) +{ if (soc_is_exynos5250()) - { - chromebook_platform_config.attributes = config_attributes_exynos5250; - chromebook_platform_config.io_resources = &io_resources_exynos5250; - chromebook_platform_config.midgard_type = KBASE_MALI_T604; - return &chromebook_platform_config; - } - - return NULL; -#endif - platform_config.attributes = config_attributes_exynos5420; - + platform_config.attributes = config_attributes_exynos5250; + else if (soc_is_exynos542x()) + platform_config.attributes = config_attributes_exynos5420; + platform_config.midgard_type = KBASE_MALI_T604; return &platform_config; } @@ -528,6 +530,7 @@ static int kbase_platform_power_clock_init(kbase_device *kbdev) struct device *dev = kbdev->dev; int timeout; struct exynos_context *platform; + void *g3d_status_reg; platform = (struct exynos_context *) kbdev->platform_context; if(NULL == platform) @@ -536,11 +539,18 @@ static int kbase_platform_power_clock_init(kbase_device *kbdev) } /* Turn on G3D power */ - __raw_writel(0x7, EXYNOS5_G3D_CONFIGURATION); + if (soc_is_exynos5250()) { + g3d_status_reg = EXYNOS5_G3D_STATUS; + __raw_writel(0x7, EXYNOS5_G3D_CONFIGURATION); + } + else if (soc_is_exynos542x()) { + g3d_status_reg = EXYNOS5420_G3D_STATUS; + __raw_writel(0x7, EXYNOS5420_G3D_CONFIGURATION); + } /* Wait for G3D power stability for 1ms */ timeout = 10; - while((__raw_readl(EXYNOS5_G3D_STATUS) & 0x7) != 0x7) { + while((__raw_readl(g3d_status_reg) & 0x7) != 0x7) { if(timeout == 0) { /* need to call panic */ panic("failed to turn on g3d power\n"); @@ -564,13 +574,13 @@ static int kbase_platform_power_clock_init(kbase_device *kbdev) printk("v4 support\n"); } -#ifdef CONFIG_T6XX_HWVER_R0P0 +#ifdef CONFIG_MIDGARD_HWVER_R0P0 platform->sclk_g3d = clk_get(dev, "aclk_g3d"); if(IS_ERR(platform->sclk_g3d)) { printk(KERN_ERR "failed to clk_get [aclk_g3d]\n"); goto out; } -#else /* CONFIG_T6XX_HWVER_R0P0 */ +#else /* CONFIG_MIDGARD_HWVER_R0P0 */ { struct clk *mpll = NULL; mpll = clk_get(dev, "mout_mpll_user"); @@ -598,7 +608,7 @@ static int kbase_platform_power_clock_init(kbase_device *kbdev) goto out; } } -#endif /* CONFIG_T6XX_HWVER_R0P0 */ +#endif /* CONFIG_MIDGARD_HWVER_R0P0 */ (void) clk_prepare_enable(platform->sclk_g3d); return 0; out: @@ -658,28 +668,27 @@ static int kbase_platform_clock_off(struct kbase_device *kbdev) return 0; } -/** - * Report GPU power status - */ -static inline int kbase_platform_is_power_on(void) -{ - return ((__raw_readl(EXYNOS5_G3D_STATUS) & 0x7) == 0x7) ? 1 : 0; -} - /** * Enable GPU power */ static int kbase_platform_power_on(void) { int timeout; + void *g3d_status_reg; - /* Turn on G3D */ - __raw_writel(0x7, EXYNOS5_G3D_CONFIGURATION); + /* Turn on G3D power */ + if (soc_is_exynos5250()) { + g3d_status_reg = EXYNOS5_G3D_STATUS; + __raw_writel(0x7, EXYNOS5_G3D_CONFIGURATION); + } + else if (soc_is_exynos542x()) { + g3d_status_reg = EXYNOS5420_G3D_STATUS; + __raw_writel(0x7, EXYNOS5420_G3D_CONFIGURATION); + } /* Wait for G3D power stability */ timeout = 1000; - - while((__raw_readl(EXYNOS5_G3D_STATUS) & 0x7) != 0x7) { + while((__raw_readl(g3d_status_reg) & 0x7) != 0x7) { if(timeout == 0) { /* need to call panic */ panic("failed to turn on g3d via g3d_configuration\n"); @@ -698,14 +707,21 @@ static int kbase_platform_power_on(void) static int kbase_platform_power_off(void) { int timeout; + void *g3d_status_reg; /* Turn off G3D */ - __raw_writel(0x0, EXYNOS5_G3D_CONFIGURATION); + if (soc_is_exynos5250()) { + g3d_status_reg = EXYNOS5_G3D_STATUS; + __raw_writel(0x0, EXYNOS5_G3D_CONFIGURATION); + } + else if (soc_is_exynos542x()) { + g3d_status_reg = EXYNOS5420_G3D_STATUS; + __raw_writel(0x0, EXYNOS5420_G3D_CONFIGURATION); + } /* Wait for G3D power stability */ timeout = 1000; - - while(__raw_readl(EXYNOS5_G3D_STATUS) & 0x7) { + while(__raw_readl(g3d_status_reg) & 0x7) { if(timeout == 0) { /* need to call panic */ panic( "failed to turn off g3d via g3d_configuration\n"); @@ -783,7 +799,7 @@ int kbase_platform_cmu_pmu_control(struct kbase_device *kbdev, int control) return 0; } -#ifdef CONFIG_MALI_T6XX_DEBUG_SYS +#ifdef CONFIG_MALI_MIDGARD_DEBUG_SYS /** The sysfs file @c clock, fbdev. * * This is used for obtaining information about the vithar @@ -817,10 +833,9 @@ static ssize_t mali_sysfs_show_clock(struct device *dev, static ssize_t mali_sysfs_set_clock(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS struct kbase_device *kbdev = dev_get_drvdata(dev); struct exynos_context *platform; - unsigned int tmp = 0; unsigned long freq; int level; @@ -851,12 +866,7 @@ static ssize_t mali_sysfs_set_clock(struct device *dev, } kbase_platform_dvfs_set_level(kbdev, level); - - /* Waiting for clock is stable */ - do { - tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_TOP0); - } while (tmp & 0x1000000); -#endif /* CONFIG_MALI_T6XX_DVFS */ +#endif /* CONFIG_MALI_MIDGARD_DVFS */ return count; } DEVICE_ATTR(clock, S_IRUGO|S_IWUSR, mali_sysfs_show_clock, @@ -918,255 +928,12 @@ static ssize_t mali_sysfs_show_memory(struct device *dev, if (!kbdev) return -ENODEV; - return ret; -} -DEVICE_ATTR(memory, S_IRUGO, mali_sysfs_show_memory, NULL); - -typedef enum { - L1_I_tag_RAM = 0x00, - L1_I_data_RAM = 0x01, - L1_I_BTB_RAM = 0x02, - L1_I_GHB_RAM = 0x03, - L1_I_TLB_RAM = 0x04, - L1_I_indirect_predictor_RAM = 0x05, - L1_D_tag_RAM = 0x08, - L1_D_data_RAM = 0x09, - L1_D_load_TLB_array = 0x0A, - L1_D_store_TLB_array = 0x0B, - L2_tag_RAM = 0x10, - L2_data_RAM = 0x11, - L2_snoop_tag_RAM = 0x12, - L2_data_ECC_RAM = 0x13, - L2_dirty_RAM = 0x14, - L2_TLB_RAM = 0x18 -} RAMID_type; - -static inline void asm_ramindex_mrc(u32 *DL1Data0, u32 *DL1Data1, - u32 *DL1Data2, u32 *DL1Data3) -{ - u32 val; - - if(DL1Data0) - { - asm volatile("mrc p15, 0, %0, c15, c1, 0" : "=r" (val)); - *DL1Data0 = val; - } - if(DL1Data1) - { - asm volatile("mrc p15, 0, %0, c15, c1, 1" : "=r" (val)); - *DL1Data1 = val; - } - if(DL1Data2) - { - asm volatile("mrc p15, 0, %0, c15, c1, 2" : "=r" (val)); - *DL1Data2 = val; - } - if(DL1Data3) - { - asm volatile("mrc p15, 0, %0, c15, c1, 3" : "=r" (val)); - *DL1Data3 = val; - } -} - -static inline void asm_ramindex_mcr(u32 val) -{ - asm volatile("mcr p15, 0, %0, c15, c4, 0" : : "r" (val)); - asm volatile("dsb"); - asm volatile("isb"); -} - -static void get_tlb_array(u32 val, u32 *DL1Data0, u32 *DL1Data1, - u32 *DL1Data2, u32 *DL1Data3) -{ - asm_ramindex_mcr(val); - asm_ramindex_mrc(DL1Data0, DL1Data1, DL1Data2, DL1Data3); -} - -static RAMID_type ramindex = L1_D_load_TLB_array; -static ssize_t mali_sysfs_show_dtlb(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct kbase_device *kbdev; - ssize_t ret = 0; - int entries, ways; - u32 DL1Data0 = 0, DL1Data1 = 0, DL1Data2 = 0, DL1Data3 = 0; - - kbdev = dev_get_drvdata(dev); - - if (!kbdev) - return -ENODEV; + ret = sprintf(buf, "%lu bytes\n", + atomic_read(&kbdev->memdev.used_pages) * PAGE_SIZE); - /* L1-I tag RAM */ - if(ramindex == L1_I_tag_RAM) - { - printk("Not implemented yet\n"); - } - /* L1-I data RAM */ - else if(ramindex == L1_I_data_RAM) - { - printk("Not implemented yet\n"); - } - /* L1-I BTB RAM */ - else if(ramindex == L1_I_BTB_RAM) - { - printk("Not implemented yet\n"); - } - /* L1-I GHB RAM */ - else if(ramindex == L1_I_GHB_RAM) - { - printk("Not implemented yet\n"); - } - /* L1-I TLB RAM */ - else if(ramindex == L1_I_TLB_RAM) - { - printk("L1-I TLB RAM\n"); - for(entries = 0 ; entries < 32 ; entries++) - { - get_tlb_array((((u8)ramindex) << 24) + entries, &DL1Data0, &DL1Data1, &DL1Data2, NULL); - printk("entries[%d], DL1Data0=%08x, DL1Data1=%08x DL1Data2=%08x\n", entries, DL1Data0, DL1Data1 & 0xffff, 0x0); - } - } - /* L1-I indirect predictor RAM */ - else if(ramindex == L1_I_indirect_predictor_RAM) - { - printk("Not implemented yet\n"); - } - /* L1-D tag RAM */ - else if(ramindex == L1_D_tag_RAM) - { - printk("Not implemented yet\n"); - } - /* L1-D data RAM */ - else if(ramindex == L1_D_data_RAM) - { - printk("Not implemented yet\n"); - } - /* L1-D load TLB array */ - else if(ramindex == L1_D_load_TLB_array) - { - printk("L1-D load TLB array\n"); - for(entries = 0 ; entries < 32 ; entries++) - { - get_tlb_array((((u8)ramindex) << 24) + entries, &DL1Data0, &DL1Data1, &DL1Data2, &DL1Data3); - printk("entries[%d], DL1Data0=%08x, DL1Data1=%08x, DL1Data2=%08x, DL1Data3=%08x\n", entries, DL1Data0, DL1Data1, DL1Data2, DL1Data3 & 0x3f); - } - } - /* L1-D store TLB array */ - else if(ramindex == L1_D_store_TLB_array) - { - printk("\nL1-D store TLB array\n"); - for(entries = 0 ; entries < 32 ; entries++) - { - get_tlb_array((((u8)ramindex) << 24) + entries, &DL1Data0, &DL1Data1, &DL1Data2, &DL1Data3); - printk("entries[%d], DL1Data0=%08x, DL1Data1=%08x, DL1Data2=%08x, DL1Data3=%08x\n", entries, DL1Data0, DL1Data1, DL1Data2, DL1Data3 & 0x3f); - } - } - /* L2 tag RAM */ - else if(ramindex == L2_tag_RAM) - { - printk("Not implemented yet\n"); - } - /* L2 data RAM */ - else if(ramindex == L2_data_RAM) - { - printk("Not implemented yet\n"); - } - /* L2 snoop tag RAM */ - else if(ramindex == L2_snoop_tag_RAM) - { - printk("Not implemented yet\n"); - } - /* L2 data ECC RAM */ - else if(ramindex == L2_data_ECC_RAM) - { - printk("Not implemented yet\n"); - } - /* L2 dirty RAM */ - else if(ramindex == L2_dirty_RAM) - { - printk("Not implemented yet\n"); - } - /* L2 TLB array */ - else if(ramindex == L2_TLB_RAM) - { - printk("\nL2 TLB array\n"); - for(ways = 0 ; ways < 4 ; ways++) - { - for(entries = 0 ; entries < 512 ; entries++) - { - get_tlb_array((ramindex << 24) + (ways << 18) + entries, &DL1Data0, &DL1Data1, &DL1Data2, &DL1Data3); - printk("ways[%d]:entries[%d], DL1Data0=%08x, DL1Data1=%08x, DL1Data2=%08x, DL1Data3=%08x\n", ways, entries, DL1Data0, DL1Data1, DL1Data2, DL1Data3); - } - } - } - - ret += snprintf(buf+ret, PAGE_SIZE-ret, "Succeeded...\n"); - - if (ret < PAGE_SIZE - 1) - ret += snprintf(buf+ret, PAGE_SIZE-ret, "\n"); - else - { - buf[PAGE_SIZE-2] = '\n'; - buf[PAGE_SIZE-1] = '\0'; - ret = PAGE_SIZE-1; - } return ret; } - -static ssize_t mali_sysfs_set_dtlb(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - struct kbase_device *kbdev; - kbdev = dev_get_drvdata(dev); - - if (!kbdev) - return -ENODEV; - - if (sysfs_streq("L1_I_tag_RAM", buf)) { - ramindex = L1_I_tag_RAM; - } else if (sysfs_streq("L1_I_data_RAM", buf)) { - ramindex = L1_I_data_RAM; - } else if (sysfs_streq("L1_I_BTB_RAM", buf)) { - ramindex = L1_I_BTB_RAM; - } else if (sysfs_streq("L1_I_GHB_RAM", buf)) { - ramindex = L1_I_GHB_RAM; - } else if (sysfs_streq("L1_I_TLB_RAM", buf)) { - ramindex = L1_I_TLB_RAM; - } else if (sysfs_streq("L1_I_indirect_predictor_RAM", buf)) { - ramindex = L1_I_indirect_predictor_RAM; - } else if (sysfs_streq("L1_D_tag_RAM", buf)) { - ramindex = L1_D_tag_RAM; - } else if (sysfs_streq("L1_D_data_RAM", buf)) { - ramindex = L1_D_data_RAM; - } else if (sysfs_streq("L1_D_load_TLB_array", buf)) { - ramindex = L1_D_load_TLB_array; - } else if (sysfs_streq("L1_D_store_TLB_array", buf)) { - ramindex = L1_D_store_TLB_array; - } else if (sysfs_streq("L2_tag_RAM", buf)) { - ramindex = L2_tag_RAM; - } else if (sysfs_streq("L2_data_RAM", buf)) { - ramindex = L2_data_RAM; - } else if (sysfs_streq("L2_snoop_tag_RAM", buf)) { - ramindex = L2_snoop_tag_RAM; - } else if (sysfs_streq("L2_data_ECC_RAM", buf)) { - ramindex = L2_data_ECC_RAM; - } else if (sysfs_streq("L2_dirty_RAM", buf)) { - ramindex = L2_dirty_RAM; - } else if (sysfs_streq("L2_TLB_RAM", buf)) { - ramindex = L2_TLB_RAM; - } else { - printk("Invalid value....\n\n"); - printk("Available options are one of below\n"); - printk("L1_I_tag_RAM, L1_I_data_RAM, L1_I_BTB_RAM\n"); - printk("L1_I_GHB_RAM, L1_I_TLB_RAM, L1_I_indirect_predictor_RAM\n"); - printk("L1_D_tag_RAM, L1_D_data_RAM, L1_D_load_TLB_array, L1_D_store_TLB_array\n"); - printk("L2_tag_RAM, L2_data_RAM, L2_snoop_tag_RAM, L2_data_ECC_RAM\n"); - printk("L2_dirty_RAM, L2_TLB_RAM\n"); - } - - return count; -} -DEVICE_ATTR(dtlb, S_IRUGO|S_IWUSR, mali_sysfs_show_dtlb, mali_sysfs_set_dtlb); +DEVICE_ATTR(memory, S_IRUGO, mali_sysfs_show_memory, NULL); static ssize_t mali_sysfs_show_vol(struct device *dev, struct device_attribute *attr, char *buf) @@ -1267,7 +1034,7 @@ static ssize_t mali_sysfs_set_clkout(struct device *dev, DEVICE_ATTR(clkout, S_IRUGO|S_IWUSR, mali_sysfs_show_clkout, mali_sysfs_set_clkout); -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS static ssize_t mali_sysfs_show_dvfs(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1326,7 +1093,7 @@ static ssize_t mali_sysfs_set_dvfs(struct device *dev, return count; } DEVICE_ATTR(dvfs, S_IRUGO|S_IWUSR, mali_sysfs_show_dvfs, mali_sysfs_set_dvfs); -#endif /* CONFIG_MALI_T6XX_DVFS */ +#endif /* CONFIG_MALI_MIDGARD_DVFS */ #ifdef MALI_DVFS_ASV_ENABLE static ssize_t mali_sysfs_show_asv(struct device *dev, @@ -1336,6 +1103,8 @@ static ssize_t mali_sysfs_show_asv(struct device *dev, struct kbase_device *kbdev; ssize_t ret = 0; int i; + int asv_group; + kbdev = dev_get_drvdata(dev); if (!kbdev) @@ -1343,8 +1112,15 @@ static ssize_t mali_sysfs_show_asv(struct device *dev, if (!buf) return -EINVAL; - ret += scnprintf(buf, PAGE_SIZE, "asv group:%d exynos_lot_id:%d\n", - exynos_result_of_asv & 0xf, exynos_lot_id); + asv_group = exynos_asv_group_get(ID_G3D); + if (soc_is_exynos5250()) { + ret += scnprintf(buf, PAGE_SIZE, "asv group:%d exynos_lot_id:%d\n", + asv_group, exynos_lot_id); + } else if (soc_is_exynos542x()) { + ret += scnprintf(buf, PAGE_SIZE, "asv group:%d mp%d\n", + asv_group, exynos5420_is_g3d_mp6() ? 6 : 4); + } + for (i = MALI_DVFS_STEP - 1; i >= 0; i--) { ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%u:%d\n", mali_dvfs_infotbl[i].clock, @@ -1395,12 +1171,6 @@ static int kbase_platform_create_sysfs_file(struct device *dev) goto out; } - if (device_create_file(dev, &dev_attr_dtlb)) - { - dev_err(dev, "Couldn't create sysfs file [dtlb]\n"); - goto out; - } - if (device_create_file(dev, &dev_attr_vol)) { dev_err(dev, "Couldn't create sysfs file [vol]\n"); @@ -1412,7 +1182,7 @@ static int kbase_platform_create_sysfs_file(struct device *dev) dev_err(dev, "Couldn't create sysfs file [clkout]\n"); goto out; } -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS if (device_create_file(dev, &dev_attr_dvfs)) { dev_err(dev, "Couldn't create sysfs file [dvfs]\n"); @@ -1424,7 +1194,7 @@ static int kbase_platform_create_sysfs_file(struct device *dev) goto out; } #endif -#endif /* CONFIG_MALI_T6XX_DVFS */ +#endif /* CONFIG_MALI_MIDGARD_DVFS */ #ifdef CONFIG_MALI_HWC_TRACE if (!mali_setup_system_tracing(dev)) goto out; @@ -1440,20 +1210,19 @@ void kbase_platform_remove_sysfs_file(struct device *dev) device_remove_file(dev, &dev_attr_clock); device_remove_file(dev, &dev_attr_available_frequencies); device_remove_file(dev, &dev_attr_fbdev); - device_remove_file(dev, &dev_attr_dtlb); device_remove_file(dev, &dev_attr_vol); device_remove_file(dev, &dev_attr_clkout); -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS device_remove_file(dev, &dev_attr_dvfs); #ifdef MALI_DVFS_ASV_ENABLE device_remove_file(dev, &dev_attr_asv); #endif -#endif /* CONFIG_MALI_T6XX_DVFS */ +#endif /* CONFIG_MALI_MIDGARD_DVFS */ #ifdef CONFIG_MALI_HWC_TRACE mali_cleanup_system_tracing(dev); #endif /* CONFIG_MALI_HWC_TRACE */ } -#endif /* CONFIG_MALI_T6XX_DEBUG_SYS */ +#endif /* CONFIG_MALI_MIDGARD_DEBUG_SYS */ mali_error kbase_platform_init(kbase_device *kbdev) { @@ -1467,7 +1236,12 @@ mali_error kbase_platform_init(kbase_device *kbdev) } kbdev->platform_context = (void *) platform; - platform->t6xx_default_clock = 533000000; + + if (soc_is_exynos542x()) + platform->t6xx_default_clock = 420000000; + else + platform->t6xx_default_clock = 533000000; + platform->cmu_pmu_status = 0; spin_lock_init(&platform->cmu_pmu_lock); @@ -1483,18 +1257,18 @@ mali_error kbase_platform_init(kbase_device *kbdev) } #endif /* CONFIG_REGULATOR */ -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS if (!kbase_platform_dvfs_init(kbdev)) goto dvfs_init_fail; -#endif /* CONFIG_MALI_T6XX_DVFS */ +#endif /* CONFIG_MALI_MIDGARD_DVFS */ /* Enable power */ kbase_platform_cmu_pmu_control(kbdev, 1); return MALI_ERROR_NONE; -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS dvfs_init_fail: -#endif /* CONFIG_MALI_T6XX_DVFS */ +#endif /* CONFIG_MALI_MIDGARD_DVFS */ #ifdef CONFIG_REGULATOR kbase_platform_regulator_disable(); regulator_init_fail: @@ -1511,9 +1285,9 @@ void kbase_platform_term(kbase_device *kbdev) platform = (struct exynos_context *) kbdev->platform_context; -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS kbase_platform_dvfs_term(); -#endif /* CONFIG_MALI_T6XX_DVFS */ +#endif /* CONFIG_MALI_MIDGARD_DVFS */ /* Disable power */ kbase_platform_cmu_pmu_control(kbdev, 0); @@ -1527,14 +1301,14 @@ void kbase_platform_term(kbase_device *kbdev) #ifdef CONFIG_REGULATOR static struct regulator *g3d_regulator=NULL; -#ifdef CONFIG_T6XX_HWVER_R0P0 +#ifdef CONFIG_MIDGARD_HWVER_R0P0 static int mali_gpu_vol = 1250000; /* 1.25V @ 533 MHz */ #else static int mali_gpu_vol = 1050000; /* 1.05V @ 266 MHz */ -#endif /* CONFIG_T6XX_HWVER_R0P0 */ +#endif /* CONFIG_MIDGARD_HWVER_R0P0 */ #endif /* CONFIG_REGULATOR */ -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS /* * Weighted moving average support for signed integer data * with 7-bits of precision (not currently used; all data @@ -1641,19 +1415,6 @@ static void mali_dvfs_event_proc(struct work_struct *w) (exynos_result_of_asv & 0xf); dvfs_status.asv_need_update = DVFS_NOT_UPDATE_ASV_TBL; } - } else if (soc_is_exynos5420()) { -#ifdef CONFIG_ARM_EXYNOS5420_ASV - int i; - unsigned int asv_volt; - - for (i = 0; i < MALI_DVFS_STEP; i++) { - asv_volt = get_match_volt(ID_G3D, - mali_dvfs_infotbl_exynos5420[i].clock - / 1000); - if (asv_volt) - mali_dvfs_infotbl[i].voltage = asv_volt; - } -#endif } #endif spin_unlock_irqrestore(&mali_dvfs_spinlock, irqflags); @@ -1718,6 +1479,29 @@ int kbase_platform_dvfs_get_control_status(void) return mali_dvfs_control; } + +static void mali_dvfs_infotbl_init_exynos542x(kbase_device *kbdev) +{ + int i; + + if (soc_is_exynos5420()) + mali_dvfs_infotbl = mali_dvfs_infotbl_exynos5420; + else + mali_dvfs_infotbl = mali_dvfs_infotbl_exynos5422; + + for (i = 0; i < MALI_DVFS_STEP; i++) { + unsigned int asv_volt; +#ifdef CONFIG_ARM_EXYNOS5420_ASV + asv_volt = get_match_volt(ID_G3D, + mali_dvfs_infotbl[i].clock / 1000); +#else + asv_volt = 0; +#endif + if (asv_volt) + mali_dvfs_infotbl[i].voltage = asv_volt; + } +} + int kbase_platform_dvfs_init(kbase_device *kbdev) { unsigned long irqflags; @@ -1751,8 +1535,8 @@ int kbase_platform_dvfs_init(kbase_device *kbdev) mali_dvfs_asv_vol_tbl_special_exynos5250; mali_dvfs_asv_vol_tbl = mali_dvfs_asv_vol_tbl_exynos5250; #endif - } else if (soc_is_exynos5420()) - mali_dvfs_infotbl = mali_dvfs_infotbl_exynos5420; + } else if (soc_is_exynos542x()) + mali_dvfs_infotbl_init_exynos542x(kbdev); spin_unlock_irqrestore(&mali_dvfs_spinlock, irqflags); @@ -1766,12 +1550,12 @@ void kbase_platform_dvfs_term(void) mali_dvfs_wq = NULL; } -#endif /* CONFIG_MALI_T6XX_DVFS */ +#endif /* CONFIG_MALI_MIDGARD_DVFS */ int kbase_platform_dvfs_event(struct kbase_device *kbdev, u32 utilisation) { -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS unsigned long irqflags; spin_lock_irqsave(&mali_dvfs_spinlock, irqflags); @@ -1859,7 +1643,7 @@ int kbase_platform_get_default_voltage(struct device *dev, int *vol) return 0; } -#ifdef CONFIG_MALI_T6XX_DEBUG_SYS +#ifdef CONFIG_MALI_MIDGARD_DEBUG_SYS int kbase_platform_get_voltage(struct device *dev, int *vol) { #ifdef CONFIG_REGULATOR @@ -1875,9 +1659,9 @@ int kbase_platform_get_voltage(struct device *dev, int *vol) #endif /* CONFIG_REGULATOR */ return 0; } -#endif /* CONFIG_MALI_T6XX_DEBUG_SYS */ +#endif /* CONFIG_MALI_MIDGARD_DEBUG_SYS */ -#ifdef CONFIG_MALI_T6XX_DVFS +#ifdef CONFIG_MALI_MIDGARD_DVFS static int kbase_platform_set_voltage(struct device *dev, int vol) { #ifdef CONFIG_REGULATOR @@ -1903,8 +1687,7 @@ static void kbase_platform_dvfs_set_clock(kbase_device *kbdev, int freq) static struct clk * fout_gpll = NULL; static int _freq = -1; static unsigned long gpll_rate_prev = 0; - unsigned long gpll_rate = 0, aclk_400_rate = 0; - unsigned long tmp = 0; + unsigned long gpll_rate = 0; struct exynos_context *platform; unsigned int i = MALI_DVFS_STEP; @@ -1923,7 +1706,7 @@ static void kbase_platform_dvfs_set_clock(kbase_device *kbdev, int freq) mout_gpll = clk_get(kbdev->dev, "mout_gpll"); fin_gpll = clk_get(kbdev->dev, "ext_xtal"); fout_gpll = clk_get(kbdev->dev, "fout_gpll"); - } else if (soc_is_exynos5420()) { + } else if (soc_is_exynos542x()) { mout_gpll = clk_get(kbdev->dev, "mout_vpll"); fin_gpll = clk_get(kbdev->dev, "ext_xtal"); fout_gpll = clk_get(kbdev->dev, "fout_vpll"); @@ -1938,21 +1721,15 @@ static void kbase_platform_dvfs_set_clock(kbase_device *kbdev, int freq) trace_mali_dvfs_set_clock(freq); for (i = 0; i < MALI_DVFS_STEP; i++) - if (freq == mali_dvfs_infotbl[i].clock) { - gpll_rate = freq; - aclk_400_rate = freq; + if (freq == mali_dvfs_infotbl[i].clock) break; - } if (i == MALI_DVFS_STEP) return; + gpll_rate = freq; + /* if changed the GPLL rate, set rate for GPLL and wait for lock time */ if( gpll_rate != gpll_rate_prev) { - /*for stable clock input.*/ - if (soc_is_exynos5250()) - clk_set_rate(platform->sclk_g3d, 100000000); - else if (soc_is_exynos5420()) - clk_set_rate(platform->sclk_g3d, 100000000); clk_set_parent(mout_gpll, fin_gpll); /*change gpll*/ @@ -1964,15 +1741,10 @@ static void kbase_platform_dvfs_set_clock(kbase_device *kbdev, int freq) } _freq = freq; - clk_set_rate(platform->sclk_g3d, aclk_400_rate); - /* Waiting for clock is stable */ - do { - tmp = __raw_readl(/*EXYNOS5_CLKDIV_STAT_TOP0*/EXYNOS_CLKREG(0x10610)); - } while (tmp & 0x1000000); #if MALI_DVFS_DEBUG printk(KERN_DEBUG "dvfs_set_clock GPLL : %lu, ACLK_400 : %luMhz\n", - gpll_rate, aclk_400_rate); + gpll_rate, clk_get_rate(platform->sclk_g3d)); #endif /* MALI_DVFS_DEBUG */ return; } @@ -2024,7 +1796,26 @@ static void kbase_platform_dvfs_set_level(kbase_device *kbdev, int level) } level_prev = level; } -#endif /* CONFIG_MALI_T6XX_DVFS */ + +static void kbase_platform_dvfs_set_max(kbase_device *kbdev) +{ + int i, level; + + /* + * Firmware may initialize the GPU clocks at a rate higher than the + * one we suspended at. Set the maximum frequency and voltage at + * suspend time so that we don't under-volt the GPU during resume. + */ + for (i = 0; i < MALI_DVFS_STEP; i++) + if (mali_dvfs_infotbl[i].max_threshold == 100) { + level = i; + break; + } + + kbase_platform_dvfs_set_level(kbdev, level); + mali_dvfs_status_current.step = level; +} +#endif /* CONFIG_MALI_MIDGARD_DVFS */ #ifdef MALI_DVFS_ASV_ENABLE static int kbase_platform_asv_set(int enable) @@ -2043,7 +1834,7 @@ static int kbase_platform_asv_set(int enable) } #endif /* MALI_DVFS_ASV_ENABLE */ -#if defined (CONFIG_MALI_HWC_TRACE) && defined (CONFIG_MALI_T6XX_DEBUG_SYS) +#if defined (CONFIG_MALI_HWC_TRACE) && defined (CONFIG_MALI_MIDGARD_DEBUG_SYS) /* * Mali hardware performance counter trace support. Each counter * has a corresponding trace event. To use, enable events and write @@ -2322,6 +2113,7 @@ struct mali_hwcounter_state { kbase_uk_hwcnt_setup setup; /* hwcounter setup block */ bool active; /* collecting data */ u32 last_read[MALI_HWC_TOTAL]; /* last counter value read */ + kbase_hwc_dma_mapping handle; /* counter data buffer handle */ }; static struct mali_hwcounter_state mali_hwcs; static struct mutex mali_hwcounter_mutex; @@ -2707,7 +2499,8 @@ static int mali_hwcounter_polling_start(struct kbase_device *kbdev) return -ENOSPC; } mali_hwcs.buf = kbase_va_alloc(mali_hwcs.ctx, - MALI_HWC_DUMP_SIZE); + MALI_HWC_DUMP_SIZE, + &mali_hwcs.handle); mali_hwcs.setup.dump_buffer = (uintptr_t) mali_hwcs.buf; error = kbase_instr_hwcnt_enable(mali_hwcs.ctx, @@ -2715,7 +2508,7 @@ static int mali_hwcounter_polling_start(struct kbase_device *kbdev) if (error != MALI_ERROR_NONE) { pr_err("%s: cannot enable hw counters\n", __func__); - kbase_va_free(mali_hwcs.ctx, mali_hwcs.buf); + kbase_va_free(mali_hwcs.ctx, &mali_hwcs.handle); mali_hwcs.buf = NULL; kbase_destroy_context(mali_hwcs.ctx); @@ -2748,7 +2541,7 @@ static void mali_hwcounter_polling_stop(struct kbase_device *kbdev) kbase_instr_hwcnt_disable(mali_hwcs.ctx); - kbase_va_free(mali_hwcs.ctx, mali_hwcs.buf); + kbase_va_free(mali_hwcs.ctx, &mali_hwcs.handle); mali_hwcs.buf = NULL; kbase_destroy_context(mali_hwcs.ctx); @@ -2807,4 +2600,4 @@ static void mali_cleanup_system_tracing(struct device *dev) device_remove_file(dev, &dev_attr_hwc_enable); mutex_destroy(&mali_hwcounter_mutex); } -#endif /* CONFIG_MALI_HWC_TRACE && CONFIG_MALI_T6XX_DEBUG_SYS */ +#endif /* CONFIG_MALI_HWC_TRACE && CONFIG_MALI_MIDGARD_DEBUG_SYS */ diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 5eefd8813f0..a122e865e63 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -178,7 +178,11 @@ /* mux clocks */ #define CLK_MOUT_HDMI 640 - +#define CLK_MOUT_G3Di 641 +#define CLK_MOUT_VPLL 642 +#define CLK_MOUT_MAUDIO0 643 +#define CLK_MOUT_USER_ACLK333 644 +#define CLK_MOUT_SW_ACLK333 645 /* divider clocks */ #define CLK_DOUT_PIXEL 768 -- cgit v1.2.3