From db0fe532db3f60c93147514adfd1765894ea501e Mon Sep 17 00:00:00 2001 From: Richard Kuo Date: Sun, 28 Oct 2012 19:54:37 -0500 Subject: Hexagon: add support for additional exceptions Add multi-reg-write and unaligned-PC exceptions. Signed-off-by: Richard Kuo --- arch/hexagon/kernel/traps.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/hexagon/kernel') diff --git a/arch/hexagon/kernel/traps.c b/arch/hexagon/kernel/traps.c index d59ee62f772..12164a30e8f 100644 --- a/arch/hexagon/kernel/traps.c +++ b/arch/hexagon/kernel/traps.c @@ -65,6 +65,10 @@ static const char *ex_name(int ex) return "Write protection fault"; case HVM_GE_C_XMAL: return "Misaligned instruction"; + case HVM_GE_C_WREG: + return "Multiple writes to same register in packet"; + case HVM_GE_C_PCAL: + return "Program counter values that are not properly aligned"; case HVM_GE_C_RMAL: return "Misaligned data load"; case HVM_GE_C_WMAL: @@ -324,6 +328,12 @@ void do_genex(struct pt_regs *regs) case HVM_GE_C_XMAL: misaligned_instruction(regs); break; + case HVM_GE_C_WREG: + illegal_instruction(regs); + break; + case HVM_GE_C_PCAL: + misaligned_instruction(regs); + break; case HVM_GE_C_RMAL: misaligned_data_load(regs); break; -- cgit v1.2.3