From 404525d5a7ecc847b5ac178dad96402f1e102ccc Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 16 Nov 2012 21:21:43 +0100 Subject: clk: sunxi: Add dummy fixed rate clock for Allwinner A1X SoCs Signed-off-by: Maxime Ripard Cc: Mike Turquette --- drivers/clk/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/Makefile') diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 71a25b91de0..9c300a828ed 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -19,6 +19,7 @@ endif obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o +obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o # Chip specific obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o -- cgit v1.2.3