From 527fad1bc519df8eedd397482febb51526e5d987 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 12 Feb 2013 20:47:59 +0530 Subject: clk: tegra: initialise parent of uart clocks Initialise the parent of UARTs to PLLP and disabling clock by default. Signed-off-by: Laxman Dewangan Acked-by: Mike Turquette Signed-off-by: Stephen Warren --- drivers/clk/tegra/clk-tegra20.c | 7 +++++-- drivers/clk/tegra/clk-tegra30.c | 6 +++++- 2 files changed, 10 insertions(+), 3 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 3d706349df3..143ce1f899a 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1254,8 +1254,11 @@ static __initdata struct tegra_clk_init_table init_table[] = { {csite, clk_max, 0, 1}, {emc, clk_max, 0, 1}, {cclk, clk_max, 0, 1}, - {uarta, pll_p, 0, 1}, - {uartd, pll_p, 0, 1}, + {uarta, pll_p, 0, 0}, + {uartb, pll_p, 0, 0}, + {uartc, pll_p, 0, 0}, + {uartd, pll_p, 0, 0}, + {uarte, pll_p, 0, 0}, {usbd, clk_max, 12000000, 0}, {usb2, clk_max, 12000000, 0}, {usb3, clk_max, 12000000, 0}, diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index bfe3dd4fe84..32c61cb6d0b 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1877,7 +1877,11 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { }; static __initdata struct tegra_clk_init_table init_table[] = { - {uarta, pll_p, 408000000, 1}, + {uarta, pll_p, 408000000, 0}, + {uartb, pll_p, 408000000, 0}, + {uartc, pll_p, 408000000, 0}, + {uartd, pll_p, 408000000, 0}, + {uarte, pll_p, 408000000, 0}, {pll_a, clk_max, 564480000, 1}, {pll_a_out0, clk_max, 11289600, 1}, {extern1, pll_a_out0, 0, 1}, -- cgit v1.2.3