From 6ec3240047ee6a4b34f90d45e19ed179bc9b4a2e Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 6 May 2013 15:11:11 -0600 Subject: clk: tegra: add ac97 controller clock AC97 controller clock is hardwired to pll_a_out0. Signed-off-by: Lucas Stach Acked-by: Peter De Schrijver Reviewed-by: Prashant Gaikwad Acked-by: Mike Turquette Tested-by: Stephen Warren Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- drivers/clk/tegra/clk-tegra20.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index d80c7cc2358..075db0c99ed 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -872,6 +872,14 @@ static void __init tegra20_periph_clk_init(void) struct clk *clk; int i; + /* ac97 */ + clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", + TEGRA_PERIPH_ON_APB, + clk_base, 0, 3, &periph_l_regs, + periph_clk_enb_refcnt); + clk_register_clkdev(clk, NULL, "tegra20-ac97"); + clks[ac97] = clk; + /* apbdma */ clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, 0, 34, &periph_h_regs, -- cgit v1.2.3