From 02416dcf5a94af34bcd28b4baf25bbbf399d8136 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 15 Jun 2005 13:00:12 +0000 Subject: Redo RM9000 workaround which along with other DSP ASE changes was causing some headache for debuggers knowing about signal frames. Signed-off-by: Ralf Baechle --- include/asm-mips/cpu-features.h | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'include/asm-mips/cpu-features.h') diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 4930824a43a..bb2212cf460 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -109,17 +109,6 @@ #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #endif -/* - * Certain CPUs may throw bizarre exceptions if not the whole cacheline - * contains valid instructions. For these we ensure proper alignment of - * signal trampolines and pad them to the size of a full cache lines with - * nops. This is also used in structure definitions so can't be a test macro - * like the others. - */ -#ifndef PLAT_TRAMPOLINE_STUFF_LINE -#define PLAT_TRAMPOLINE_STUFF_LINE 0UL -#endif - #ifdef CONFIG_32BIT # ifndef cpu_has_nofpuex # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) -- cgit v1.2.3