From 3c36cc688e7ad4ab595a0ac59697e4e1d06338c5 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 26 May 2010 11:38:19 +0300 Subject: ASoC: TWL4030: Correct the ARXR2_APGA_CTL chip default It seams at least on twl5031 that the ARXR2_APGA_CTL register does not have the same default value as it is written in the TRM. Since the codec part of the PM chip has not been actually changed according to TI, assuming, that all version has the same problem, so writing there the TRM value. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- sound/soc/codecs/twl4030.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'sound/soc/codecs/twl4030.c') diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index 30b7bbaf6ae..c667ca5a8a9 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c @@ -289,6 +289,9 @@ static void twl4030_init_chip(struct platform_device *pdev) TWL4030_ATXL1_EN | TWL4030_ATXR1_EN | TWL4030_ARXL2_EN | TWL4030_ARXR2_EN); + /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */ + twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32); + /* Machine dependent setup */ if (!setup) return; -- cgit v1.2.3