aboutsummaryrefslogtreecommitdiff
path: root/drivers/net/wireless/iwlwifi/iwl-io.c
blob: e2e3b5c9cf7fb411fb6f22c86138fda0b4ebcb4d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
/******************************************************************************
 *
 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
 *
 * Portions of this file are derived from the ipw3945 project.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 *****************************************************************************/
#include <linux/delay.h>
#include <linux/device.h>

#include "iwl-io.h"
#include"iwl-csr.h"
#include "iwl-debug.h"

#define IWL_POLL_INTERVAL 10	/* microseconds */

static inline void __iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
{
	iwl_write32(trans, reg, iwl_read32(trans, reg) | mask);
}

static inline void __iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
{
	iwl_write32(trans, reg, iwl_read32(trans, reg) & ~mask);
}

void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
{
	unsigned long flags;

	spin_lock_irqsave(&trans->reg_lock, flags);
	__iwl_set_bit(trans, reg, mask);
	spin_unlock_irqrestore(&trans->reg_lock, flags);
}

void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
{
	unsigned long flags;

	spin_lock_irqsave(&trans->reg_lock, flags);
	__iwl_clear_bit(trans, reg, mask);
	spin_unlock_irqrestore(&trans->reg_lock, flags);
}

int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
		 u32 bits, u32 mask, int timeout)
{
	int t = 0;

	do {
		if ((iwl_read32(trans, addr) & mask) == (bits & mask))
			return t;
		udelay(IWL_POLL_INTERVAL);
		t += IWL_POLL_INTERVAL;
	} while (t < timeout);

	return -ETIMEDOUT;
}

int iwl_grab_nic_access_silent(struct iwl_trans *trans)
{
	int ret;

	lockdep_assert_held(&trans->reg_lock);

	/* this bit wakes up the NIC */
	__iwl_set_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);

	/*
	 * These bits say the device is running, and should keep running for
	 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
	 * but they do not indicate that embedded SRAM is restored yet;
	 * 3945 and 4965 have volatile SRAM, and must save/restore contents
	 * to/from host DRAM when sleeping/waking for power-saving.
	 * Each direction takes approximately 1/4 millisecond; with this
	 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
	 * series of register accesses are expected (e.g. reading Event Log),
	 * to keep device from sleeping.
	 *
	 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
	 * SRAM is okay/restored.  We don't check that here because this call
	 * is just for hardware register access; but GP1 MAC_SLEEP check is a
	 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
	 *
	 * 5000 series and later (including 1000 series) have non-volatile SRAM,
	 * and do not save/restore SRAM when power cycling.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
			   (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
			    CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
	if (ret < 0) {
		iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
		return -EIO;
	}

	return 0;
}

int iwl_grab_nic_access(struct iwl_trans *trans)
{
	int ret = iwl_grab_nic_access_silent(trans);
	if (ret) {
		u32 val = iwl_read32(trans, CSR_GP_CNTRL);
		IWL_ERR(trans,
			"MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
	}

	return ret;
}

void iwl_release_nic_access(struct iwl_trans *trans)
{
	lockdep_assert_held(&trans->reg_lock);
	__iwl_clear_bit(trans, CSR_GP_CNTRL,
			CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
}

u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
{
	u32 value;
	unsigned long flags;

	spin_lock_irqsave(&trans->reg_lock, flags);
	iwl_grab_nic_access(trans);
	value = iwl_read32(trans, reg);
	iwl_release_nic_access(trans);
	spin_unlock_irqrestore(&trans->reg_lock, flags);

	return value;
}

void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
{
	unsigned long flags;

	spin_lock_irqsave(&trans->reg_lock, flags);
	if (!iwl_grab_nic_access(trans)) {
		iwl_write32(trans, reg, value);
		iwl_release_nic_access(trans);
	}
	spin_unlock_irqrestore(&trans->reg_lock, flags);
}

int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
			int timeout)
{
	int t = 0;

	do {
		if ((iwl_read_direct32(trans, addr) & mask) == mask)
			return t;
		udelay(IWL_POLL_INTERVAL);
		t += IWL_POLL_INTERVAL;
	} while (t < timeout);

	return -ETIMEDOUT;
}

static inline u32 __iwl_read_prph(struct iwl_trans *trans, u32 reg)
{
	iwl_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
	rmb();
	return iwl_read32(trans, HBUS_TARG_PRPH_RDAT);
}

static inline void __iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
{
	iwl_write32(trans, HBUS_TARG_PRPH_WADDR,
		    ((addr & 0x0000FFFF) | (3 << 24)));
	wmb();
	iwl_write32(trans, HBUS_TARG_PRPH_WDAT, val);
}

u32 iwl_read_prph(struct iwl_trans *trans, u32 reg)
{
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&trans->reg_lock, flags);
	iwl_grab_nic_access(trans);
	val = __iwl_read_prph(trans, reg);
	iwl_release_nic_access(trans);
	spin_unlock_irqrestore(&trans->reg_lock, flags);
	return val;
}

void iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&trans->reg_lock, flags);
	if (!iwl_grab_nic_access(trans)) {
		__iwl_write_prph(trans, addr, val);
		iwl_release_nic_access(trans);
	}
	spin_unlock_irqrestore(&trans->reg_lock, flags);
}

void iwl_set_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
{
	unsigned long flags;

	spin_lock_irqsave(&trans->reg_lock, flags);
	iwl_grab_nic_access(trans);
	__iwl_write_prph(trans, reg, __iwl_read_prph(trans, reg) | mask);
	iwl_release_nic_access(trans);
	spin_unlock_irqrestore(&trans->reg_lock, flags);
}

void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 reg,
			    u32 bits, u32 mask)
{
	unsigned long flags;

	spin_lock_irqsave(&trans->reg_lock, flags);
	iwl_grab_nic_access(trans);
	__iwl_write_prph(trans, reg,
			 (__iwl_read_prph(trans, reg) & mask) | bits);
	iwl_release_nic_access(trans);
	spin_unlock_irqrestore(&trans->reg_lock, flags);
}

void iwl_clear_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
{
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&trans->reg_lock, flags);
	iwl_grab_nic_access(trans);
	val = __iwl_read_prph(trans, reg);
	__iwl_write_prph(trans, reg, (val & ~mask));
	iwl_release_nic_access(trans);
	spin_unlock_irqrestore(&trans->reg_lock, flags);
}

void _iwl_read_targ_mem_words(struct iwl_trans *trans, u32 addr,
			      void *buf, int words)
{
	unsigned long flags;
	int offs;
	u32 *vals = buf;

	spin_lock_irqsave(&trans->reg_lock, flags);
	iwl_grab_nic_access(trans);

	iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
	rmb();

	for (offs = 0; offs < words; offs++)
		vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);

	iwl_release_nic_access(trans);
	spin_unlock_irqrestore(&trans->reg_lock, flags);
}

u32 iwl_read_targ_mem(struct iwl_trans *trans, u32 addr)
{
	u32 value;

	_iwl_read_targ_mem_words(trans, addr, &value, 1);

	return value;
}

int _iwl_write_targ_mem_words(struct iwl_trans *trans, u32 addr,
				void *buf, int words)
{
	unsigned long flags;
	int offs, result = 0;
	u32 *vals = buf;

	spin_lock_irqsave(&trans->reg_lock, flags);
	if (!iwl_grab_nic_access(trans)) {
		iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
		wmb();

		for (offs = 0; offs < words; offs++)
			iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]);
		iwl_release_nic_access(trans);
	} else
		result = -EBUSY;
	spin_unlock_irqrestore(&trans->reg_lock, flags);

	return result;
}

int iwl_write_targ_mem(struct iwl_trans *trans, u32 addr, u32 val)
{
	return _iwl_write_targ_mem_words(trans, addr, &val, 1);
}