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All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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Previous patches fixed endian neutral issues in Arndale BSP, so mark it as one
that supports big endian
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
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Samsung serial driver uses __set_bit and __clear_bit functions directly with
h/w registers. But these functions are not endian neutral. In case of BE host
before operation on the bit byte swap is needed and byte swap is required
after operation on the bit is complete. Patch creates and use __hw_set_bit
and __hw_clear_bit, that in case of LE just call __set_bit and __clear_bit,
but in case of BE they do required byteswaps
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
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If kernel operates in BE mode on board that has LE bootloader/rom code, we need
to switch CPU to operate in BE mode as soon as possible. generic
secondary_startup that is called from exynos specific secondary startup code
will do the switch, but we need it to do earlier because exynos specific
secondary_startup code works with BE data.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
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uncompress serial line write utils need to use endian neutral functions to
read h/w register - i.e in case of BE host byteswap is needed. Fix uart_rd,
uart_wr and serial chip fifo related macros
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
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Need to use endian neutral functions to read/write LE h/w registers. I.e
instead of __raw_read[lw] and _raw_write[lw] functions code need to use
read[lw]_relaxed and write[lw]_relaxed functions. If the first just
read/write register with memory barrier, the second will byteswap it if host
operates in BE mode.
This patch covers drivers used by arndale board where all changes are trivial,
sed like replacement of __raw_xxx functions with xxx_relaxed variant.
Literally this sed program was used to make the change:
s|__raw_readl|readl_relaxed|g
s|__raw_writel|writel_relaxed|g
s|__raw_readw|readw_relaxed|g
s|__raw_writew|writew_relaxed|g
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
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Need to use endian neutral functions to read/write h/w registers. I.e
__raw_readl replaced with readl_relaxed and __raw_writel replaced with
writel_relaxed. The relaxed version of function will read/write LE h/w
register and byteswap it if host operates in BE mode.
However in case of this file __raw_read(wlq) and __raw_write(wlq) are also
used to transfer data from uchar buffer into h/w mmc host register. And in
this case byteswap is not need - bytes of data buffer should go into h/w
register in the same order as they are in memory. So we need to split control
mci_readl/mci_writel macros from one that operates on data mci_readw_data,
mci_readl_data, mci_readq_data, mci_writew, mci_writel_data, mci_writeq_data.
The latter one do not do byte swaps.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
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Need to use endian neutral functions to read/write LE h/w registers. I.e
insted of __raw_readl and _raw_writel, readl_relaxed and writel_relaxed. If
the first just read/write register with memory barrier, the second will
byteswap it if host operates in BE mode.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
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sclk_usbphy3* are the operational clocks used by USB 3.0 PHY
on exynos5420 platform, but the same are not handled by the
phy-samsung-usb3 driver. So enable the gates for these
sclk_usbphy3* for now to make USB 3.0 ports present on
smdk5420 working.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Adding required DT nodes to enable support for USB 2.0 (EHCI/OHCI)
and USB 3.0 (DWC3) on exynos5420 platform.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Multiple USB-PHY controllers shall be identofied by their aliases,
thereby making it possible to use the alias numbers as channel numbers
for USB 3.0 PHY controllers.
Based on this corresponding PHYs can be powered.
This patch also updates binding documentation samsung-usbphy for alias
numbers.
BUG=chrome-os-partner:19007
TEST=build and boot on smdk5420 and peach pit;
tested usb HID devices and mass storage devices on
USB 2.0 and USB 3.0 ports.
Change-Id: I0afdd1edd0093957d361f7f926c6b4526664e121
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/56398
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Adding another device-id for exynos-5420 type SoC, to facilitate
separate driver data.
BUG=chrome-os-partner:19007
TEST=build and boot on smdk5420 and peach pit;
tested usb HID devices and mass storage devices on
USB 2.0 and USB 3.0 ports.
Change-Id: I9381d40b254cfc6a297c4e5a714c3ab7e31f5f20
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/56397
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Adding another device-id for exynos-5420 type SoC, to facilitate
separate driver data.
BUG=chrome-os-partner:19007
TEST=build and boot on smdk5420 and peach pit;
tested usb HID devices and mass storage devices on
USB 2.0 and USB 3.0 ports.
Change-Id: I127d382982da88caeef4f2878e4d89c6c67fac67
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/56396
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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The serial driver never releases the interrupt on shutdown, but it does
repeatedly acquire it on startup.
$ cat /proc/interrupts
85: 69 0 GIC exynos4210-uart.2, exynos4210-uart.2, exynos4210-uart.2
Signed-off-by: Michael O'Reilly <m@dgmo.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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This patchset integrate the SATA patches submitted by Vasanth Ananthan.
In addition to that SATA and SATA PHY driver will use common clock
framework API.
Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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This patchset integrate the SATA patches submitted by Vasanth Ananthan.
In addition to that SATA and SATA PHY driver will use common clock
framework API.
Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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The probe function of SATA phy driver is being accessed later in SATA
probe. But it gets poisoned memory during that time. Suspecting
__init attribute to be the culprit.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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This patch adds a platform driver and I2C client driver for SATA PHY controller
Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
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This patch adds a platform driver for SATA controller.
Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
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This patch adds SATA PHY utility framework APIs. The framework acts as an
interface between the SATA device and the PHY device. The SATA PHY device
registers itself with the framework through the APIs provided and the SATA
device finds and requests for an appropriate PHY device.
Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
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This patch adds Device Nodes for SATA and SATA PHY device.
Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
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Currently DRM driver doesn't handle deferred probe properly. If
the regulators are not found during HDMI probe, it doesn't retry
later. Since I2C controller is registered as a module driver, the
PMIC client driver also gets registered later. In current build-order,
DRM drivers are registered before the PMIC driver, hence causing
this failure.
The regulators are always-enabled and the regulator operations
from driver is removed.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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display_pd is affecting HDMI/Mixer functionality. Till appropriate
handles are added in driver code, comment this pd definition.
Additionally disable mau_pd for Audio functionality.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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hdmiphy dt node needs a child node called 'phy-power-control'
which represents the PMU register for power controlling the
hdmiphy.
hdmi driver dt node provides phy property which points to
the hdmiphy dt node.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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hdmiphy dt node needs a child node called 'phy-power-control'
which represents the PMU register for power controlling the
hdmiphy.
hdmi driver dt node provides phy property which points to
the hdmiphy dt node.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Add hdmiphy power control node as a child to hdmi node. This
node will be parsed by hdmi driver to map phy control pmu reg and
control the phy power.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Exynos hdmi ddc is a I2C device and if we register hdmi ddc
driver with id_table as NULL, cause failure in probing.
id_table field should not be NULL for i2c_driver registeration.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Before hdmiphy operation like config, start etc, hdmiphy
bit in PMU block should be enabled. Earlier this happens
in hdmi driver through a dummy "hdmiphy" clock.
Pmu bit control is added in both i2c and platform driver
for exynos hdmiphy.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Exynos5420 hdmiphy device is a platform device, unlike
predecessor SoCs where it used to be a I2C device. This
support is added to the hdmiphy platform driver.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Exynos hdmiphy operations and configs are kept inside
the hdmi driver. Hdmiphy related code is very tightly
coupled with hdmi IP driver.
This patch moves hdmiphy related code to hdmiphy I2C driver
which supports hdmiphys which are accessible through i2c
control bus for example in exynos4210, exynos4212 and
exynos5250.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Without this patch, HDMI monitor still displays data after shutdown.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Some boards set the coherent_dma_mask as 64 bits (while working
with LPAE). So we need to update coherent_dma_mask only if
it is not already set.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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HPD support is not working properly on Arndale board. Till the issue
is fixed, HPD support is disabled.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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While booting Exynos5420 based Arndale-Octa board, we are getting
a data abort as soon as we get the command prompt. This behaviour
has become extremely reproducible (avg. 9 out of 10 iterations)
since v3.14-rc1. Currently ignoring this fault so that the board
becomes usable again.
This is a work-around till the actual issue has been fixed.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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The Exynos 5250 includes an architected timer which is on core and
very cheap to read.
Enabling the architected timer can lead to a significant performance
improvement for timer sensitive workloads such as TCP/IP.
It turns out that both arch_sys_counter and mct-frc have a rating of
400. On bootup, arch_sys_counter is initialized first then the
clocksource changes to mct-frc when that initialises later on.
If the rating of mct-frc is reduced below 400, then arch_sys_counter
becomes the default.
Suggested-by: Steve Capper <steve.capper@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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In intial boot-up, u-boot commit "3d28a181aab5e... arndale5250: Boot in Hyp
mode and enable architected timers" puts the CPUs in HYP mode.
Hence, the CPUs need to be put in HYP mode when they are hot plugged out and
plugged back in.
This patch is almost same as above u-boot patch, it additionally takes care
if the kernel is compiled with thumb-2 option.
Signed-off-by: Giridhar Maruthy <giridhar.m@samsung.com>
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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As per commit b3377d186572 ("ARM: 7064/1: vexpress: Use wfi macro
in platform_do_lowpower."), wfi macro should be used instead
of the hardcoded WFI instruction.
This fixes following oops with a kernel compiled in Thumb-2 mode.
$ reboot
reboot
Disabling non-boot CPUs ...
IRQ153 no longer affine to CPU1
CPU1: shutdown
Internal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP THUMB2
Modules linked in:
CPU: 1 Not tainted (3.9.0-rc1-00015-gce76372 #1)
PC is at 0xc065858e
LR is at exynos_cpu_die+0x53/0xc0
Tested on EXYNOS5250 based Arndale board.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Added I2S nodes to Exynos5420 DT file.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Added ADMA mode to Exynos5420 DT file.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Enable stub audio card. Useful to get HDMI audio when no codec
is connected to the board.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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HDMI can be configured to source audio data from I2S bus. For boards
on which there are no external audio chips, we still need to create
a I2S-based soundcard with a dummy codec driver to enable I2S subsystem
to pump data to the I2S bus, which can be used by HDMI module.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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HDMI (in Samsung EXYNOS based SoCs) can be configured to source audio
data from I2S bus. For boards on which there are no external audio chips,
we still need to create a I2S-based soundcard with a dummy codec driver
to enable I2S subsystem to pump data to the I2S bus, which can be used
by HDMI module.
This patch adds a I2S stub audio codec driver which can be used to create
a I2S soundcard when external chip is not there.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Without this, we get following error.
sound/built-in.o: In function `dma_enqueue':
sound/soc/samsung/dma.c:79: undefined reference to `__aeabi_uldivmod'
sound/built-in.o: In function `iis_irq':
sound/soc/samsung/idma.c:285: undefined reference to `__aeabi_uldivmod'
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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In case there are multiple USB-Ethernet devices (through USB-Ethernet
dongles), then all of them used to get the same MAC address passed
from bootloader.
Reported-by: Fathi Boudra <fathi.boudra@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Inherited from arch/mips/rb532/devices.c
Example: bootargs="mac=00:40:5c:26:0a:5b"
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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