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Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Zhang Mingjun <zhang.mingjun@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Zhang Mingjun <zhang.mingjun@linaro.org>
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Support hi6421 rtc function.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Support Hi6421 PMIC powerkey driver.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Correct the register address of L2 controller in Hi3620 DTS file.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Enable PL310 L2 cache for Hi3xxx SoC.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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gpio-ranges property could binds gpio to pinctrl. But there may be some
gpios without pinctrl operation. So check whether gpio-ranges property
exists in device node first.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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If gpio base number isn't specified, the gpio base will be find from
the end of gpio number. In order to keep with schematics, add a new
property "linux,gpio-base" to specify the gpio number in DTS file.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
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touchscreen:
Device Drivers --->
Input device support --->
[*] Touchscreens --->
[*] Atmel mXT224E based touchscreens
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
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Add support to hi6421 regulators. Hi6421 is a multi-functional PMIC
manufactured by HiSilicon Inc.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Add support of HiSilicon Hi6421 in mfd. Hi6421 is a power management and
codec IC from HiSilicon Inc., which includes regulators, codec, ADCs,
Coulomb counter, etc. The way to communitcate with Hi6421 is through
memory mapped I/O ports.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Suggest by Arnd: abstract mmc tuning as clock behavior,
also because different soc have different tuning method and registers.
hi3620_mmc_clks is added to handle mmc clock specifically on hi3620.
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
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By default if no fill symbol is given to .align directive in a code
section it fills gap with NOPs. If previous fragment is not
instruction-aligned, additional pre-alignment is done by zero bytes
before NOPs. These zero bytes are marked as data by special symbol $d in
symbol table. Unfortunately GAS assumes that there is only code in the
code section so it "puts back" code symbol $a at the end of this
pre-alignment. So if there is some data after alignment it will be
interpreted as code and will be swapped back to LE for BE8 system during
a final linking.
If explicit fill value is given to .align, the NOP-padding code is
skipped and symbol table does not get messed-up.
So the workaround for this issue:
Use explicit fill value if data should be aligned in the code section.
Acked-by: Ben Dooks <ben.dooks@codethink.co.uk>
Acked-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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The kprobes test will build certain instructions incorrectly if building
big endian as .word/.short output gets endian-swapped by the linker.
Change to using <asm/opcodes.h> and __inst_thumbXX() to produce instructions.
Acked-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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The kprobes test will build certain instructions incorrectly if building
big endian as .word output gets endian-swapped by the linker. Change to
using <asm/opcodes.h> and __inst_arm() to produce instructions.
Acked-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
[taras.kondratiuk@linaro.org: fixed unsupported coprocessor instructions]
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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Ensure we read instructions in the correct endian-ness by using
the <asm/opcodes.h> helper to transform them as necessary.
Acked-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
[taras.kondratiuk@linaro.org: fix next_instruction() function]
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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If we are running BE8, the data and instruction endianness do not
match, so use <asm/opcodes.h> to correctly translate memory accesses
into ARM instructions.
Acked-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
[taras.kondratiuk@linaro.org: fixed Thumb instruction fetch order]
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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Previous patches fixed big endian issues in OMAP4 code,
so mark it as one that supports big endian
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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If kernel operates in BE mode on device that has LE bootloader/ROM code,
we need to switch CPU to operate in BE mode before it will start to
access BE data. Generic secondary_startup function that is called from
OMAP specific secondary startup code will do the switch, but we need
to do it earlier because OMAP's secondary_startup code works with BE data.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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Assembler functions defined in sleep44xx.S need to byteswap values
after read / before write from h/w register if code compiled in big
endian mode. Simple change to do 'rev x, x' before str instruction
and after ldr instruction that deals with h/w registers.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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Previous patches fixed endian neutral issues in Arndale BSP, so mark it as one
that supports big endian
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
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Samsung serial driver uses __set_bit and __clear_bit functions directly with
h/w registers. But these functions are not endian neutral. In case of BE host
before operation on the bit byte swap is needed and byte swap is required
after operation on the bit is complete. Patch creates and use __hw_set_bit
and __hw_clear_bit, that in case of LE just call __set_bit and __clear_bit,
but in case of BE they do required byteswaps
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
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If kernel operates in BE mode on board that has LE bootloader/rom code, we need
to switch CPU to operate in BE mode as soon as possible. generic
secondary_startup that is called from exynos specific secondary startup code
will do the switch, but we need it to do earlier because exynos specific
secondary_startup code works with BE data.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
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uncompress serial line write utils need to use endian neutral functions to
read h/w register - i.e in case of BE host byteswap is needed. Fix uart_rd,
uart_wr and serial chip fifo related macros
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
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Need to use endian neutral functions to read/write LE h/w registers. I.e
instead of __raw_read[lw] and _raw_write[lw] functions code need to use
read[lw]_relaxed and write[lw]_relaxed functions. If the first just
read/write register with memory barrier, the second will byteswap it if host
operates in BE mode.
This patch covers drivers used by arndale board where all changes are trivial,
sed like replacement of __raw_xxx functions with xxx_relaxed variant.
Literally this sed program was used to make the change:
s|__raw_readl|readl_relaxed|g
s|__raw_writel|writel_relaxed|g
s|__raw_readw|readw_relaxed|g
s|__raw_writew|writew_relaxed|g
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
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Need to use endian neutral functions to read/write h/w registers. I.e
__raw_readl replaced with readl_relaxed and __raw_writel replaced with
writel_relaxed. The relaxed version of function will read/write LE h/w
register and byteswap it if host operates in BE mode.
However in case of this file __raw_read(wlq) and __raw_write(wlq) are also
used to transfer data from uchar buffer into h/w mmc host register. And in
this case byteswap is not need - bytes of data buffer should go into h/w
register in the same order as they are in memory. So we need to split control
mci_readl/mci_writel macros from one that operates on data mci_readw_data,
mci_readl_data, mci_readq_data, mci_writew, mci_writel_data, mci_writeq_data.
The latter one do not do byte swaps.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
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Need to use endian neutral functions to read/write LE h/w registers. I.e
insted of __raw_readl and _raw_writel, readl_relaxed and writel_relaxed. If
the first just read/write register with memory barrier, the second will
byteswap it if host operates in BE mode.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
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sclk_usbphy3* are the operational clocks used by USB 3.0 PHY
on exynos5420 platform, but the same are not handled by the
phy-samsung-usb3 driver. So enable the gates for these
sclk_usbphy3* for now to make USB 3.0 ports present on
smdk5420 working.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Adding required DT nodes to enable support for USB 2.0 (EHCI/OHCI)
and USB 3.0 (DWC3) on exynos5420 platform.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Multiple USB-PHY controllers shall be identofied by their aliases,
thereby making it possible to use the alias numbers as channel numbers
for USB 3.0 PHY controllers.
Based on this corresponding PHYs can be powered.
This patch also updates binding documentation samsung-usbphy for alias
numbers.
BUG=chrome-os-partner:19007
TEST=build and boot on smdk5420 and peach pit;
tested usb HID devices and mass storage devices on
USB 2.0 and USB 3.0 ports.
Change-Id: I0afdd1edd0093957d361f7f926c6b4526664e121
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/56398
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Adding another device-id for exynos-5420 type SoC, to facilitate
separate driver data.
BUG=chrome-os-partner:19007
TEST=build and boot on smdk5420 and peach pit;
tested usb HID devices and mass storage devices on
USB 2.0 and USB 3.0 ports.
Change-Id: I9381d40b254cfc6a297c4e5a714c3ab7e31f5f20
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/56397
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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Adding another device-id for exynos-5420 type SoC, to facilitate
separate driver data.
BUG=chrome-os-partner:19007
TEST=build and boot on smdk5420 and peach pit;
tested usb HID devices and mass storage devices on
USB 2.0 and USB 3.0 ports.
Change-Id: I127d382982da88caeef4f2878e4d89c6c67fac67
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/56396
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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The serial driver never releases the interrupt on shutdown, but it does
repeatedly acquire it on startup.
$ cat /proc/interrupts
85: 69 0 GIC exynos4210-uart.2, exynos4210-uart.2, exynos4210-uart.2
Signed-off-by: Michael O'Reilly <m@dgmo.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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This patchset integrate the SATA patches submitted by Vasanth Ananthan.
In addition to that SATA and SATA PHY driver will use common clock
framework API.
Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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This patchset integrate the SATA patches submitted by Vasanth Ananthan.
In addition to that SATA and SATA PHY driver will use common clock
framework API.
Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
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