From a9eba86bf34290c9952245d9010cb79291c7cd20 Mon Sep 17 00:00:00 2001 From: "Yin, Fengwei" Date: Sun, 13 Sep 2015 22:00:06 +0800 Subject: Update the initialization sequence to enable DB410c. The soc on DB410c board is not same as MTP8916. It doesn't support 48M operation frequency. Signed-off-by: Yin, Fengwei --- drivers/net/wireless/ath/wcn36xx/wcnss_core.c | 32 +++++++++++++++++++++++---- drivers/net/wireless/ath/wcn36xx/wcnss_core.h | 3 +++ 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/net/wireless/ath/wcn36xx/wcnss_core.c b/drivers/net/wireless/ath/wcn36xx/wcnss_core.c index 66e31440f3c3..b3e4b826d887 100644 --- a/drivers/net/wireless/ath/wcn36xx/wcnss_core.c +++ b/drivers/net/wireless/ath/wcn36xx/wcnss_core.c @@ -15,7 +15,8 @@ static int wcnss_core_config(struct platform_device *pdev, void __iomem *base) { int ret = 0; - u32 value; + u32 value, iris_read = INVALID_IRIS_REG; + int clk_48m = 0; value = readl_relaxed(base + SPARE_OFFSET); value |= WCNSS_FW_DOWNLOAD_ENABLE; @@ -24,11 +25,34 @@ static int wcnss_core_config(struct platform_device *pdev, void __iomem *base) writel_relaxed(0, base + PMU_OFFSET); value = readl_relaxed(base + PMU_OFFSET); value |= WCNSS_PMU_CFG_GC_BUS_MUX_SEL_TOP | - WCNSS_PMU_CFG_IRIS_XO_EN; + WCNSS_PMU_CFG_IRIS_XO_EN; writel_relaxed(value, base + PMU_OFFSET); - value &= ~(WCNSS_PMU_CFG_IRIS_XO_MODE); - value |= WCNSS_PMU_CFG_IRIS_XO_MODE_48; + iris_read_v = readl_relaxed(base + IRIS_REG_OFFSET); + pr_info("iris_read_v: 0x%x\n", iris_read_v); + + iris_read_v &= 0xffff; + iris_read_v |= 0x04; + writel_relaxed(iris_read_v, base + IRIS_REG_OFFSET); + + value = readl_relaxed(base + PMU_OFFSET); + value |= WCNSS_PMU_CFG_IRIS_XO_READ; + writel_relaxed(value, base + PMU_OFFSET); + + while (readl_relaxed(base + PMU_OFFSET) & + WCNSS_PMU_CFG_IRIS_XO_READ_STS) + cpu_relax(); + + iris_read_v = readl_relaxed(base + 0x1134); + pr_info("wcnss: IRIS Reg: 0x%08x\n", iris_read_v); + clk_48m = (iris_read_v >> 30) ? 0 : 1; + value &= ~WCNSS_PMU_CFG_IRIS_XO_READ; + + /* XO_MODE[b2:b1]. Clear implies 19.2MHz */ + value &= ~WCNSS_PMU_CFG_IRIS_XO_MODE; + + if (clk_48m) + value |= WCNSS_PMU_CFG_IRIS_XO_MODE_48; writel_relaxed(value, base + PMU_OFFSET); diff --git a/drivers/net/wireless/ath/wcn36xx/wcnss_core.h b/drivers/net/wireless/ath/wcn36xx/wcnss_core.h index d81fc472f62f..4c3517b99c30 100644 --- a/drivers/net/wireless/ath/wcn36xx/wcnss_core.h +++ b/drivers/net/wireless/ath/wcn36xx/wcnss_core.h @@ -3,6 +3,9 @@ #define PMU_OFFSET 0x1004 #define SPARE_OFFSET 0x1088 +#define IRIS_REG_OFFSET 0x1134 + +#define INVALID_IRIS_REG 0xbaadbaad #define WCNSS_PMU_CFG_IRIS_XO_CFG BIT(3) #define WCNSS_PMU_CFG_IRIS_XO_EN BIT(4) -- cgit v1.2.3