path: root/arch/arm/boot/dts/qcom-msm8974.dtsi

/dts-v1/;

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include "skeleton.dtsi"

/ {
	model = "Qualcomm MSM8974";
	compatible = "qcom,msm8974";
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		smem_region: smem@fa00000 {
			reg = <0xfa00000 0x200000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <1 9 0xf04>;

		cpu0: cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
			clocks = <&kraitcc 0>;
			clock-names = "cpu";
			clock-latency = <100000>;
		};

		cpu1: cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
			clocks = <&kraitcc 1>;
			clock-names = "cpu";
			clock-latency = <100000>;
		};

		cpu2: cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
			clocks = <&kraitcc 2>;
			clock-names = "cpu";
			clock-latency = <100000>;
		};

		cpu3: cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
			clocks = <&kraitcc 3>;
			clock-names = "cpu";
			clock-latency = <100000>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			qcom,saw = <&saw_l2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <150>;
				exit-latency-us = <200>;
				min-residency-us = <2000>;
			};
		};
	};

	thermal-zones {
		cpu-thermal0 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 5>;

			trips {
				cpu_alert0: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit0: trip@1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu-thermal1 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 6>;

			trips {
				cpu_alert1: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit1: trip@1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu-thermal2 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 7>;

			trips {
				cpu_alert2: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit2: trip@1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu-thermal3 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 8>;

			trips {
				cpu_alert3: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit3: trip@1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 7 0xf04>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 4 0xf08>,
			     <1 1 0xf08>;
		clock-frequency = <19200000>;
	};

	qcom,pvs {
		qcom,pvs-format-b;
			/* Hz		uV	ua */
		qcom,speed0-pvs0-bin-v0 =
			<  300000000  815000  73 >,
			<  345600000  825000  85 >,
			<  422400000  835000 104 >,
			<  499200000  845000 124 >,
			<  576000000  855000 144 >,
			<  652800000  865000 165 >,
			<  729600000  875000 186 >,
			<  806400000  890000 208 >,
			<  883200000  900000 229 >,
			<  960000000  915000 252 >;

		qcom,speed0-pvs1-bin-v0 =
			<  300000000  800000  73 >,
			<  345600000  810000  85 >,
			<  422400000  820000 104 >,
			<  499200000  830000 124 >,
			<  576000000  840000 144 >,
			<  652800000  850000 165 >,
			<  729600000  860000 186 >,
			<  806400000  875000 208 >,
			<  883200000  885000 229 >,
			<  960000000  895000 252 >;

		qcom,speed0-pvs2-bin-v0 =
			<  300000000  785000  73 >,
			<  345600000  795000  85 >,
			<  422400000  805000 104 >,
			<  499200000  815000 124 >,
			<  576000000  825000 144 >,
			<  652800000  835000 165 >,
			<  729600000  845000 186 >,
			<  806400000  855000 208 >,
			<  883200000  865000 229 >,
			<  960000000  875000 252 >;

		qcom,speed0-pvs3-bin-v0 =
			<  300000000  775000  73 >,
			<  345600000  780000  85 >,
			<  422400000  790000 104 >,
			<  499200000  800000 124 >,
			<  576000000  810000 144 >,
			<  652800000  820000 165 >,
			<  729600000  830000 186 >,
			<  806400000  840000 208 >,
			<  883200000  850000 229 >,
			<  960000000  860000 252 >;

		qcom,speed0-pvs4-bin-v0 =
			<  300000000  775000  73 >,
			<  345600000  775000  85 >,
			<  422400000  780000 104 >,
			<  499200000  790000 124 >,
			<  576000000  800000 144 >,
			<  652800000  810000 165 >,
			<  729600000  820000 186 >,
			<  806400000  830000 208 >,
			<  883200000  840000 229 >,
			<  960000000  850000 252 >;

		qcom,speed0-pvs5-bin-v0 =
			<  300000000  750000  73 >,
			<  345600000  760000  85 >,
			<  422400000  770000 104 >,
			<  499200000  780000 124 >,
			<  576000000  790000 144 >,
			<  652800000  800000 165 >,
			<  729600000  810000 186 >,
			<  806400000  820000 208 >,
			<  883200000  830000 229 >,
			<  960000000  840000 252 >;

		qcom,speed0-pvs6-bin-v0 =
			<  300000000  750000  73 >,
			<  345600000  750000  85 >,
			<  422400000  760000 104 >,
			<  499200000  770000 124 >,
			<  576000000  780000 144 >,
			<  652800000  790000 165 >,
			<  729600000  800000 186 >,
			<  806400000  810000 208 >,
			<  883200000  820000 229 >,
			<  960000000  830000 252 >;

		qcom,speed2-pvs0-bin-v0 =
			<  300000000  800000  72 >,
			<  345600000  800000  83 >,
			<  422400000  805000 102 >,
			<  499200000  815000 121 >,
			<  576000000  825000 141 >,
			<  652800000  835000 161 >,
			<  729600000  845000 181 >,
			<  806400000  855000 202 >,
			<  883200000  865000 223 >,
			<  960000000  875000 245 >;

		qcom,speed2-pvs1-bin-v0 =
			<  300000000  800000  72 >,
			<  345600000  800000  83 >,
			<  422400000  800000 102 >,
			<  499200000  800000 121 >,
			<  576000000  810000 141 >,
			<  652800000  820000 161 >,
			<  729600000  830000 181 >,
			<  806400000  840000 202 >,
			<  883200000  850000 223 >,
			<  960000000  860000 245 >;

		qcom,speed2-pvs2-bin-v0 =
			<  300000000  775000  72 >,
			<  345600000  775000  83 >,
			<  422400000  775000 102 >,
			<  499200000  785000 121 >,
			<  576000000  795000 141 >,
			<  652800000  805000 161 >,
			<  729600000  815000 181 >,
			<  806400000  825000 202 >,
			<  883200000  835000 223 >,
			<  960000000  845000 245 >;

		qcom,speed2-pvs3-bin-v0 =
			<  300000000  775000  72 >,
			<  345600000  775000  83 >,
			<  422400000  775000 102 >,
			<  499200000  775000 121 >,
			<  576000000  780000 141 >,
			<  652800000  790000 161 >,
			<  729600000  800000 181 >,
			<  806400000  810000 202 >,
			<  883200000  820000 223 >,
			<  960000000  830000 245 >;

		qcom,speed2-pvs4-bin-v0 =
			<  300000000  775000  72 >,
			<  345600000  775000  83 >,
			<  422400000  775000 102 >,
			<  499200000  775000 121 >,
			<  576000000  775000 141 >,
			<  652800000  780000 161 >,
			<  729600000  790000 181 >,
			<  806400000  800000 202 >,
			<  883200000  810000 223 >,
			<  960000000  820000 245 >;

		qcom,speed2-pvs5-bin-v0 =
			<  300000000  750000  72 >,
			<  345600000  750000  83 >,
			<  422400000  750000 102 >,
			<  499200000  750000 121 >,
			<  576000000  760000 141 >,
			<  652800000  770000 161 >,
			<  729600000  780000 181 >,
			<  806400000  790000 202 >,
			<  883200000  800000 223 >,
			<  960000000  810000 245 >;

		qcom,speed2-pvs6-bin-v0 =
			<  300000000  750000  72 >,
			<  345600000  750000  83 >,
			<  422400000  750000 102 >,
			<  499200000  750000 121 >,
			<  576000000  750000 141 >,
			<  652800000  760000 161 >,
			<  729600000  770000 181 >,
			<  806400000  780000 202 >,
			<  883200000  790000 223 >,
			<  960000000  800000 245 >;

		qcom,speed1-pvs0-bin-v0 =
			<  300000000  775000  72 >,
			<  345600000  775000  83 >,
			<  422400000  775000 101 >,
			<  499200000  780000 120 >,
			<  576000000  790000 139 >,
			<  652800000  800000 159 >,
			<  729600000  810000 180 >,
			<  806400000  820000 200 >,
			<  883200000  830000 221 >,
			<  960000000  840000 242 >;

		qcom,speed1-pvs1-bin-v0 =
			<  300000000  775000  72 >,
			<  345600000  775000  83 >,
			<  422400000  775000 101 >,
			<  499200000  775000 120 >,
			<  576000000  775000 139 >,
			<  652800000  785000 159 >,
			<  729600000  795000 180 >,
			<  806400000  805000 200 >,
			<  883200000  815000 221 >,
			<  960000000  825000 242 >;

		qcom,speed1-pvs2-bin-v0 =
			<  300000000  750000  72 >,
			<  345600000  750000  83 >,
			<  422400000  750000 101 >,
			<  499200000  750000 120 >,
			<  576000000  760000 139 >,
			<  652800000  770000 159 >,
			<  729600000  780000 180 >,
			<  806400000  790000 200 >,
			<  883200000  800000 221 >,
			<  960000000  810000 242 >;

		qcom,speed1-pvs3-bin-v0 =
			<  300000000  750000  72 >,
			<  345600000  750000  83 >,
			<  422400000  750000 101 >,
			<  499200000  750000 120 >,
			<  576000000  750000 139 >,
			<  652800000  755000 159 >,
			<  729600000  765000 180 >,
			<  806400000  775000 200 >,
			<  883200000  785000 221 >,
			<  960000000  795000 242 >;

		qcom,speed1-pvs4-bin-v0 =
			<  300000000  750000  72 >,
			<  345600000  750000  83 >,
			<  422400000  750000 101 >,
			<  499200000  750000 120 >,
			<  576000000  750000 139 >,
			<  652800000  750000 159 >,
			<  729600000  755000 180 >,
			<  806400000  765000 200 >,
			<  883200000  775000 221 >,
			<  960000000  785000 242 >;

		qcom,speed1-pvs5-bin-v0 =
			<  300000000  725000  72 >,
			<  345600000  725000  83 >,
			<  422400000  725000 101 >,
			<  499200000  725000 120 >,
			<  576000000  725000 139 >,
			<  652800000  735000 159 >,
			<  729600000  745000 180 >,
			<  806400000  755000 200 >,
			<  883200000  765000 221 >,
			<  960000000  775000 242 >;

		qcom,speed1-pvs6-bin-v0 =
			<  300000000  725000  72 >,
			<  345600000  725000  83 >,
			<  422400000  725000 101 >,
			<  499200000  725000 120 >,
			<  576000000  725000 139 >,
			<  652800000  725000 159 >,
			<  729600000  735000 180 >,
			<  806400000  745000 200 >,
			<  883200000  755000 221 >,
			<  960000000  765000 242 >;
	};

	kraitcc: clock-controller {
		compatible = "qcom,krait-cc-v2";
		#clock-cells = <1>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@f9000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0xf9000000 0x1000>,
			      <0xf9002000 0x1000>;
		};

		qfprom: qfprom@fc4bc000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "qcom,qfprom";
			reg = <0xfc4bc000 0x1000>;
			tsens_calib: calib@d0 {
				reg = <0xd0 0x18>;
			};
			tsens_backup: backup@440 {
				reg = <0x440 0x10>;
			};
		};

		tsens: thermal-sensor@fc4a8000 {
			compatible = "qcom,msm8974-tsens";
			reg = <0xfc4a8000 0x2000>;
			nvmem-cells = <&tsens_calib>, <&tsens_backup>;
			nvmem-cell-names = "calib", "calib_backup";
			qcom,tsens-slopes = <3200 3200 3200 3200 3200 3200
				3200 3200 3200 3200 3200>;
			#thermal-sensor-cells = <1>;
		};

		timer@f9020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xf9020000 0x1000>;
			clock-frequency = <19200000>;

			frame@f9021000 {
				frame-number = <0>;
				interrupts = <0 8 0x4>,
					     <0 7 0x4>;
				reg = <0xf9021000 0x1000>,
				      <0xf9022000 0x1000>;
			};

			frame@f9023000 {
				frame-number = <1>;
				interrupts = <0 9 0x4>;
				reg = <0xf9023000 0x1000>;
				status = "disabled";
			};

			frame@f9024000 {
				frame-number = <2>;
				interrupts = <0 10 0x4>;
				reg = <0xf9024000 0x1000>;
				status = "disabled";
			};

			frame@f9025000 {
				frame-number = <3>;
				interrupts = <0 11 0x4>;
				reg = <0xf9025000 0x1000>;
				status = "disabled";
			};

			frame@f9026000 {
				frame-number = <4>;
				interrupts = <0 12 0x4>;
				reg = <0xf9026000 0x1000>;
				status = "disabled";
			};

			frame@f9027000 {
				frame-number = <5>;
				interrupts = <0 13 0x4>;
				reg = <0xf9027000 0x1000>;
				status = "disabled";
			};

			frame@f9028000 {
				frame-number = <6>;
				interrupts = <0 14 0x4>;
				reg = <0xf9028000 0x1000>;
				status = "disabled";
			};
		};

		saw0: power-controller@f9089000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
		};

		saw1: power-controller@f9099000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
		};

		saw2: power-controller@f90a9000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw3: power-controller@f90b9000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
		};

		clock-controller@f9016000 {
			compatible = "qcom,hfpll";
			reg = <0xf9016000 0x30>;
			clock-output-names = "hfpll_l2";
		};

		clock-controller@f908a000 {
			compatible = "qcom,hfpll";
			reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
			clock-output-names = "hfpll0";
		};

		clock-controller@f909a000 {
			compatible = "qcom,hfpll";
			reg = <0xf909a000 0x30>, <0xf900a000 0x30>;
			clock-output-names = "hfpll1";
		};

		clock-controller@f90aa000 {
			compatible = "qcom,hfpll";
			reg = <0xf90aa000 0x30>, <0xf900a000 0x30>;
			clock-output-names = "hfpll2";
		};

		clock-controller@f90ba000 {
			compatible = "qcom,hfpll";
			reg = <0xf90ba000 0x30>, <0xf900a000 0x30>;
			clock-output-names = "hfpll3";
		};

		saw_l2: regulator@f9012000 {
			compatible = "qcom,saw2";
			reg = <0xf9012000 0x1000>;
			regulator;
		};

		acc0: clock-controller@f9088000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
		};

		acc1: clock-controller@f9098000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
		};

		acc2: clock-controller@f90a8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
		};

		acc3: clock-controller@f90b8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
		};

		restart@fc4ab000 {
			compatible = "qcom,pshold";
			reg = <0xfc4ab000 0x4>;
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-msm8974";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfc400000 0x4000>;
		};

		tcsr_mutex_block: syscon@fd484000 {
			compatible = "syscon";
			reg = <0xfd484000 0x2000>;
		};

		mmcc: clock-controller@fd8c0000 {
			compatible = "qcom,mmcc-msm8974";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfd8c0000 0x6000>;
		};

		tcsr_mutex: tcsr-mutex {
			compatible = "qcom,tcsr-mutex";
			syscon = <&tcsr_mutex_block 0 0x80>;

			#hwlock-cells = <1>;
		};

		smem@fa00000 {
			compatible = "qcom,smem";

			memory-region = <&smem_region>;
			reg = <0xfc428000 0x4000>;

			hwlocks = <&tcsr_mutex 3>;
		};

		blsp1_uart2: serial@f991e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991e000 0x1000>;
			interrupts = <0 108 0x0>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f9824900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 123 0>, <0 138 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f98a4900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 125 0>, <0 221 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		rng@f9bff000 {
			compatible = "qcom,prng";
			reg = <0xf9bff000 0x200>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		msmgpio: pinctrl@fd510000 {
			compatible = "qcom,msm8974-pinctrl";
			reg = <0xfd510000 0x4000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 208 0>;
		};

		blsp_i2c11: i2c@f9967000 {
			status = "disable";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9967000 0x1000>;
			interrupts = <0 105 IRQ_TYPE_NONE>;
			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spmi_bus: spmi@fc4cf000 {
			compatible = "qcom,spmi-pmic-arb";
			reg-names = "core", "intr", "cnfg";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			interrupt-names = "periph_irq";
			interrupts = <0 190 0>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};
	};
};