aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-11-29GIC-Clayton: Fix the GICR base addressRD-INFRA-MC-2019.12.13topics/refinfra-mcrefinfra-mcVijayenthiran Subramaniam
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-11-26rddaniel-4xlr: add pd tree changes for quad chipVijayenthiran Subramaniam
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-11-26rddaniel-4xlr: intialize gic multichip for chip 2 and 3Vijayenthiran Subramaniam
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-11-26plat/arm/css/sgi: add mmap entries for 8TB+ devicesVijayenthiran Subramaniam
Add mmap entries for 8TB+ and 12TB+ devices to support the quad chip configuration. This allows the primary CPU to access chip 2 and chip 3. Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-11-26rddaniel-4xlr: increase pa and va size ot 44 bitsVijayenthiran Subramaniam
In RD-Daniel quad chip configuration the address space for all 4 chips ranges from 0TB to 16TB. To accomadate this address space increase pa and va to 44 bits. Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-10-23[HACK]: spinlock: send explicit event after store release instructionRD-INFRA-MC-20191024-RC0Vijayenthiran Subramaniam
stlr instruction in the spin_unlock function is expected to send an implicit event to all CPU cores. In a cross chip scenario, FVP has stability issues while sending this implicit event across chips. To avoid the stability issues, add sev instruction which sends explicit events to all cores. Explicit events are propagated across chips without any stability issues. Change-Id: I94db4f940e98f9b60f4120d0bde4930f9d31440c Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-10-23rddaniel-2xlr: add pd tree changes for dual-chipVijayenthiran Subramaniam
Change-Id: Id326e5820b3ac51c0750c9d8afa9abcf9ff4db0e Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-10-23board/rddaniel: intialize gic600 multichipVijayenthiran Subramaniam
Change-Id: I3265a3162de98266897a65f855a2acccaa5e6957 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-10-23board/rddaniel-2xlr: increase pa and va to 43 bitsVijayenthiran Subramaniam
In rd-daniel-2xlr platforms the address space for second chip (chip 1) ranges from 4TB to 8TB. To accomadate this address space increase pa and va to 43 bits. Change-Id: I591267d74476b23744815deb81a32c35021bed65 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-10-23sgi_plat: add mmap entry for 4TB+ device regionVijayenthiran Subramaniam
Add mmap entry for 4TB+ device region so that the primary CPU can access the peripherals on the slave chip Change-Id: I0c6d1c14ac581d4ed77d986d8e5c6c7a3c840068 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-10-23sgi: support dual-chip platforms in pdVijayenthiran Subramaniam
Change-Id: I956f51308f79d95944edca0b63b16c8893fb6b71 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-10-23plat/arm: use Aff3 bits also to validate mpidrManish Pandey
There are some platforms which uses MPIDR Affinity level 3 for storing extra affinity information e.g. N1SDP uses it for keeping chip id in a multichip setup, for such platforms MPIDR validation should not fail. This patch adds Aff3 bits also as part of mpidr validation mask, for platforms which does not uses Aff3 will not have any impact as these bits will be all zeros. Change-Id: Ia8273972fa7948fdb11708308d0239d2dc4dfa85 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2019-10-23board/rdn1edge: initialize GIC-600 multichip operationVijayenthiran Subramaniam
RdN1Edge platform supports a dual-chip configuration wherein two rdn1edge boards are connected through a high speed coherent CCIX link. Initialize GIC-600 multichip operation by overriding the default GICR frames with array of GICR frames and setting the chip 0 as routing table owner. Change-Id: I379c1aededb6bfe84947397a237247f173c48037 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-10-23plat/arm/sgi: bl31: add platform handler for board specific setupVijayenthiran Subramaniam
Introduce a new platform specific placeholder function sgi_bl31_board_setup. This placeholder can be extended to implement board specific BL31 stage platform setup. Change-Id: Ia44bccc0a7f40a155b33909bcb438a0909b20d42 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-10-23gic/gic600: add support for multichip configurationVijayenthiran Subramaniam
Add support to configure GIC-600's multichip routing table registers. Introduce a new gic600 multichip structure in order to support platforms to pass their GIC-600 multichip information such as routing table owner, SPI blocks ownership. Change-Id: Id409d0bc07843e271ead3fc2f6e3cb38b317878d Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-10-23plat/arm/gicv3: add support for probing multiple GIC Redistributor framesVijayenthiran Subramaniam
ARM platform can have a non-contiguous GICR frames. For instance, a multi socket platform can have two or more GIC Redistributor frames which are 4TB apart. Hence it is necessary for the `gicv3_rdistif_probe` function to probe all the GICR frames available in the platform. Introduce `plat_arm_override_gicr_frames` function which platforms can use to override the default gicr_frames which holds the GICR base address of the primary cpu. Change-Id: I1f537b0d871a679cb256092944737f2e55ab866e Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2019-10-23board/rddaniel: add board support for rd-daniel platformRD-INFRA-20191024-RC0Jagadeesh Ujja
Add the initial board support for RD-Daniel Config-M platform. This platform consists of 16 CPUs connected to the interconnect using direct connect mode. Change-Id: Ibe73ed136560ef64d2e0013ab8540a26f4fbd447 Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
2019-10-23plat/css/sgi: add support for rd-daniel config-m platformJagadeesh Ujja
Add the initial support for RD-Daniel Config-M platform in SGI CSS platform code. Change-Id: I6ec1713df74ce511e89d6c3aeafe012e3e2faa57 Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
2019-10-23plat/arm: let platforms define power levelsAditya Angadi
In order to add thread power level state support in ARM platform common code, let platforms define the Thread/Core/Cluster/System power levels and use those in the ARM platform common code. With this change, the power levels of Thread/Core/Cluster are derived from platform definition files rather than being implicitly assumed in the common code. Change-Id: I9bb593be69407f521b2dee51ec1723cb18a1bb12 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2019-10-23plat/arm: rename CSS_SYSTEM_PWR_DMN_LVL macroAditya Angadi
The first step in adding CPU thread power level state support into the common ARM platform code is to move away from using ARM_PWR_LVLx macros in the common ARM platform code. In order to do that, define a system power level macro that is usable by both ARM CSS and non-CSS platforms. The ARM CSS platforms currently define CSS_SYSTEM_PWR_DMN_LVL as ARM_PWR_LVL2 whereas the non-CSS platforms do not define any such macro to represent the system power state level. In order to move away from using ARM_PWR_LVL2 macro in ARM platform common code, let us rename the CSS_SYSTEM_PWR_DMN_LVL macro as PLAT_SYSTEM_PWR_LVL. This allows both ARM CSS and non-CSS platforms to define this and all uses of ARM_PWR_LVL2 can be replaced with PLAT_SYSTEM_PWR_LVL in the ARM platform common code. Change-Id: I91a58bcda3dadb6bcb2b5680df38b284b780d448 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2019-10-23plat/arm/sgi: allow nor2 flash and system registers access from s-el0Jagadeesh Ujja
Allow the access of system registers and nor2 flash memory region from s-el0. This allows the secure parititions to access these memory regions. Change-Id: Iedc7307603ad76568b9c7808d0508e16afccc0dc Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
2019-10-23plat/rde1edge: mark mm-communicate and CPER buffers as r/w from non-secure modeSughosh Ganu
The region of memory starting from ARM_AP_TZC_DRAM1_BASE for 16MB is configured for secure-only access. Carve out a region of 64KB and 128KB starting at 0xFF600000 for access from secure and non-secure world. Change-Id: I77147ae180d99c3da3853df58e6c9eb6766fe446 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
2019-10-23plat/rdn1edge: mark mm-communicate and CPER buffers as r/w from non-secure modeSughosh Ganu
The region of memory starting from ARM_AP_TZC_DRAM1_BASE for 16MB is configured for secure-only access. Carve out a region of 64KB and 128KB starting at 0xFF600000 for access from secure and non-secure world. Change-Id: I226646115faad1d5cc503b5b7cddd33e37079e93 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
2019-10-23plat/sgi575: mark mm-communicate and CPER buffers as r/w from non-secure modeSughosh Ganu
The region of memory starting from ARM_AP_TZC_DRAM1_BASE for 16MB is configured for secure-only access. Carve out a region of 64KB and 128KB starting at 0xFF600000 for access from secure and non-secure world. Change-Id: I6310e2177367ffcef468740d1f2cb59163808d16 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
2019-10-22Merge "Update TF-A version to 2.2" into integrationPaul Beesley
2019-10-22Merge "Update change log for v2.2 Release" into integrationPaul Beesley
2019-10-22Merge "Update release-information for v2.2 Release" into integrationPaul Beesley
2019-10-22Merge "doc: Final, pre-release fixes and updates" into integrationPaul Beesley
2019-10-22doc: Final, pre-release fixes and updatesPaul Beesley
A small set of misc changes to ensure correctness before the v2.2 release tagging. Change-Id: I888840b9483ea1a1633d204fbbc0f9594072101e Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-10-22Update release-information for v2.2 Releaselaurenw-arm
Removed deprecated interfaces that have been removed from the TF-A project, updated the deprecated list with new deprecations for v2.2 Release, added upcoming release information, remove mentions of PR from github. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Signed-off-by: Paul Beesley <paul.beesley@arm.com> Change-Id: I2b59d351cde9860ad0dcb6520a8bd2827ad403cf
2019-10-22Merge "doc: Expand contact information in About section" into integrationPaul Beesley
2019-10-22doc: Expand contact information in About sectionPaul Beesley
Giving a bit more background information about the issue tracker and mailing lists. Change-Id: I68921d54e3113d348f1e16c685f74d32df2ca19f Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-10-22Merge "doc: Move platform list to the Platform Ports index page" into ↵Paul Beesley
integration
2019-10-22Merge "doc: Move "About" content from index.rst to a new chapter" into ↵Paul Beesley
integration
2019-10-21Update change log for v2.2 Releaselaurenw-arm
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I53a7706016539e7de7fdbe87b786d99665bbe1d8
2019-10-21doc: Move platform list to the Platform Ports index pagePaul Beesley
The list of upstream platforms on the index page is growing quite long, especially with all the FVP variants being listed individually. This patch leverages the "Platform Ports" chapter in the docs table of contents to condense this information. Almost all platform ports now have documentation, so the table of contents serves as the list of upstream platforms by itself. For those upstream platforms that do not have corresponding documentation, the top-level "Platform Ports" page mentions them individually. It also mentions each Arm FVP, just as the index page did before. Note that there is an in-progress patch that creates new platform port documentation for the Arm Juno and Arm FVP platforms, so this list of "other platforms" will soon be reduced further as those platforms become part of the table of contents as well. Change-Id: I6b1eab8cba71a599d85a6e22553a34b07f213268 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-10-21doc: Move "About" content from index.rst to a new chapterPaul Beesley
The index.rst page is now the primary landing page for the TF-A documentation. It contains quite a lot of content these days, including: - The project purpose and general intro - A list of functionality - A list of planned functionality - A list of supported platforms - "Getting started" links to other documents - Contact information for raising issues This patch creates an "About" chapter in the table of contents and moves some content there. In order, the above listed content: - Stayed where it is. This is the right place for it. - Moved to About->Features - Moved to About->Features (in subsection) - Stayed where it is. Moved in a later patch. - Was expanded in-place - Moved to About->Contact Change-Id: I254bb87560fd09140b9e485cf15246892aa45943 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-10-21Merge "xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config" into ↵Soby Mathew
integration
2019-10-21Merge "Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__" into ↵Soby Mathew
integration
2019-10-18xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY configArtsem Artsemenka
The WARMBOOT_ENABLE_DCACHE_EARLY allows caches to be turned on early during the boot. But the xlat_change_mem_attributes_ctx() API did not do the required cache maintenance after the mmap tables are modified if WARMBOOT_ENABLE_DCACHE_EARLY is enabled. This meant that when the caches are turned off during power down, the tables in memory are accessed as part of cache maintenance for power down, and the tables are not correct at this point which results in a data abort. This patch removes the optimization within xlat_change_mem_attributes_ctx() when WARMBOOT_ENABLE_DCACHE_EARLY is enabled. Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Change-Id: I82de3decba87dd13e9856b5f3620a1c8571c8d87
2019-10-18Merge "Fix documentation" into integrationPaul Beesley
2019-10-18Merge "doc: Remove version and release variables from conf.py" into integrationPaul Beesley
2019-10-17doc: Remove version and release variables from conf.pyPaul Beesley
We would need to update this version for the release but, in fact, it is not required for our publishing workflow; the hosted version of the docs uses git commit/tag information in place of these variables anyway. Instead of updating the version, just remove these variables entirely. Change-Id: I424c4e45786e87604e91c7197b7983579afe4806 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-10-15Fix documentationArtsem Artsemenka
User guide: 1. Remove obsolete note saying only FVP is supported with AArch32 2. Switch compiler for Juno AArch32 to arm-eabi 3. Mention SOFTWARE folder in Juno Linaro release Index.rst: 1. Switch default FVP model to Version 11.6 Build 45 Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Change-Id: Ib47a2ea314e2b8394a20189bf91796de0e17de53
2019-10-15Update TF-A version to 2.2Deepika Bhavnani
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Ia03701e2e37e3a00a501b144960a4a65aedbfde9
2019-10-15Merge "Correct UART PL011 initialization calculation" into integrationPaul Beesley
2019-10-15Merge "doc: Update Linaro release mentioned on index page" into integrationPaul Beesley
2019-10-15doc: Update Linaro release mentioned on index pagePaul Beesley
The version of the Linaro release that is used for testing was updated in 35010bb8 and the user guide was updated with the correct version, however the version is also mentioned on the index page and that was missed. Update the index page with the new version. We can come back and de-duplicate this content later, to ease future maintenance. Change-Id: I3fe83d7a1c59ab8d3ce2b18bcc23e16c93f7af97 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-10-11Merge "doc: Misc syntax and spelling fixes" into integrationPaul Beesley
2019-10-11doc: Misc syntax and spelling fixesPaul Beesley
Tidying up a few Sphinx warnings that had built-up over time. None of these are critical but it cleans up the Sphinx output. At the same time, fixing some spelling errors that were detected. Change-Id: I38209e235481eed287f8008c6de9dedd6b12ab2e Signed-off-by: Paul Beesley <paul.beesley@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-22 18:25:39 +0000