From 459813190c1cc4be3655361af3c1d587fefa0ab3 Mon Sep 17 00:00:00 2001 From: Aditya Angadi Date: Fri, 26 Apr 2019 14:13:32 +0530 Subject: plat/arm: let platforms define power levels In order to add thread power level state support in ARM platform common code, let platforms define the Thread/Core/Cluster/System power levels and use those in the ARM platform common code. With this change, the power levels of Thread/Core/Cluster are derived from platform definition files rather than being implicitly assumed in the common code. Change-Id: I9bb593be69407f521b2dee51ec1723cb18a1bb12 Signed-off-by: Aditya Angadi --- drivers/arm/css/scp/css_pm_scmi.c | 8 ++++---- drivers/arm/css/scp/css_pm_scpi.c | 4 ++-- include/plat/arm/css/common/css_pm.h | 8 ++++++-- plat/arm/board/fvp/fvp_pm.c | 24 +++++++++++------------ plat/arm/board/fvp/include/platform_def.h | 6 +++++- plat/arm/board/juno/include/platform_def.h | 9 +++++++-- plat/arm/board/rddaniel/include/platform_def.h | 8 ++++++-- plat/arm/board/rddanielxlr/include/platform_def.h | 8 ++++++-- plat/arm/board/rde1edge/include/platform_def.h | 8 ++++++-- plat/arm/board/rdn1edge/include/platform_def.h | 6 ++++-- plat/arm/board/rdn2/include/platform_def.h | 8 ++++++-- plat/arm/board/sgi575/include/platform_def.h | 6 ++++-- plat/arm/common/arm_pm.c | 10 +++++----- plat/arm/css/common/css_pm.c | 14 ++++++------- plat/arm/css/sgm/include/sgm_base_platform_def.h | 8 +++++++- 15 files changed, 87 insertions(+), 48 deletions(-) diff --git a/drivers/arm/css/scp/css_pm_scmi.c b/drivers/arm/css/scp/css_pm_scmi.c index 5656eb0e2..5c109f9c9 100644 --- a/drivers/arm/css/scp/css_pm_scmi.c +++ b/drivers/arm/css/scp/css_pm_scmi.c @@ -110,7 +110,7 @@ void css_scp_suspend(const struct psci_power_state *target_state) int ret; /* At least power domain level 0 should be specified to be suspended */ - assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == + assert(target_state->pwr_domain_state[PLAT_MIN_PWR_LVL] == ARM_LOCAL_STATE_OFF); /* Check if power down at system power domain level is requested */ @@ -136,10 +136,10 @@ void css_scp_suspend(const struct psci_power_state *target_state) assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); /* For level 0, specify `scmi_power_state_sleep` as the power state */ - SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, ARM_PWR_LVL0, + SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, PLAT_MIN_PWR_LVL, scmi_power_state_sleep); - for (lvl = ARM_PWR_LVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { + for (lvl = PLAT_MIN_PWR_LVL + 1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) break; @@ -179,7 +179,7 @@ void css_scp_off(const struct psci_power_state *target_state) uint32_t scmi_pwr_state = 0; /* At-least the CPU level should be specified to be OFF */ - assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == + assert(target_state->pwr_domain_state[PLAT_MIN_PWR_LVL] == ARM_LOCAL_STATE_OFF); /* PSCI CPU OFF cannot be used to turn OFF system power domain */ diff --git a/drivers/arm/css/scp/css_pm_scpi.c b/drivers/arm/css/scp/css_pm_scpi.c index b4019ce03..f0cac92e5 100644 --- a/drivers/arm/css/scp/css_pm_scpi.c +++ b/drivers/arm/css/scp/css_pm_scpi.c @@ -80,7 +80,7 @@ int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level) * The format of 'power_level' is implementation-defined, but 0 must * mean a CPU. We also allow 1 to denote the cluster */ - if (power_level != ARM_PWR_LVL0 && power_level != ARM_PWR_LVL1) + if (power_level > PLAT_CLUSTER_PWR_LVL) return PSCI_E_INVALID_PARAMS; /* Query SCP */ @@ -89,7 +89,7 @@ int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level) return PSCI_E_INVALID_PARAMS; /* Map power states of CPU and cluster to expected PSCI return codes */ - if (power_level == ARM_PWR_LVL0) { + if (power_level == PLAT_MIN_PWR_LVL) { /* * The CPU state returned by SCP is an 8-bit bit mask * corresponding to each CPU in the cluster diff --git a/include/plat/arm/css/common/css_pm.h b/include/plat/arm/css/common/css_pm.h index 783375c3f..9bb239556 100644 --- a/include/plat/arm/css/common/css_pm.h +++ b/include/plat/arm/css/common/css_pm.h @@ -13,8 +13,12 @@ #include /* Macros to read the CSS power domain state */ -#define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0] -#define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1] +#define CSS_THREAD_PWR_STATE(state) (state)->pwr_domain_state[PLAT_THREAD_PWR_LVL] +#define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[PLAT_CORE_PWR_LVL] +#define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[PLAT_CLUSTER_PWR_LVL] + +#define CSS_MIN_PWR_STATE(state) (state)->pwr_domain_state[PLAT_MIN_PWR_LVL] +#define CSS_MAX_PWR_STATE(state) (state)->pwr_domain_state[PLAT_MAX_PWR_LVL] static inline unsigned int css_system_pwr_state(const psci_power_state_t *state) { diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c index 333d89288..069a1710d 100644 --- a/plat/arm/board/fvp/fvp_pm.c +++ b/plat/arm/board/fvp/fvp_pm.c @@ -103,14 +103,14 @@ static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_s { unsigned long mpidr; - assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == + assert(target_state->pwr_domain_state[PLAT_MIN_PWR_LVL] == ARM_LOCAL_STATE_OFF); /* Get the mpidr for this cpu */ mpidr = read_mpidr_el1(); /* Perform the common cluster specific operations */ - if (target_state->pwr_domain_state[ARM_PWR_LVL1] == + if (target_state->pwr_domain_state[PLAT_CLUSTER_PWR_LVL] == ARM_LOCAL_STATE_OFF) { /* * This CPU might have woken up whilst the cluster was @@ -127,7 +127,7 @@ static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_s fvp_interconnect_enable(); } /* Perform the common system specific operations */ - if (target_state->pwr_domain_state[ARM_PWR_LVL2] == + if (target_state->pwr_domain_state[PLAT_SYSTEM_PWR_LVL] == ARM_LOCAL_STATE_OFF) arm_system_pwr_domain_resume(); @@ -183,7 +183,7 @@ static int fvp_pwr_domain_on(u_register_t mpidr) ******************************************************************************/ static void fvp_pwr_domain_off(const psci_power_state_t *target_state) { - assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == + assert(target_state->pwr_domain_state[PLAT_MIN_PWR_LVL] == ARM_LOCAL_STATE_OFF); /* @@ -201,7 +201,7 @@ static void fvp_pwr_domain_off(const psci_power_state_t *target_state) /* Program the power controller to power off this cpu. */ fvp_pwrc_write_ppoffr(read_mpidr_el1()); - if (target_state->pwr_domain_state[ARM_PWR_LVL1] == + if (target_state->pwr_domain_state[PLAT_CLUSTER_PWR_LVL] == ARM_LOCAL_STATE_OFF) fvp_cluster_pwrdwn_common(); @@ -219,11 +219,11 @@ static void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) * FVP has retention only at cpu level. Just return * as nothing is to be done for retention. */ - if (target_state->pwr_domain_state[ARM_PWR_LVL0] == + if (target_state->pwr_domain_state[PLAT_MIN_PWR_LVL] == ARM_LOCAL_STATE_RET) return; - assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == + assert(target_state->pwr_domain_state[PLAT_MIN_PWR_LVL] == ARM_LOCAL_STATE_OFF); /* Get the mpidr for this cpu */ @@ -242,12 +242,12 @@ static void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) */ /* Perform the common cluster specific operations */ - if (target_state->pwr_domain_state[ARM_PWR_LVL1] == + if (target_state->pwr_domain_state[PLAT_CLUSTER_PWR_LVL] == ARM_LOCAL_STATE_OFF) fvp_cluster_pwrdwn_common(); /* Perform the common system specific operations */ - if (target_state->pwr_domain_state[ARM_PWR_LVL2] == + if (target_state->pwr_domain_state[PLAT_SYSTEM_PWR_LVL] == ARM_LOCAL_STATE_OFF) arm_system_pwr_domain_save(); @@ -292,7 +292,7 @@ static void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state /* * Nothing to be done on waking up from retention from CPU level. */ - if (target_state->pwr_domain_state[ARM_PWR_LVL0] == + if (target_state->pwr_domain_state[PLAT_MIN_PWR_LVL] == ARM_LOCAL_STATE_RET) return; @@ -372,7 +372,7 @@ static void fvp_get_sys_suspend_power_state(psci_power_state_t *req_state) { unsigned int i; - for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) + for (i = PLAT_MIN_PWR_LVL; i <= PLAT_MAX_PWR_LVL; i++) req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; } #endif @@ -396,7 +396,7 @@ static int fvp_validate_power_state(unsigned int power_state, * via PSCI CPU SUSPEND API. Currently system suspend is only * supported via PSCI SYSTEM SUSPEND API. */ - req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN; + req_state->pwr_domain_state[PLAT_SYSTEM_PWR_LVL] = ARM_LOCAL_STATE_RUN; return rc; } diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index f0f27ff3f..f3a9c818c 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -23,8 +23,12 @@ #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) + 1 + +#define PLAT_CORE_PWR_LVL ARM_PWR_LVL0 +#define PLAT_CLUSTER_PWR_LVL ARM_PWR_LVL1 #define PLAT_SYSTEM_PWR_LVL ARM_PWR_LVL2 -#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 +#define PLAT_MIN_PWR_LVL PLAT_CORE_PWR_LVL +#define PLAT_MAX_PWR_LVL PLAT_SYSTEM_PWR_LVL /* * Other platform porting definitions are provided by included headers diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index fbb13d930..4ae790395 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -21,14 +21,19 @@ #include "../juno_def.h" /* Required platform porting definitions */ -/* Juno supports system power domain */ -#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ JUNO_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ JUNO_CLUSTER1_CORE_COUNT) +#define PLAT_CORE_PWR_LVL ARM_PWR_LVL0 +#define PLAT_CLUSTER_PWR_LVL ARM_PWR_LVL1 +#define PLAT_SYSTEM_PWR_LVL ARM_PWR_LVL2 + +#define PLAT_MIN_PWR_LVL PLAT_CORE_PWR_LVL +#define PLAT_MAX_PWR_LVL PLAT_SYSTEM_PWR_LVL + /* Cryptocell HW Base address */ #define PLAT_CRYPTOCELL_BASE UL(0x60050000) diff --git a/plat/arm/board/rddaniel/include/platform_def.h b/plat/arm/board/rddaniel/include/platform_def.h index 5b98b4e8c..c0718ae23 100644 --- a/plat/arm/board/rddaniel/include/platform_def.h +++ b/plat/arm/board/rddaniel/include/platform_def.h @@ -18,8 +18,12 @@ #define PLAT_CSS_MHU_BASE UL(0x45400000) #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE -#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 -#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 +#define PLAT_CORE_PWR_LVL ARM_PWR_LVL0 +#define PLAT_CLUSTER_PWR_LVL ARM_PWR_LVL1 +#define PLAT_SYSTEM_PWR_LVL ARM_PWR_LVL2 + +#define PLAT_MIN_PWR_LVL PLAT_CORE_PWR_LVL +#define PLAT_MAX_PWR_LVL PLAT_CLUSTER_PWR_LVL /* TZC Related Constants */ #define PLAT_ARM_TZC_BASE UL(0x21830000) diff --git a/plat/arm/board/rddanielxlr/include/platform_def.h b/plat/arm/board/rddanielxlr/include/platform_def.h index 112b2102b..3c848750b 100644 --- a/plat/arm/board/rddanielxlr/include/platform_def.h +++ b/plat/arm/board/rddanielxlr/include/platform_def.h @@ -17,8 +17,12 @@ #define PLAT_CSS_MHU_BASE UL(0x45400000) #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE -#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 -#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 +#define PLAT_CORE_PWR_LVL ARM_PWR_LVL0 +#define PLAT_CLUSTER_PWR_LVL ARM_PWR_LVL1 +#define PLAT_SYSTEM_PWR_LVL ARM_PWR_LVL2 + +#define PLAT_MIN_PWR_LVL PLAT_CORE_PWR_LVL +#define PLAT_MAX_PWR_LVL PLAT_CLUSTER_PWR_LVL /* Virtual address used by dynamic mem_protect for chunk_base */ #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000) diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h index bbdc012bf..0334a6a52 100644 --- a/plat/arm/board/rde1edge/include/platform_def.h +++ b/plat/arm/board/rde1edge/include/platform_def.h @@ -21,10 +21,14 @@ #define RDE1EDGE_DMC620_BASE0 UL(0x4e000000) #define RDE1EDGE_DMC620_BASE1 UL(0x4e100000) -#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 - +#define PLAT_THREAD_PWR_LVL ARM_PWR_LVL0 +#define PLAT_CORE_PWR_LVL ARM_PWR_LVL1 +#define PLAT_CLUSTER_PWR_LVL ARM_PWR_LVL2 #define PLAT_SYSTEM_PWR_LVL ARM_PWR_LVL3 +#define PLAT_MIN_PWR_LVL PLAT_THREAD_PWR_LVL +#define PLAT_MAX_PWR_LVL PLAT_CLUSTER_PWR_LVL + /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h index 748f5fde1..d120c74cf 100644 --- a/plat/arm/board/rdn1edge/include/platform_def.h +++ b/plat/arm/board/rdn1edge/include/platform_def.h @@ -21,10 +21,12 @@ #define RDN1EDGE_DMC620_BASE0 UL(0x4e000000) #define RDN1EDGE_DMC620_BASE1 UL(0x4e100000) -/* System power domain level */ +#define PLAT_CORE_PWR_LVL ARM_PWR_LVL0 +#define PLAT_CLUSTER_PWR_LVL ARM_PWR_LVL1 #define PLAT_SYSTEM_PWR_LVL ARM_PWR_LVL2 -#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 +#define PLAT_MIN_PWR_LVL PLAT_CORE_PWR_LVL +#define PLAT_MAX_PWR_LVL PLAT_CLUSTER_PWR_LVL /* Virtual address used by dynamic mem_protect for chunk_base */ #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) diff --git a/plat/arm/board/rdn2/include/platform_def.h b/plat/arm/board/rdn2/include/platform_def.h index ebfbf66a6..9b13eb8c3 100644 --- a/plat/arm/board/rdn2/include/platform_def.h +++ b/plat/arm/board/rdn2/include/platform_def.h @@ -18,8 +18,12 @@ #define PLAT_CSS_MHU_BASE UL(0x2A920000) #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE -#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 -#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 +#define PLAT_CORE_PWR_LVL ARM_PWR_LVL0 +#define PLAT_CLUSTER_PWR_LVL ARM_PWR_LVL1 +#define PLAT_SYSTEM_PWR_LVL ARM_PWR_LVL2 + +#define PLAT_MIN_PWR_LVL PLAT_CORE_PWR_LVL +#define PLAT_MAX_PWR_LVL PLAT_CLUSTER_PWR_LVL /* TZC Related Constants */ #define PLAT_ARM_TZC_BASE UL(0x10820000) diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h index 00ac753af..54697819a 100644 --- a/plat/arm/board/sgi575/include/platform_def.h +++ b/plat/arm/board/sgi575/include/platform_def.h @@ -21,10 +21,12 @@ #define SGI575_DMC620_BASE0 UL(0x4e000000) #define SGI575_DMC620_BASE1 UL(0x4e100000) -/* System power domain level */ +#define PLAT_CORE_PWR_LVL ARM_PWR_LVL0 +#define PLAT_CLUSTER_PWR_LVL ARM_PWR_LVL1 #define PLAT_SYSTEM_PWR_LVL ARM_PWR_LVL2 -#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 +#define PLAT_MIN_PWR_LVL PLAT_CORE_PWR_LVL +#define PLAT_MAX_PWR_LVL PLAT_CLUSTER_PWR_LVL /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c index 5434c9457..49ffa85a5 100644 --- a/plat/arm/common/arm_pm.c +++ b/plat/arm/common/arm_pm.c @@ -39,13 +39,13 @@ int arm_validate_power_state(unsigned int power_state, * It's possible to enter standby only on power level 0 * Ignore any other power level. */ - if (pwr_lvl != ARM_PWR_LVL0) + if (pwr_lvl != PLAT_MIN_PWR_LVL) return PSCI_E_INVALID_PARAMS; - req_state->pwr_domain_state[ARM_PWR_LVL0] = + req_state->pwr_domain_state[PLAT_MIN_PWR_LVL] = ARM_LOCAL_STATE_RET; } else { - for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++) + for (i = PLAT_MIN_PWR_LVL; i <= pwr_lvl; i++) req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; } @@ -138,7 +138,7 @@ int arm_validate_psci_entrypoint(uintptr_t entrypoint) void arm_system_pwr_domain_save(void) { /* Assert system power domain is available on the platform */ - assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); + assert(PLAT_MAX_PWR_LVL >= PLAT_SYSTEM_PWR_LVL); plat_arm_gic_save(); @@ -167,7 +167,7 @@ void arm_system_pwr_domain_resume(void) arm_console_runtime_init(); /* Assert system power domain is available on the platform */ - assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); + assert(PLAT_MAX_PWR_LVL >= PLAT_SYSTEM_PWR_LVL); plat_arm_gic_resume(); diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c index 5ecb9072c..0486d6593 100644 --- a/plat/arm/css/common/css_pm.c +++ b/plat/arm/css/common/css_pm.c @@ -48,7 +48,7 @@ const unsigned int arm_pm_idle_states[] = { * All the power management helpers in this file assume at least cluster power * level is supported. */ -CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1, +CASSERT(PLAT_MAX_PWR_LVL >= PLAT_CLUSTER_PWR_LVL, assert_max_pwr_lvl_supported_mismatch); /* @@ -72,7 +72,7 @@ int css_pwr_domain_on(u_register_t mpidr) static void css_pwr_domain_on_finisher_common( const psci_power_state_t *target_state) { - assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); + assert(CSS_MIN_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); /* * Perform the common cluster specific operations i.e enable coherency @@ -154,7 +154,7 @@ static void css_power_down_common(const psci_power_state_t *target_state) ******************************************************************************/ void css_pwr_domain_off(const psci_power_state_t *target_state) { - assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); + assert(CSS_MIN_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); css_power_down_common(target_state); css_scp_off(target_state); } @@ -169,11 +169,11 @@ void css_pwr_domain_suspend(const psci_power_state_t *target_state) * CSS currently supports retention only at cpu level. Just return * as nothing is to be done for retention. */ - if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) + if (CSS_MIN_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) return; - assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); + assert(CSS_MIN_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); css_power_down_common(target_state); /* Perform system domain state saving if issuing system suspend */ @@ -198,7 +198,7 @@ void css_pwr_domain_suspend_finish( const psci_power_state_t *target_state) { /* Return as nothing is to be done on waking up from retention. */ - if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) + if (CSS_MIN_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) return; /* Perform system domain restore if woken up from system suspend */ @@ -271,7 +271,7 @@ void css_get_sys_suspend_power_state(psci_power_state_t *req_state) */ assert(PLAT_MAX_PWR_LVL == PLAT_SYSTEM_PWR_LVL); - for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) + for (i = PLAT_MIN_PWR_LVL; i <= PLAT_MAX_PWR_LVL; i++) req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; } diff --git a/plat/arm/css/sgm/include/sgm_base_platform_def.h b/plat/arm/css/sgm/include/sgm_base_platform_def.h index e55a9ca8b..a5741c337 100644 --- a/plat/arm/css/sgm/include/sgm_base_platform_def.h +++ b/plat/arm/css/sgm/include/sgm_base_platform_def.h @@ -21,11 +21,17 @@ #define PLAT_ARM_CLUSTER_CORE_COUNT U(8) #define PLATFORM_CORE_COUNT PLAT_ARM_CLUSTER_CORE_COUNT -#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ PLAT_ARM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) +#define PLAT_CORE_PWR_LVL ARM_PWR_LVL0 +#define PLAT_CLUSTER_PWR_LVL ARM_PWR_LVL1 +#define PLAT_SYSTEM_PWR_LVL ARM_PWR_LVL2 + +#define PLAT_MIN_PWR_LVL PLAT_CORE_PWR_LVL +#define PLAT_MAX_PWR_LVL PLAT_SYSTEM_PWR_LVL + /* * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 * terminology. On a GICv2 system or mode, the lists will be merged and treated -- cgit v1.2.3