blob: aa97afa3064986e518d146c094fa648021fa45de (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
/*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <lib/utils_def.h>
#include <sgi_base_platform_def.h>
#define CSS_SGI_MAX_CHIP_COUNT 2
#define PLAT_ARM_CLUSTER_COUNT 2
#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
#define CSS_SGI_MAX_PE_PER_CPU 1
#define CSS_SGI_MAX_PE_PER_CHIP \
(PLAT_ARM_CLUSTER_COUNT * CSS_SGI_MAX_CPUS_PER_CLUSTER * \
CSS_SGI_MAX_PE_PER_CPU)
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
/* Base address of DMC-620 instances */
#define RDN1EDGE_DMC620_BASE0 UL(0x4e000000)
#define RDN1EDGE_DMC620_BASE1 UL(0x4e100000)
#define PLAT_CORE_PWR_LVL ARM_PWR_LVL0
#define PLAT_CLUSTER_PWR_LVL ARM_PWR_LVL1
#define PLAT_SYSTEM_PWR_LVL ARM_PWR_LVL2
#define PLAT_MIN_PWR_LVL PLAT_CORE_PWR_LVL
#define PLAT_MAX_PWR_LVL PLAT_CLUSTER_PWR_LVL
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#endif
#endif /* PLATFORM_DEF_H */
|
