diff options
| author | Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> | 2020-10-04 12:50:29 +0530 |
|---|---|---|
| committer | Thomas Abraham <thomas.abraham@arm.com> | 2020-10-04 14:27:55 +0530 |
| commit | 787f738a8d41e3a9815f28c2986cb953dd5481be (patch) | |
| tree | da9987e0b99f3544c63e857774cfa9a35b6060bb | |
| parent | 0bd5132e9797d0fe393c15d5830f22e142af9e81 (diff) | |
platforms/rd: disable multithreading for dgi
Disable use of multithreading for Distributed GIC Intergace (DGI)
transactions in GIC multichip use cases. This will dnable sending
multichip DGI messages in a separate thread. This patch affects
only the multi-chip plaforms - rdn1edgex2 and rddanielxlr.
Change-Id: I6414f53f2341d0d5da3545a5274ad5e5f1dc3fc6
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
| -rw-r--r-- | rdinfra/platforms/rddanielxlr/run_model.sh | 4 | ||||
| -rwxr-xr-x | rdinfra/platforms/rdn1edgex2/run_model.sh | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/rdinfra/platforms/rddanielxlr/run_model.sh b/rdinfra/platforms/rddanielxlr/run_model.sh index c5b1650..ba62ca3 100644 --- a/rdinfra/platforms/rddanielxlr/run_model.sh +++ b/rdinfra/platforms/rddanielxlr/run_model.sh @@ -402,6 +402,7 @@ PARAMS=" \ -C soc0.pl011_uart1.unbuffered_output=1 \ -C css0.pl011_uart_ap.unbuffered_output=1 \ -C css0.gic_distributor.ITS-device-bits=20 \ + -C css0.gic_distributor.multichip-threaded-dgi=0 \ --data css1.scp.armcortexm7ct=$OUTDIR/scp_ramfw.bin@0x0BD80000 \ -C css1.cmn_650.force_rnsam_internal=true \ @@ -416,6 +417,7 @@ PARAMS=" \ -C soc1.pl011_uart1.unbuffered_output=1 \ -C css1.pl011_uart_ap.unbuffered_output=1 \ -C css1.gic_distributor.ITS-device-bits=20 \ + -C css1.gic_distributor.multichip-threaded-dgi=0 \ --data css2.scp.armcortexm7ct=$OUTDIR/scp_ramfw.bin@0x0BD80000 \ -C css2.cmn_650.force_rnsam_internal=true \ @@ -430,6 +432,7 @@ PARAMS=" \ -C soc2.pl011_uart1.unbuffered_output=1 \ -C css2.pl011_uart_ap.unbuffered_output=1 \ -C css2.gic_distributor.ITS-device-bits=20 \ + -C css2.gic_distributor.multichip-threaded-dgi=0 \ --data css3.scp.armcortexm7ct=$OUTDIR/scp_ramfw.bin@0x0BD80000 \ -C css3.cmn_650.force_rnsam_internal=true \ @@ -444,6 +447,7 @@ PARAMS=" \ -C soc3.pl011_uart1.unbuffered_output=1 \ -C css3.pl011_uart_ap.unbuffered_output=1 \ -C css3.gic_distributor.ITS-device-bits=20 \ + -C css3.gic_distributor.multichip-threaded-dgi=0 \ ${MODEL_PARAMS} \ ${TZC_BYPASS_PARAMS} \ ${EXTRA_MODEL_PARAMS}" diff --git a/rdinfra/platforms/rdn1edgex2/run_model.sh b/rdinfra/platforms/rdn1edgex2/run_model.sh index fba5862..7e0699a 100755 --- a/rdinfra/platforms/rdn1edgex2/run_model.sh +++ b/rdinfra/platforms/rdn1edgex2/run_model.sh @@ -295,6 +295,7 @@ PARAMS=" \ -C soc0.pl011_uart1.unbuffered_output=1 \ -C css0.pl011_uart_ap.unbuffered_output=1 \ -C css0.gic_distributor.ITS-device-bits=20 \ + -C css0.gic_distributor.multichip-threaded-dgi=0 \ -C css1.cmn600.mesh_config_file=$PATH_TO_MODEL/RD_N1_E1_cmn600.yml \ -C css1.cmn600.force_rnsam_internal=false \ @@ -317,6 +318,7 @@ PARAMS=" \ -C soc1.pl011_uart1.unbuffered_output=1 \ -C css1.pl011_uart_ap.unbuffered_output=1 \ -C css1.gic_distributor.ITS-device-bits=20 \ + -C css1.gic_distributor.multichip-threaded-dgi=0 \ ${MODEL_PARAMS} \ ${EXTRA_MODEL_PARAMS}" |