diff options
author | Jun Nie <jun.nie@linaro.org> | 2019-08-14 14:59:31 +0800 |
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committer | Jun Nie <jun.nie@linaro.org> | 2019-08-14 14:59:31 +0800 |
commit | 348e0156e7a196ff25f8b047f4ca73ccb906f72a (patch) | |
tree | 3683e63477dbf43f21bbfaa994390cdd21b87f5e | |
parent | d9f8282587f6892f43fca119a73df7c941c30418 (diff) |
imx8mm: Add registers definition
Add registers definition according to reference manual.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Change-Id: Ifb11190195e2d2ed2543eb9230903929a59f4822
-rw-r--r-- | plat/imx/imx8m/include/imx_regs.h | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/plat/imx/imx8m/include/imx_regs.h b/plat/imx/imx8m/include/imx_regs.h new file mode 100644 index 00000000..b1ce4372 --- /dev/null +++ b/plat/imx/imx8m/include/imx_regs.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IMX_REGS_H +#define IMX_REGS_H + +/* Define the processor memory map */ +#define CAAM_BASE 0x00100000 /* CAAM block base address */ +#define OCRAM_S_BASE 0x00180000 /* OCRAM_S */ +#define OCRAM_S_SIZE U(0x8000) +#define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) +#define OCRAM_BASE 0x00900000 /* OCRAM base */ + +/* BootROM absolute base address */ +#define BOOTROM_BASE 0x00000000 /* BootROM */ + +/* Peripherals like GPIO live in the AIPS range */ +#define AIPS1_BASE 0x30000000 /* AIPS1 */ +#define AIPS2_BASE 0x30400000 /* AIPS2 */ +#define AIPS3_BASE 0x30800000 /* AIPS3 */ + +#define AIPS4_BASE 0x32c00000 /* AIPS4 */ + +/* ARM peripherals like GIC */ +#define ARM_PERIPHERAL_GIC_BASE 0x38800000 /* GIC */ + +/* Configuration ports */ +#define GPV0_BASE 0x32000000 /* Main config port */ +#define GPV1_BASE 0x32100000 /* Wakeup config port */ +#define GPV2_BASE 0x32200000 /* Per_s config port */ +#define GPV3_BASE 0x32300000 /* Per_m config port */ +#define GPV4_BASE 0x32400000 /* Enet config port */ +#define GPV5_BASE 0x32500000 /* Display config port */ +#define GPV6_BASE 0x32600000 /* M4 conig port */ +#define GPV7_BASE 0x32700000 /* NoC conig port */ +#define GPV8_BASE 0x32800000 /* HSIO conig port */ + +/* MMAP peripherals - like APBH DMA */ +#define APBH_DMA_BASE 0x33000000 /* APBH DMA block */ + +/* QSPI RX BUFFERS */ +#define QSPI_RX_BUFFER_BASE 0x34000000 /* QSPI RX buffers */ + +/* AIPS1 block addresses */ +#define AIPSTZ_CONFIG_OFFSET 0x001f0000 +#define CCM_BASE (AIPS1_BASE + 0x380000) + +/* Define the maximum number of UART blocks on this SoC */ +#define MXC_UART1_BASE (AIPS3_BASE + 0x060000) +#define MXC_UART2_BASE (AIPS3_BASE + 0x090000) +#define MXC_UART3_BASE (AIPS3_BASE + 0x080000) +#define MXC_UART4_BASE (AIPS3_BASE + 0x260000) +#define MXC_MAX_UART_NUM 0x04 + +/* Define the maximum number of USDHCI blocks on this SoC */ +#define MXC_MAX_USDHC_NUM 3 + +/* Define the number of CSU registers for this SoC */ +//#define MXC_MAX_CSU_REGS 0x40 +#define CSU_BASE (AIPS1_BASE + 0x3E0000) + +/* IO Mux block base */ +#define MXC_IO_MUXC_BASE (AIPS1_BASE + 0x330000) + +#define ANA_PLL_BASE (AIPS1_BASE + 0x360000) + +/* SNVS base */ +#define SNVS_BASE (AIPS1_BASE + 0x370000) + +/* GP Timer base */ +#define GPT1_BASE_ADDR (AIPS1_BASE + 0x2d0000) + +/* MMC base */ +#define USDHC1_BASE (AIPS1_BASE + 0xb40000) +#define USDHC2_BASE (AIPS1_BASE + 0xb50000) +#define USDHC3_BASE (AIPS1_BASE + 0xb60000) + +/* Arm optional memory mapped counter module base address */ +#define SYS_CNTCTL_BASE (AIPS2_BASE + 0x2c0000) + +/* Define CAAM AIPS offset */ +#define CAAM_AIPS_BASE (AIPS3_BASE + 0x100000) +//#define CAAM_NUM_JOB_RINGS 0x03 +//#define CAAM_NUM_RTIC 0x04 +//#define CAAM_NUM_DECO 0x01 + +/* Define watchdog base addresses */ +#define WDOG1_BASE (AIPS1_BASE + 0x280000) +#define WDOG2_BASE (AIPS1_BASE + 0x290000) +#define WDOG3_BASE (AIPS1_BASE + 0x2A0000) + +/* Define the maximum number of WDOG blocks on this SoC */ +#define MXC_MAX_WDOG_NUM 0x03 + +#endif /* IMX_REGS_H */ |