diff options
| author | Silvano di Ninno <silvano.dininno@nxp.com> | 2018-10-01 17:58:43 +0200 |
|---|---|---|
| committer | Silvano di Ninno <silvano.dininno@nxp.com> | 2018-10-01 18:17:00 +0200 |
| commit | 021f515d9a5e58d141a459276982614d3167ceaa (patch) | |
| tree | ffb10ccb70d2935f7e1d6195aeed0966bfc98929 | |
| parent | 5a28c563eeaa33482830aa5d5df3876a0c2ff8e9 (diff) | |
TEE-318: TZASC: optee memory is not protected on i.MX 8mq and 8mm
TZASC is not configured properly on i.MX 8MQ and 8MM.
root@imx8mqevk:/unit_tests# ./memtool -32 0xfe000000 1
Reading 0x1 count starting at address 0xFE000000
0xFE000000: AA0003F3
Instead we should have a data abort.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
| -rw-r--r-- | core/arch/arm/plat-imx/tzasc.c | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/core/arch/arm/plat-imx/tzasc.c b/core/arch/arm/plat-imx/tzasc.c index 73068807..14f5334b 100644 --- a/core/arch/arm/plat-imx/tzasc.c +++ b/core/arch/arm/plat-imx/tzasc.c @@ -315,10 +315,12 @@ static int board_imx_tzasc_configure(vaddr_t addr) tzc_configure_region(0, 0x00000000, TZC_ATTR_SP_S_RW); - /* The DDR mappng seems to start at 0 instead of 0x4000 0000 - We map 4G disabling 2 subregion of 512 M to effectively map 3G at - 0x0000 0000 - */ + /* The DDR mapping seems to start at 0 instead of 0x4000 0000. + * Substract the offset from the CFG_TZDRAM_START and CFG_SHMEM_START + * addresses. + * In addition, to map the 3GBytes of DDR available on the board, 4Gbytes + * are configured and the last 2 subregions (of 512MB each) are disabled. + */ tzc_configure_region(1, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_NS_RW @@ -326,10 +328,10 @@ static int board_imx_tzasc_configure(vaddr_t addr) | TZC_ATTR_SUBREGION_DIS(7) ); - tzc_configure_region(2, CFG_TZDRAM_START, + tzc_configure_region(2, (CFG_TZDRAM_START - DRAM0_BASE), TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_32M) | TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_S_RW); - tzc_configure_region(3, CFG_SHMEM_START, + tzc_configure_region(3, (CFG_SHMEM_START - DRAM0_BASE), TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4M) | TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); @@ -346,14 +348,17 @@ static int board_imx_tzasc_configure(vaddr_t addr) tzc_configure_region(0, 0x00000000, TZC_ATTR_SP_S_RW); + /* + * Like with i.MX 8MQ, The DDR mapping seems to start at 0. + */ tzc_configure_region(1, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_2G) | TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_NS_RW); - tzc_configure_region(2, CFG_TZDRAM_START, + tzc_configure_region(2, (CFG_TZDRAM_START - DRAM0_BASE), TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_32M) | TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_S_RW); - tzc_configure_region(3, CFG_SHMEM_START, + tzc_configure_region(3, (CFG_SHMEM_START - DRAM0_BASE), TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4M) | TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); |