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The upstream arm-trusted-firmware reserves 0x10100000-0x10300000 for
secure DRAM. Change the address according to the upstream A-T-F.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
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Tested-by: Victor Chong <victor.chong@linaro.org> (hikey aosp)
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org> (poplar)
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org> (rpi3)
Tested-by: Joakim Bech <joakim.bech@linaro.org> (RPi3)
Tested-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> (RCAR M3)
Tested-by: Joseph Chen <chenjh@rock-chips.com> (RK322X)
Tested-by: Kevin Peng <kevinp@marvell.com> (Armada 7K, 8K, 3700)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (NXP - LS1046A-RDB)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1, GP)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2120/b2260, GP)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960, GP)
Tested-by: Andrew F. Davis <afd@ti.com> (TI platforms)
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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Makes stack trace robust by checking addresses before copying data.
Kernel stack traces are a bit more relaxed as we have crashed already.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960 AArch32, Aarch64)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno, QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Prior to this patch assign_mobj_to_param_mem() stored the offset
supplied with a non-contiguous buffer in mem->offs. Since that offset
already is stored inside the resulting MOBJ that offset is added twice.
This patch fixes this by initializing mem->offs to 0 instead.
Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Once non-secure DDR is discovered either via FDT or via register_ddr()
maximum output address is updated.
Note that is only has an effect in AArch64.
Fixes: https://github.com/OP-TEE/optee_os/issues/2402
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Suggested-by: Jean-Paul Etienne <jean-paul.etienne@arm.com>
Reported-by: Rouven Czerwinski <rouven@czerwinskis.de>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno, FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Use MIN_UNSAFE/MAX_UNSAFE macros as MAX/MIN macros fail to build
from in current platform_config.h imaplement with the error trace
below:
In file included from core/arch/arm/include/arm.h:8:0,
from core/arch/arm/include/kernel/thread.h:11,
from core/arch/arm/kernel/asm-defines.c:7:
lib/libutils/ext/include/util.h:24:16: error: missing binary operator before token "("
(__extension__({ __typeof__(a) _a = (a); \
^
core/arch/arm/plat-stm/./platform_config.h:190:25: note: in expansion of macro ‘MAX’
#define STM_SECDDR_END MAX(TZSRAM_BASE + TZSRAM_SIZE, \
^~~
core/arch/arm/plat-stm/./platform_config.h:204:6: note: in expansion of macro ‘STM_SECDDR_END’
#if (STM_SECDDR_END < 0x80000000ULL)
^~~~~~~~~~~~~~
make: *** [out/core/include/generated/.asm-defines.s] Error 1
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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This change allows one to use MAX_UNSAFE() and MIN_UNSAFE() macros
in particular conditions where MAX()/MIN() macros fail to build
from C source file implementation with error traces as below:
In file included from core/arch/arm/include/arm.h:8:0,
from core/arch/arm/include/kernel/thread.h:11,
from core/arch/arm/kernel/asm-defines.c:7:
lib/libutils/ext/include/util.h:24:16: error: missing binary operator before token "("
(__extension__({ __typeof__(a) _a = (a); \
^
core/arch/arm/plat-stm/./platform_config.h:190:25: note: in expansion of macro ‘MAX’
#define STM_SECDDR_END MAX(TZSRAM_BASE + TZSRAM_SIZE, \
^~~
core/arch/arm/plat-stm/./platform_config.h:204:6: note: in expansion of macro ‘STM_SECDDR_END’
#if (STM_SECDDR_END < 0x80000000ULL)
^~~~~~~~~~~~~~
make: *** [out/core/include/generated/.asm-defines.s] Error 1
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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When a TA dump is processed, there is a list of ELF files just before the
call stack. However, when analyzing a TEE core dump, there is no such
list. Make sure this situation is properly handled to avoid displaying a
spurious message. This means fixing incorrect indentation in a
conditional.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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Having -Werror turned on by default can be annoying, because not everyone
uses the same compiler, and different compiler versions have different
warnings.
Therefore, provide CFG_WERROR to turn it on instead. Enable CFG_WERROR in
the CI scripts because we still don't want warnings with the officially
supported compilers.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
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Fixes: https://github.com/OP-TEE/optee_os/issues/2418
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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In case if timestamp buffer is allocated in userspace and new register
user memory API is used for its registering in OP-TEE (introduced in
optee_client commit 27888d73d156 ("tee_client_api: register user memory")),
there is no possibility to keep this mapping permanent among different
TEEC_InvokeCommand invocations, as all SHM are automatically unmapped from
OP-TEE VA space after TEEC_InvokeCommand is handled by OP-TEE.
Timestamp buffer is now allocated with thread_rpc_alloc_global_payload().
Fixes: https://github.com/OP-TEE/optee_os/issues/1979
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
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With the introduction of dynamically linked TAs, symbolize.py may
encounter undefined (external) symbols when it parses the output of the nm
command looking for a symbol's address. The current code is not prepared
for that and will raise an exception. Fix the issue by ignoring lines that
have an unexpected format.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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Add support of allocating SHM shared with non-secure kernel
and exported to a non-secure userspace application.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
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objectSize/keySize was not getting updated when an ECDSA/ECDH
object was imported.
Updating the ObjectSize/keySize based on the EC Curve.
Fixes: https://github.com/OP-TEE/optee_os/issues/2386
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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OP-TEE core images are reformatted into a STM32 compliant format
expected by the platform flashing tools.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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Used by platform stm32mp1.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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Introduce platform stm32mp1 with board stm32mp1-stm32mp157c-ev1 based
on stm32mp1 SoC family integrating Arm Cortex-A7 technology. In its
default configuration, stm32mp1 OP-TEE core operates in a 256kB secure
RAM with pager support enabled.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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Removes get_rng_array() in favor of crypto_rng_read() which always uses
the configured RNG implementation to draw random.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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MPA is used in two configurations, either in kernel mode or in user mode.
In kernel mode random is always drawn with crypto_rng_read() and in
user mode utee_cryp_random_number_generate() is used instead.
This patch makes the code easier to follow by replacing the call via a
function pointer to a normal function call instead.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Adds a new cryptographically secure pseudo random number generator known
as Fortuna. The implementation is based on the description in [0]. This
implementation replaces the implementation in LTC which was used until
now.
Gathering of entropy has been refined with crypto_rng_add_event() to
better match how entropy is added to Fortuna. A enum crypto_rng_src
identifies the source of the event. The source also controls how the
event is added. There are two options available, queue it in a circular
buffer for later processing or adding it directly to a pool. The former
option is suitable when being called from an interrupt handler or some
other place where RPC to normal world is forbidden.
plat_prng_add_jitter_entropy_norpc() is removed and
plat_prng_add_jitter_entropy() is updated to use this new entropy source
scheme.
The configuration of LTC is simplified by this, now PRNG is always drawn
via prng_mpa_desc.
plat_rng_init() takes care of initializing the PRNG in order to allow
platforms to override or enhance the Fortuna integration.
[0] Link:https://www.schneier.com/academic/paperfiles/fortuna.pdf
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Splits tee_pager_init() into tee_pager_set_alias_area() and
tee_pager_generate_authenc_key(). The former function is called where
tee_pager_init() used to be called and the latter function is called
after the crypto API and RNG has been initialized.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Since the two addresses are already of type struct core_mmu_phys_mem, do
not divide by sizeof(struct core_mmu_phys_mem). This broke dynamic shared
memory on Juno r0, since nelem would be zero for two slots.
Tested on Juno r0.
Fixes: 2f82082fada3 ("core: add ddr overall register")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Rouven Czerwinski <rouven@czerwinskis.de>
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Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
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This commit adds maintainer for this board.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
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Initial version support for Allwinner H2+ platform. Specific to Banana Pi
M2 zero board currently.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
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checkpatch will check if udelay value is too large. Use udelay() to
implement mdelay() when we want to delay more than 10000 us.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
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Add DT support for serial8250 uart driver. The matchtable currently
supports allwinner H2+ SoC.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
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Add platform 'k3' for the TI K3 family. These are ARMv8 devices
and are quite different from our line of existing ARMv7 OMAP style
SoCs, hence the new platform.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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Update the Aarch64 Crypto Extension accelerated CBC encryption/decryption
routines to the latest upstream implementation in the Linux kernel
(v4.17-rc7).
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960)
CC: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Fixes: https://github.com/OP-TEE/optee_os/issues/2355
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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Now that the Travis container-based environment is running Ubuntu Trusty
(14.04), some downloads and build steps are not needed anymore. Use the
tools that come with the distribution instead.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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The default ccache directory used by buildroot is ~/.buildroot-ccache [1],
which is outside the paths saved by the Travis caching mechanism [2]. Fix
that by adding BR2_CCACHE_DIR=~/.ccache to the make command.
Link: [1] https://buildroot.org/downloads/manual/manual.html#ccache
Link: [2] https://docs.travis-ci.com/user/caching/#ccache-cache
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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Keepalive condition check should involve single instance flag too, since
the keepalive flag is meaningless if the TA is not single instance.
The same fix was done earlier in the core by commit f9a64f12b542 ("core:
fix the keepalive condition in close session").
Fixes: b7ea03ff2963 ("libutee: fix TA_CreateEntryPoint() and TA_DestroyEntryPoint()")
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Defines MBEDTLS_X509_CHECK_KEY_USAGE to enable checking key usage of a
certificate.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Prior to this patch when syscall_cryp_obj_get_attr() is called with a
NULL buffer to query buffer size the function returns
TEE_ERROR_ACCESS_DENIED while TEE_ERROR_SHORT_BUFFER is expected. This
patch fixes syscall_cryp_obj_get_attr() to return TEE_ERROR_SHORT_BUFFER
if supplied buffer parameter is NULL.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Signed-off-by: Yongqin Liu <yongqin.liu@linaro.org>
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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Try to speed up the Shippable CI by re-introducing parallel builds, which
were removed by commit c330283b4a00 ("ci: .shippable.yml: disable parallel
build") due to random build errors. Although the root cause was never
identified, there are reasons to believe that the issue may not be
reproducible anymore:
- The container environment has likely seen updates
- Commit 836334a163f9 ("ci: shippable: set build directory identically for
all platforms") has modified the output paths, so a race condition on
directory creation seems quite unlikely to happen.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
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There is a problem with how the counter is incremented in our Aarch32
implementation of ce_aes_ctr_encrypt(). When 3 or more 16-byte blocks of
data are processed, the counter is incremented one time too many and
invalid data is produced as a result [1].
More generally, the way the counter is handled is quite convoluted. It is
incremented:
- In the generic LibTomCrypt code in ctr_encrypt_sub(),
- In the Crypto Extension glue layer in aes_ctr_encrypt_nblocks(),
- In the CE accelerated assembly code in ce_aes_ctr_encrypt().
We can easily get rid of the second one. We can also avoid always calling
the non-accelerated function on the first block of data.
This commit simplifies the C code to reflect the following rules:
- The core encryption functions (accelerated or not) should use the
counter value as is to process the first block of data,
- They should increment it for each block that is processed and return it
as an output parameter
The AArch32 and AArch64 CE assembler implementations are updated to the
latest available in the upstream Linux kernel (v4.17-rc7), thus
incorporating further improvements/simplifications by Ard Biesheuvel.
These functions handle the counter as described above so they fit our use
case perfectly.
Fixes: [1] https://github.com/OP-TEE/optee_os/issues/2305
CC: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960, 32/64, CE/no CE)
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Except for very special cases (such as virtualization), the number of CPU
cores that can enter OP-TEE is a fixed number that depends on the hardware
configuration and should not be configurable at build time.
Therefore, use $(call force,CFG_TEE_CORE_NB_CORE,<value>) to set the
value.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Further improve the ccache hit rate by setting the build directory
to be the same for all platforms. Prior to this, only the build for
the same platform could share cached files, because the file path is
part of the hash.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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There is currently no caching possible between the various _make lines in
.shippable.yml, because they select different configuration flags. Since
all the files include $(out-dir)/include/generated/conf.h automatically,
the preprocessor output is therefore different simply due to the fact that
conf.h is different from one line to the other.
This is quite unfortunate, because most source files depend on a handful
of configuration flags only and therefore activating unrelated flags
should not cause a cache miss.
Addressing this problem is exactly the purpose of the 'unify' option of
ccache [1]. Activate it by setting CCACHE_UNIFY=true and CFG_DEBUG_INFO=n
before building. The lines that set DEBUG=0 or DEBUG=1 are adjusted to
produce the same result as before.
Link: [1] https://github.com/ccache/ccache/blob/v3.4.2/doc/MANUAL.adoc#configuration-settings
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Introduces CFG_CC_OPTIMIZE_FOR_SIZE (default y) which selects the C
compiler flag -Os and -O0 otherwise, and CFG_DEBUG_INFO (default y)
which selects the C compiler flag -g3 and assembler flag -g.
DEBUG=1 is kept for compatibility.
Being able to compile without -g is useful to get much better performance
from ccache thanks to its 'unify' option [1].
Link: https://github.com/ccache/ccache/blob/v3.4.2/doc/MANUAL.adoc#configuration-settings
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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PLATFORM=imx-mx7dsabresd
Name Before After
TEE_RAM_START be000000 be000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START be100000 be100000
TA_RAM_SIZE 01d00000 01d00000
TEE_SHMEM_START bfe00000 bfe00000
TEE_SHMEM_SIZE 00200000 00200000
TZDRAM_BASE be000000 be000000
TZDRAM_SIZE 01e00000 01e00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR be000000 be000000
TEE_RAM_VA_SIZE 00100000 00100000
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
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PLATFORM=imx-mx6sxsabreauto
Name Before After
TEE_RAM_START fe000000 fe000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START fe100000 fe100000
TA_RAM_SIZE 01d00000 01d00000
TEE_SHMEM_START ffe00000 ffe00000
TEE_SHMEM_SIZE 00200000 00200000
TZDRAM_BASE fe000000 fe000000
TZDRAM_SIZE 01e00000 01e00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR fe000000 fe000000
TEE_RAM_VA_SIZE 00100000 00100000
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
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PLATFORM=imx-mx6ulevk
Name Before After
TEE_RAM_START 9e000000 9e000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START 9e100000 9e100000
TA_RAM_SIZE 01d00000 01d00000
TEE_SHMEM_START 9fe00000 9fe00000
TEE_SHMEM_SIZE 00200000 00200000
TZDRAM_BASE 9e000000 9e000000
TZDRAM_SIZE 01e00000 01e00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR 9e000000 9e000000
TEE_RAM_VA_SIZE 00100000 00100000
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
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The 'after' values are computed with the fix to TA_RAM_SIZE.
PLATFORM=imx-mx6qsabresd CFG_WITH_PAGER=n
Name Before After
TEE_RAM_START 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START 4e100000 4e100000
TA_RAM_SIZE 01e00000 01e00000
TEE_SHMEM_START 4ff00000 4ff00000
TEE_SHMEM_SIZE 00100000 00100000
TZDRAM_BASE 4e000000 4e000000
TZDRAM_SIZE 01f00000 01f00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000
PLATFORM=imx-mx6qsabresd CFG_WITH_PAGER=y
Name Before After
TEE_RAM_START 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START 4e100000 4e100000
TA_RAM_SIZE 01e00000 01e00000
TEE_SHMEM_START 4ff00000 4ff00000
TEE_SHMEM_SIZE 00100000 00100000
TZDRAM_BASE 4e000000 4e000000
TZDRAM_SIZE 01f00000 01f00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
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