diff options
| author | Jun Nie <jun.nie@linaro.org> | 2018-09-04 12:08:07 +0800 |
|---|---|---|
| committer | Jun Nie <jun.nie@linaro.org> | 2018-09-04 14:32:05 +0800 |
| commit | 02cb24cd2b8e1211a59f113eb38415aa6ff2be0f (patch) | |
| tree | fe3bd66c35e36866678a3fc856b471960eb03df7 | |
| parent | 17391dd0a372e6df23061e7622144f911e12f048 (diff) | |
Aarch32: adjust pc register after IRQ routine
Adjust pc register after IRQ routine because CPU pipeline
increase the pc value while the instruction is not excuted
yet when IRQ interrupt pipeline.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
| -rw-r--r-- | framework/aarch32/exceptions.S | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/framework/aarch32/exceptions.S b/framework/aarch32/exceptions.S index 63e11df..00353d7 100644 --- a/framework/aarch32/exceptions.S +++ b/framework/aarch32/exceptions.S @@ -50,11 +50,18 @@ vector_base tftf_vector */ func tftf_intr_handle push {r0 - r3, lr} +#if ARM_ARCH_MAJOR == 7 + mrs lr, spsr + push {lr} +#endif bl tftf_irq_handler_dispatcher - pop {r0 - r3, lr} #if ARM_ARCH_MAJOR == 8 + pop {r0 - r3, lr} eret #else - movs pc, lr + pop {lr} + msr spsr_cxsf, lr + pop {r0 - r3, lr} + subs pc, lr, #4 #endif endfunc tftf_intr_handle |