Reorganize tests manifest files.

Split tests-common.xml in several individual tests manifests that
focus on one feature to test.

This has 2 advantages.

1. It is easier to maintain small tests manifests rather than a
   single, big one that contains all tests and keeps growing and
   growing over time.

2. It is now possible to run tests in isolation, e.g. only SDEI tests
   by selecting the SDEI tests manifest.

This patch also includes the "Performance" tests in the common tests.

Change-Id: I9b722bcb1658740476605be5157825a9e160bcbf

15 files changed, 478 insertions, 203 deletions

diff --git a/plat/arm/board/juno/tests.xml b/plat/arm/board/juno/tests.xml
index 4731014..8f77bd1 100644
--- a/plat/arm/board/juno/tests.xml
+++ b/plat/arm/board/juno/tests.xml
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="utf-8"?>
 
 <!--
-  Copyright (c) 2017, ARM Limited. All rights reserved.
+  Copyright (c) 2017-2018, ARM Limited. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -12,15 +12,32 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 -->
 
-<!-- External reference to the common tests file -->
+<!-- External references to all individual tests files. -->
 <!DOCTYPE testsuites [
-  <!ENTITY common-tests SYSTEM "../../../../tests/tests-common.xml">
+  <!ENTITY tests-tftf-validation SYSTEM "../../../../tests/tests-tftf-validation.xml">
+  <!ENTITY tests-psci SYSTEM "../../../../tests/tests-psci.xml">
+  <!ENTITY tests-spm SYSTEM "../../../../tests/tests-spm.xml">
+  <!ENTITY tests-sdei SYSTEM "../../../../tests/tests-sdei.xml">
+  <!ENTITY tests-rt-instr SYSTEM "../../../../tests/tests-runtime-instrumentation.xml">
+  <!ENTITY tests-tsp SYSTEM "../../../../tests/tests-tsp.xml">
+  <!ENTITY tests-el3-pstate SYSTEM "../../../../tests/tests-el3-power-state.xml">
+  <!ENTITY tests-state-switch SYSTEM "../../../../tests/tests-arm-state-switch.xml">
+  <!ENTITY tests-cpu-extensions SYSTEM "../../../../tests/tests-cpu-extensions.xml">
+  <!ENTITY tests-performance SYSTEM "../../../../tests/tests-performance.xml">
 ]>
 
 <testsuites>
 
-  <!-- Include the common tests -->
-  &common-tests;
+  &tests-tftf-validation;
+  &tests-psci;
+  &tests-spm;
+  &tests-sdei;
+  &tests-rt-instr;
+  &tests-tsp;
+  &tests-el3-pstate;
+  &tests-state-switch;
+  &tests-cpu-extensions;
+  &tests-performance;
 
   <testsuite name="Juno - IRQ support in TSP" description="Test the normal IRQ preemption support in TSP.">
     <testcase name="Juno - Multicore spurious interrupt test" function="test_juno_multicore_spurious_interrupt" />
diff --git a/tests/tests-arm-state-switch.xml b/tests/tests-arm-state-switch.xml
new file mode 100644
index 0000000..a681abe
--- /dev/null
+++ b/tests/tests-arm-state-switch.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+  Copyright (c) 2018, ARM Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+-->
+
+<testsuites>
+  <!--
+      Test suite exercising execution state switch SiP service.
+
+      'test_exec_state_switch_reset_before' must execute first in the suite, and
+      'test_exec_state_switch_after_cpu_on' the last. See comments in
+      test_exec_state_switch.c for details.
+  -->
+  <testsuite name="State switch" description="Test ARM SiP State Switch service">
+    <testcase name="System reset before state switch" function="test_exec_state_switch_reset_before" />
+    <testcase name="Request state switch with invalid PC" function="test_exec_state_switch_invalid_pc" />
+    <testcase name="Request state switch with invalid context" function="test_exec_state_switch_invalid_ctx" />
+    <testcase name="Request a valid state switch" function="test_exec_state_switch_valid" />
+    <testcase name="Request a valid state switch after CPU_ON" function="test_exec_state_switch_after_cpu_on" />
+  </testsuite>
+
+</testsuites>
diff --git a/tests/tests-common.xml b/tests/tests-common.xml
index a914be2..b384c49 100644
--- a/tests/tests-common.xml
+++ b/tests/tests-common.xml
@@ -6,188 +6,32 @@
   SPDX-License-Identifier: BSD-3-Clause
 -->
 
-<testsuites>
-
-  <!--
-     The "template" testsuite aims at providing template test code as a
-     starting point for developing new tests. These tests don't do anything
-     useful in terms of testing so they are disabled by default. Uncomment
-     those lines along with the corresponding source files in the Makefile
-     tests/tests.mk to enable them.
-  -->
-  <!--
-  <testsuite name="Template" description="Template test code">
-     <testcase name="Single core test" function="test_template_single_core" />
-     <testcase name="Multi core test" function="test_template_multi_core" />
-  </testsuite>
-  -->
-
-  <testsuite name="Framework Validation" description="Validate the core features of the test framework">
-    <testcase name="NVM support" function="test_validation_nvm" />
-    <testcase name="NVM serialisation" function="test_validate_nvm_serialisation" />
-    <testcase name="Events API" function="test_validation_events" />
-    <testcase name="IRQ handling" function="test_validation_irq" />
-    <testcase name="SGI support" function="test_validation_sgi" />
-  </testsuite>
-
-  <testsuite name="SPM" description="SPM test framework">
-     <testcase name="SPM NS interrupts test" function="test_secure_partition_interrupt_by_ns" />
-     <testcase name="SPM secondary CPUs sequential test" function="test_secure_partition_secondary_cores_seq" />
-     <testcase name="SPM secondary CPUs simultaneous test" function="test_secure_partition_secondary_cores_sim" />
-  </testsuite>
-
-  <testsuite name="SDEI" description="SDEI test framework">
-     <testcase name="SDEI event handler state machine testing" function="test_sdei_state" />
-     <testcase name="SDEI event handling on all cores in sequence" function="test_sdei_event_serial" />
-     <testcase name="SDEI event handling on all cores in parallel" function="test_sdei_event_parallel" />
-     <testcase name="SDEI event signaling: each core signals itself" function="test_sdei_event_signal_serial" />
-     <testcase name="SDEI event signaling: one core signals all others" function="test_sdei_event_signal_all" />
-  </testsuite>
-
-  <testsuite name="Runtime Instrumentation Validation" description="Validate PMF Runtime Instrumentation">
-     <testcase name="Suspend to deepest power level on all cores in parallel" function="test_rt_instr_susp_deep_parallel" />
-     <testcase name="Suspend to deepest power level on all cores in sequence" function="test_rt_instr_susp_deep_serial" />
-     <testcase name="CPU suspend on all cores in parallel" function="test_rt_instr_cpu_susp_parallel" />
-     <testcase name="CPU suspend on all cores in sequence" function="test_rt_instr_cpu_susp_serial" />
-     <testcase name="CPU off on all non-lead cores in sequence and suspend lead to deepest power level" function="test_rt_instr_cpu_off_serial" />
-     <testcase name="PSCI version call on all cores in parallel" function="test_rt_instr_psci_version_parallel" />
-  </testsuite>
-
-  <testsuite name="Timer framework Validation" description="Validate the timer driver and timer framework">
-     <testcase name="Verify the timer interrupt generation" function="test_timer_framework_interrupt" />
-     <testcase name="Target timer to a power down cpu" function="test_timer_target_power_down_cpu" />
-     <testcase name="Test scenario where multiple CPUs call same timeout" function="test_timer_target_multiple_same_interval" />
-     <testcase name="Stress test the timer framework" function="stress_test_timer_framework" />
-  </testsuite>
-
-  <testsuite name="PSCI System Suspend Validation" description="Validate PSCI System Suspend API">
-     <testcase name="System suspend multiple times" function="test_psci_sys_susp_multiple_iteration" />
-     <testcase name="system suspend from all cores" function="test_system_suspend_from_all_cores" />
-     <testcase name="System suspend with cores on" function="test_psci_sys_susp_with_cores_on" />
-     <testcase name="Suspend system with cores in suspend" function="test_psci_sys_susp_with_cores_in_suspend" />
-     <testcase name="Validate suspend to RAM functionality" function="test_psci_sys_susp_validate_ram" />
-     <testcase name="System suspend with invalid entrypoint address" function="test_system_suspend_invalid_entrypoint" />
-     <testcase name="System suspend with pending IRQ" function="test_psci_sys_susp_pending_irq" />
-  </testsuite>
-
-  <testsuite name="Query runtime services" description="Generic queries as defined by the SMCCC">
-    <testcase name="Query Standard Service" function="test_query_std_svc" />
-  </testsuite>
-
-  <testsuite name="PSCI Version" description="Check the version of PSCI implemented">
-    <testcase name="PSCI Version" function="test_psci_version" />
-  </testsuite>
-
-  <testsuite name="PSCI Affinity Info" description="Test PSCI AFFINITY_INFO support">
-    <testcase name="Affinity info level0 on" function="test_affinity_info_level0_on" />
-    <testcase name="Affinity info level0 off" function="test_affinity_info_level0_off" />
-    <testcase name="Affinity info level1 on" function="test_affinity_info_level1_on" />
-    <testcase name="Affinity info level1 off" function="test_affinity_info_level1_off" />
-    <testcase name="Affinity info level2" function="test_affinity_info_level2" />
-    <testcase name="Affinity info level3" function="test_affinity_info_level3" />
-    <testcase name="Affinity info level0 powerdown" function="test_affinity_info_level0_powerdown" />
-  </testsuite>
-
-  <testsuite name="CPU Hotplug" description="Test PSCI CPU Hotplug support">
-    <testcase name="CPU hotplug" function="test_psci_cpu_hotplug" />
-    <testcase name="CPU already on" function="test_psci_cpu_hotplug_plugged" />
-    <testcase name="Context ID passing" function="test_context_ids" />
-    <testcase name="Invalid CPU" function="test_psci_cpu_hotplug_invalid_cpu" />
-    <testcase name="Invalid entry point" function="test_psci_cpu_hotplug_invalid_ep" />
-  </testsuite>
 
-  <testsuite name="PSCI CPU Suspend" description="Test PSCI CPU Suspend support">
-    <testcase name="CPU suspend to powerdown at level 0" function="test_psci_suspend_powerdown_level0" />
-    <testcase name="CPU suspend to powerdown at level 1" function="test_psci_suspend_powerdown_level1" />
-    <testcase name="CPU suspend to powerdown at level 2" function="test_psci_suspend_powerdown_level2" />
-    <testcase name="CPU suspend to powerdown at level 3" function="test_psci_suspend_powerdown_level3" />
+<!-- External references to all individual tests files. -->
+<!DOCTYPE testsuites [
+  <!ENTITY tests-tftf-validation SYSTEM "tests-tftf-validation.xml">
+  <!ENTITY tests-psci SYSTEM "tests-psci.xml">
+  <!ENTITY tests-spm SYSTEM "tests-spm.xml">
+  <!ENTITY tests-sdei SYSTEM "tests-sdei.xml">
+  <!ENTITY tests-rt-instr SYSTEM "tests-runtime-instrumentation.xml">
+  <!ENTITY tests-tsp SYSTEM "tests-tsp.xml">
+  <!ENTITY tests-el3-pstate SYSTEM "tests-el3-power-state.xml">
+  <!ENTITY tests-state-switch SYSTEM "tests-arm-state-switch.xml">
+  <!ENTITY tests-cpu-extensions SYSTEM "tests-cpu-extensions.xml">
+  <!ENTITY tests-performance SYSTEM "tests-performance.xml">
+]>
 
-    <testcase name="CPU suspend to standby at level 0" function="test_psci_suspend_standby_level0" />
-    <testcase name="CPU suspend to standby at level 1" function="test_psci_suspend_standby_level1" />
-    <testcase name="CPU suspend to standby at level 2" function="test_psci_suspend_standby_level2" />
-    <testcase name="CPU suspend to standby at level 3" function="test_psci_suspend_standby_level3" />
-  </testsuite>
-
-  <testsuite name="EL3 power state parser validation" description="Validation of EL3 power state parsing algorithm">
-    <testcase name="Create all power states and validate EL3 power state parsing" function="test_psci_validate_pstate" />
-    <testcase name="Create only local power state and validate EL3 power state parsing" function="test_psci_valid_local_pstate" />
-    <testcase name="Create invalid local power state at all levels and validate EL3 power state parsing" function="test_psci_invalid_stateID" />
-    <testcase name="Create invalid power state type and validate EL3 power state parsing" function="test_psci_invalid_state_type" />
-    <testcase name="Create invalid power level and validate EL3 power state parsing for original state format" function="test_psci_invalid_power_level" />
-    <testcase name="Create a power state with valid and invalid local state ID at different levels and validate power state parsing" function="test_psci_mixed_state_id" />
-  </testsuite>
-
-  <testsuite name="PSCI STAT" description="Test PSCI STAT support Core level">
-    <testcase name="for valid composite state CPU suspend" function="test_psci_stat_all_power_states" />
-    <testcase name="Stats test cases for CPU OFF" function="test_psci_stats_cpu_off" />
-    <testcase name="Stats test cases after system suspend" function="test_psci_stats_system_suspend" />
-  </testsuite>
-
-  <testsuite name="PSCI NODE_HW_STATE" description="Test PSCI NODE_HW_STATE API">
-    <testcase name="Tests for NODE_HW_STATE" function="test_psci_node_hw_state" />
-    <testcase name="Tests for NODE_HW_STATE on multicluster" function="test_psci_node_hw_state_multi" />
-  </testsuite>
-
-  <testsuite name="PSCI Features" description="Check the PSCI features implemented">
-    <testcase name="PSCI Features" function="test_psci_features" />
-    <testcase name="PSCI Invalid Features" function="test_psci_features_invalid_id" />
-  </testsuite>
-
-  <testsuite name="PSCI MIGRATE_INFO_TYPE" description="Test MIGRATE_INFO_TYPE support">
-     <testcase name="PSCI MIGRATE_INFO_TYPE" function="test_migrate_info_type" />
-  </testsuite>
-
-  <testsuite name="PSCI mem_protect_check" description="Check the mem_protect_check_range feature">
-    <testcase name="PSCI mem_protect_check" function="test_mem_protect_check" />
-  </testsuite>
-
-  <testsuite name="TSP handler standard functions result test" description="Validate TSP SMC standard function call">
-     <testcase name="TestSecurePayload standard functions service call" function="test_smc_tsp_std_fns_call" />
-  </testsuite>
-
-  <testsuite name="Stress test TSP functionality" description="Validate TSP functionality">
-     <testcase name="Stress test TSP functionality" function="test_tsp_fast_smc_operations" />
-  </testsuite>
-
-  <testsuite name="IRQ support in TSP" description="Test the normal IRQ preemption support in TSP.">
-    <testcase name="TSP preempt by IRQ and resume" function="tsp_int_and_resume" />
-    <testcase name="Fast SMC while TSP preempted" function="test_fast_smc_when_tsp_preempted" />
-    <testcase name="STD SMC resumption while TSP preempted" function="test_std_smc_when_tsp_preempted_resume" />
-    <testcase name="STD SMC abortion while TSP preempted" function="test_std_smc_when_tsp_preempted_abort" />
-    <testcase name="Resume SMC without TSP preemption" function="test_resume_smc_without_preemption" />
-    <testcase name="Stress TSP preemption and resumption" function="tsp_int_and_resume_stress" />
-    <testcase name="Test Secure FIQ while TSP is preempted" function="tsp_fiq_while_int" />
-    <testcase name="Resume preempted STD SMC" function="test_irq_preempted_std_smc" />
-    <testcase name="Resume preempted STD SMC from other CPUs" function="test_resume_preempted_std_smc_other_cpus" />
-    <testcase name="Resume STD SMC from different CPUs" function="test_resume_different_cpu_preempted_std_smc" />
-    <testcase name="Resume preempted STD SMC after PSCI CPU OFF/ON cycle" function="test_psci_cpu_on_off_preempted_std_smc" />
-    <!-- The following test fails on some FVP configs. See GENFW-2230 -->
-    <!-- <testcase name="Resume preempted STD SMC after PSCI CPU SUSPEND" function="test_psci_cpu_suspend_preempted_std_smc" /> -->
-    <testcase name="Resume preempted STD SMC after PSCI SYSTEM SUSPEND" function="test_psci_system_suspend_preempted_std_smc" />
-  </testsuite>
-
-  <!-- Test suite exercising execution state switch SiP service.
-       'test_exec_state_switch_reset_before' must execute first in the suite,
-       and 'test_exec_state_switch_after_cpu_on' the last. See comments in
-       test_exec_state_switch.c for details -->
-  <testsuite name="State switch" description="Test ARM SiP State Switch service">
-    <testcase name="System reset before state switch" function="test_exec_state_switch_reset_before" />
-    <testcase name="Request state switch with invalid PC" function="test_exec_state_switch_invalid_pc" />
-    <testcase name="Request state switch with invalid context" function="test_exec_state_switch_invalid_ctx" />
-    <testcase name="Request a valid state switch" function="test_exec_state_switch_valid" />
-    <testcase name="Request a valid state switch after CPU_ON" function="test_exec_state_switch_after_cpu_on" />
-  </testsuite>
+<testsuites>
 
-  <testsuite name="CPU extensions" description="Various CPU extensions tests">
-    <testcase name="AMUv1 non-zero counters" function="test_amu_nonzero_ctr" />
-    <testcase name="AMUv1 suspend/resume" function="test_amu_suspend_resume" />
-  </testsuite>
+  &tests-tftf-validation;
+  &tests-psci;
+  &tests-spm;
+  &tests-sdei;
+  &tests-rt-instr;
+  &tests-tsp;
+  &tests-el3-pstate;
+  &tests-state-switch;
+  &tests-cpu-extensions;
+  &tests-performance;
 
 </testsuites>
-
-  <!-- This testsuite crashes the firmware.
-       A final report will *NOT* be generated. -->
-  <!--testsuite name="Test Crash reporting" description="Test the Unhandled Exception Reporting in EL3.">
-    <testcase name="Access Secure memory crash " function="tsp_crash_reporting_test1" />
-    <testcase name="Access 32 bit register as 64 bit crash" function="tsp_crash_reporting_test2" />
-  </testsuite-->
diff --git a/tests/tests-cpu-extensions.xml b/tests/tests-cpu-extensions.xml
new file mode 100644
index 0000000..e89b92d
--- /dev/null
+++ b/tests/tests-cpu-extensions.xml
@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+  Copyright (c) 2018, ARM Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+-->
+
+<testsuites>
+
+  <testsuite name="CPU extensions" description="Various CPU extensions tests">
+    <testcase name="AMUv1 non-zero counters" function="test_amu_nonzero_ctr" />
+    <testcase name="AMUv1 suspend/resume" function="test_amu_suspend_resume" />
+  </testsuite>
+
+</testsuites>
diff --git a/tests/tests-crash-reporting.xml b/tests/tests-crash-reporting.xml
new file mode 100644
index 0000000..a2c9940
--- /dev/null
+++ b/tests/tests-crash-reporting.xml
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+  Copyright (c) 2018, ARM Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+-->
+
+<testsuites>
+
+  <!-- This testsuite crashes the firmware. A final report will *NOT* be generated. -->
+  <testsuite name="Test Crash reporting" description="Test the Unhandled Exception Reporting in EL3.">
+    <testcase name="Access Secure memory crash " function="tsp_crash_reporting_test1" />
+    <testcase name="Access 32 bit register as 64 bit crash" function="tsp_crash_reporting_test2" />
+  </testsuite>
+
+</testsuites>
diff --git a/tests/tests-el3-power-state.xml b/tests/tests-el3-power-state.xml
new file mode 100644
index 0000000..ca3ae8b
--- /dev/null
+++ b/tests/tests-el3-power-state.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+  Copyright (c) 2018, ARM Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+-->
+
+<testsuites>
+
+  <testsuite name="EL3 power state parser validation" description="Validation of EL3 power state parsing algorithm">
+    <testcase name="Create all power states and validate EL3 power state parsing" function="test_psci_validate_pstate" />
+    <testcase name="Create only local power state and validate EL3 power state parsing" function="test_psci_valid_local_pstate" />
+    <testcase name="Create invalid local power state at all levels and validate EL3 power state parsing" function="test_psci_invalid_stateID" />
+    <testcase name="Create invalid power state type and validate EL3 power state parsing" function="test_psci_invalid_state_type" />
+    <testcase name="Create invalid power level and validate EL3 power state parsing for original state format" function="test_psci_invalid_power_level" />
+    <testcase name="Create a power state with valid and invalid local state ID at different levels and validate power state parsing" function="test_psci_mixed_state_id" />
+  </testsuite>
+
+</testsuites>
diff --git a/tests/tests-extensive.xml b/tests/tests-extensive.xml
index f8deba0..a214f54 100644
--- a/tests/tests-extensive.xml
+++ b/tests/tests-extensive.xml
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="utf-8"?>
 
 <!--
-  Copyright (c) 2015-2016, ARM Limited. All rights reserved.
+  Copyright (c) 2015-2018, ARM Limited. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -12,26 +12,36 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 -->
 
-<!-- External reference to the common tests file -->
+
+<!-- External references to all individual tests files. -->
 <!DOCTYPE testsuites [
-  <!ENTITY common-tests SYSTEM "tests-common.xml">
+  <!ENTITY tests-psci-extensive SYSTEM "tests-psci-extensive.xml">
+
+  <!ENTITY tests-tftf-validation SYSTEM "tests-tftf-validation.xml">
+  <!ENTITY tests-psci SYSTEM "tests-psci.xml">
+  <!ENTITY tests-spm SYSTEM "tests-spm.xml">
+  <!ENTITY tests-sdei SYSTEM "tests-sdei.xml">
+  <!ENTITY tests-rt-instr SYSTEM "tests-runtime-instrumentation.xml">
+  <!ENTITY tests-tsp SYSTEM "tests-tsp.xml">
+  <!ENTITY tests-el3-pstate SYSTEM "tests-el3-power-state.xml">
+  <!ENTITY tests-state-switch SYSTEM "tests-arm-state-switch.xml">
+  <!ENTITY tests-cpu-extensions SYSTEM "tests-cpu-extensions.xml">
+  <!ENTITY tests-performance SYSTEM "tests-performance.xml">
 ]>
 
 <testsuites>
-  <testsuite name="PSCI CPU ON OFF Stress Tests" description="Stress-test hotplug">
-    <testcase name="Repeated shutdown of all cores to stress test CPU_ON, CPU_SUSPEND and CPU_OFF" function="psci_on_off_suspend_coherency_test" />
-    <!-- testcase name="Verify PSCI CPU ON race" function="psci_verify_cpu_on_race" / -->
-    <testcase name="PSCI CPU ON OFF stress test" function="psci_cpu_on_off_stress" />
-    <testcase name="PSCI CPU ON OFF SUSPEND stress test" function="psci_cpu_on_off_suspend_stress" />
-    <testcase name="Repeated hotplug of all cores to stress test CPU_ON and CPU_OFF" function="psci_hotplug_stress_test" />
-    <testcase name="Random hotplug cores in a large iteration to stress boot path code" function="psci_hotplug_single_core_stress_test" />
-    <testcase name="Hotplug a cluster in a large iteration to stress cluster on and off functionality" function="psci_cluster_hotplug_stress_test" />
-  </testsuite>
-  <testsuite name="PSCI SYSTEM SUSPEND stress tests" description="Stress-test SYSTEM SUSPEND">
-    <testcase name="Stress test PSCI_SYSTEM_SUSPEND" function="psci_sys_susp_on_off_stress_test" />
-  </testsuite>
-
-  <!-- Include the common tests -->
-  &common-tests;
+
+  &tests-psci-extensive;
+
+  &tests-tftf-validation;
+  &tests-psci;
+  &tests-spm;
+  &tests-sdei;
+  &tests-rt-instr;
+  &tests-tsp;
+  &tests-el3-pstate;
+  &tests-state-switch;
+  &tests-cpu-extensions;
+  &tests-performance;
 
 </testsuites>
diff --git a/tests/tests-psci-extensive.xml b/tests/tests-psci-extensive.xml
new file mode 100644
index 0000000..87368b6
--- /dev/null
+++ b/tests/tests-psci-extensive.xml
@@ -0,0 +1,35 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<testsuites>
+
+<!--
+  Copyright (c) 2018, ARM Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+-->
+
+  <testsuite name="PSCI CPU ON OFF Stress Tests" description="Stress-test hotplug">
+    <testcase name="Repeated shutdown of all cores to stress test CPU_ON, CPU_SUSPEND and CPU_OFF"
+              function="psci_on_off_suspend_coherency_test" />
+    <!-- testcase name="Verify PSCI CPU ON race" function="psci_verify_cpu_on_race" / -->
+    <testcase name="PSCI CPU ON OFF stress test" function="psci_cpu_on_off_stress" />
+    <testcase name="PSCI CPU ON OFF SUSPEND stress test" function="psci_cpu_on_off_suspend_stress" />
+    <testcase name="Repeated hotplug of all cores to stress test CPU_ON and CPU_OFF"
+              function="psci_hotplug_stress_test" />
+    <testcase name="Random hotplug cores in a large iteration to stress boot path code"
+              function="psci_hotplug_single_core_stress_test" />
+    <testcase name="Hotplug a cluster in a large iteration to stress cluster on and off functionality"
+              function="psci_cluster_hotplug_stress_test" />
+  </testsuite>
+
+  <testsuite name="PSCI SYSTEM SUSPEND stress tests" description="Stress-test SYSTEM SUSPEND">
+    <testcase name="Stress test PSCI_SYSTEM_SUSPEND" function="psci_sys_susp_on_off_stress_test" />
+  </testsuite>
+
+</testsuites>
diff --git a/tests/tests-psci.xml b/tests/tests-psci.xml
new file mode 100644
index 0000000..913f8b4
--- /dev/null
+++ b/tests/tests-psci.xml
@@ -0,0 +1,93 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+  Copyright (c) 2018, ARM Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+-->
+
+<testsuites>
+
+  <!--
+      Strictly speaking, this testsuite is not testing PSCI but we put it here
+      nonetheless to avoid having it alone in a separate XML file.
+  -->
+  <testsuite name="Query runtime services" description="Generic queries as defined by the SMCCC">
+    <testcase name="Query Standard Service" function="test_query_std_svc" />
+  </testsuite>
+
+  <testsuite name="PSCI Version" description="Check the version of PSCI implemented">
+    <testcase name="PSCI Version" function="test_psci_version" />
+  </testsuite>
+
+  <testsuite name="PSCI Affinity Info" description="Test PSCI AFFINITY_INFO support">
+    <testcase name="Affinity info level0 on" function="test_affinity_info_level0_on" />
+    <testcase name="Affinity info level0 off" function="test_affinity_info_level0_off" />
+    <testcase name="Affinity info level1 on" function="test_affinity_info_level1_on" />
+    <testcase name="Affinity info level1 off" function="test_affinity_info_level1_off" />
+    <testcase name="Affinity info level2" function="test_affinity_info_level2" />
+    <testcase name="Affinity info level3" function="test_affinity_info_level3" />
+    <testcase name="Affinity info level0 powerdown" function="test_affinity_info_level0_powerdown" />
+  </testsuite>
+
+  <testsuite name="CPU Hotplug" description="Test PSCI CPU Hotplug support">
+    <testcase name="CPU hotplug" function="test_psci_cpu_hotplug" />
+    <testcase name="CPU already on" function="test_psci_cpu_hotplug_plugged" />
+    <testcase name="Context ID passing" function="test_context_ids" />
+    <testcase name="Invalid CPU" function="test_psci_cpu_hotplug_invalid_cpu" />
+    <testcase name="Invalid entry point" function="test_psci_cpu_hotplug_invalid_ep" />
+  </testsuite>
+
+  <testsuite name="PSCI CPU Suspend" description="Test PSCI CPU Suspend support">
+    <testcase name="CPU suspend to powerdown at level 0" function="test_psci_suspend_powerdown_level0" />
+    <testcase name="CPU suspend to powerdown at level 1" function="test_psci_suspend_powerdown_level1" />
+    <testcase name="CPU suspend to powerdown at level 2" function="test_psci_suspend_powerdown_level2" />
+    <testcase name="CPU suspend to powerdown at level 3" function="test_psci_suspend_powerdown_level3" />
+
+    <testcase name="CPU suspend to standby at level 0" function="test_psci_suspend_standby_level0" />
+    <testcase name="CPU suspend to standby at level 1" function="test_psci_suspend_standby_level1" />
+    <testcase name="CPU suspend to standby at level 2" function="test_psci_suspend_standby_level2" />
+    <testcase name="CPU suspend to standby at level 3" function="test_psci_suspend_standby_level3" />
+  </testsuite>
+
+  <testsuite name="PSCI STAT" description="Test PSCI STAT support Core level">
+    <testcase name="for valid composite state CPU suspend" function="test_psci_stat_all_power_states" />
+    <testcase name="Stats test cases for CPU OFF" function="test_psci_stats_cpu_off" />
+    <testcase name="Stats test cases after system suspend" function="test_psci_stats_system_suspend" />
+  </testsuite>
+
+  <testsuite name="PSCI NODE_HW_STATE" description="Test PSCI NODE_HW_STATE API">
+    <testcase name="Tests for NODE_HW_STATE" function="test_psci_node_hw_state" />
+    <testcase name="Tests for NODE_HW_STATE on multicluster" function="test_psci_node_hw_state_multi" />
+  </testsuite>
+
+  <testsuite name="PSCI Features" description="Check the PSCI features implemented">
+    <testcase name="PSCI Features" function="test_psci_features" />
+    <testcase name="PSCI Invalid Features" function="test_psci_features_invalid_id" />
+  </testsuite>
+
+  <testsuite name="PSCI MIGRATE_INFO_TYPE" description="Test MIGRATE_INFO_TYPE support">
+     <testcase name="PSCI MIGRATE_INFO_TYPE" function="test_migrate_info_type" />
+  </testsuite>
+
+  <testsuite name="PSCI mem_protect_check" description="Check the mem_protect_check_range feature">
+    <testcase name="PSCI mem_protect_check" function="test_mem_protect_check" />
+  </testsuite>
+
+  <testsuite name="PSCI System Suspend Validation" description="Validate PSCI System Suspend API">
+     <testcase name="System suspend multiple times" function="test_psci_sys_susp_multiple_iteration" />
+     <testcase name="system suspend from all cores" function="test_system_suspend_from_all_cores" />
+     <testcase name="System suspend with cores on" function="test_psci_sys_susp_with_cores_on" />
+     <testcase name="Suspend system with cores in suspend" function="test_psci_sys_susp_with_cores_in_suspend" />
+     <testcase name="Validate suspend to RAM functionality" function="test_psci_sys_susp_validate_ram" />
+     <testcase name="System suspend with invalid entrypoint address" function="test_system_suspend_invalid_entrypoint" />
+     <testcase name="System suspend with pending IRQ" function="test_psci_sys_susp_pending_irq" />
+  </testsuite>
+
+</testsuites>
diff --git a/tests/tests-runtime-instrumentation.xml b/tests/tests-runtime-instrumentation.xml
new file mode 100644
index 0000000..a96b816
--- /dev/null
+++ b/tests/tests-runtime-instrumentation.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+  Copyright (c) 2018, ARM Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+-->
+
+<testsuites>
+
+  <testsuite name="Runtime Instrumentation Validation" description="Validate PMF Runtime Instrumentation">
+     <testcase name="Suspend to deepest power level on all cores in parallel" function="test_rt_instr_susp_deep_parallel" />
+     <testcase name="Suspend to deepest power level on all cores in sequence" function="test_rt_instr_susp_deep_serial" />
+     <testcase name="CPU suspend on all cores in parallel" function="test_rt_instr_cpu_susp_parallel" />
+     <testcase name="CPU suspend on all cores in sequence" function="test_rt_instr_cpu_susp_serial" />
+     <testcase name="CPU off on all non-lead cores in sequence and suspend lead to deepest power level" function="test_rt_instr_cpu_off_serial" />
+     <testcase name="PSCI version call on all cores in parallel" function="test_rt_instr_psci_version_parallel" />
+  </testsuite>
+
+</testsuites>
diff --git a/tests/tests-sdei.xml b/tests/tests-sdei.xml
new file mode 100644
index 0000000..25266ff
--- /dev/null
+++ b/tests/tests-sdei.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+  Copyright (c) 2018, ARM Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+-->
+
+<testsuites>
+
+  <testsuite name="SDEI" description="SDEI test framework">
+     <testcase name="SDEI event handler state machine testing" function="test_sdei_state" />
+     <testcase name="SDEI event handling on all cores in sequence" function="test_sdei_event_serial" />
+     <testcase name="SDEI event handling on all cores in parallel" function="test_sdei_event_parallel" />
+     <testcase name="SDEI event signaling: each core signals itself" function="test_sdei_event_signal_serial" />
+     <testcase name="SDEI event signaling: one core signals all others" function="test_sdei_event_signal_all" />
+  </testsuite>
+
+</testsuites>
diff --git a/tests/tests-spm.xml b/tests/tests-spm.xml
new file mode 100644
index 0000000..137d8b4
--- /dev/null
+++ b/tests/tests-spm.xml
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+  Copyright (c) 2018, ARM Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+-->
+
+<testsuites>
+
+  <testsuite name="SPM" description="SPM test framework">
+     <testcase name="SPM NS interrupts test" function="test_secure_partition_interrupt_by_ns" />
+     <testcase name="SPM secondary CPUs sequential test" function="test_secure_partition_secondary_cores_seq" />
+     <testcase name="SPM secondary CPUs simultaneous test" function="test_secure_partition_secondary_cores_sim" />
+  </testsuite>
+
+</testsuites>
diff --git a/tests/tests-template.xml b/tests/tests-template.xml
new file mode 100644
index 0000000..7c6bb9c
--- /dev/null
+++ b/tests/tests-template.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+  Copyright (c) 2018, ARM Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+-->
+
+<testsuites>
+  <!--
+     The "template" testsuite aims at providing template test code as a
+     starting point for developing new tests. These tests don't do anything
+     useful in terms of testing.
+  -->
+  <testsuite name="Template" description="Template test code">
+     <testcase name="Single core test" function="test_template_single_core" />
+     <testcase name="Multi core test" function="test_template_multi_core" />
+  </testsuite>
+
+</testsuites>
diff --git a/tests/tests-tftf-validation.xml b/tests/tests-tftf-validation.xml
new file mode 100644
index 0000000..a27366c
--- /dev/null
+++ b/tests/tests-tftf-validation.xml
@@ -0,0 +1,32 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+  Copyright (c) 2018, ARM Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+-->
+
+<testsuites>
+
+  <testsuite name="Framework Validation" description="Validate the core features of the test framework">
+    <testcase name="NVM support" function="test_validation_nvm" />
+    <testcase name="NVM serialisation" function="test_validate_nvm_serialisation" />
+    <testcase name="Events API" function="test_validation_events" />
+    <testcase name="IRQ handling" function="test_validation_irq" />
+    <testcase name="SGI support" function="test_validation_sgi" />
+  </testsuite>
+
+  <testsuite name="Timer framework Validation" description="Validate the timer driver and timer framework">
+     <testcase name="Verify the timer interrupt generation" function="test_timer_framework_interrupt" />
+     <testcase name="Target timer to a power down cpu" function="test_timer_target_power_down_cpu" />
+     <testcase name="Test scenario where multiple CPUs call same timeout" function="test_timer_target_multiple_same_interval" />
+     <testcase name="Stress test the timer framework" function="stress_test_timer_framework" />
+  </testsuite>
+
+</testsuites>
diff --git a/tests/tests-tsp.xml b/tests/tests-tsp.xml
new file mode 100644
index 0000000..1dc65dc
--- /dev/null
+++ b/tests/tests-tsp.xml
@@ -0,0 +1,42 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+  Copyright (c) 2018, ARM Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+-->
+
+<testsuites>
+
+  <testsuite name="IRQ support in TSP" description="Test the normal IRQ preemption support in TSP.">
+    <testcase name="TSP preempt by IRQ and resume" function="tsp_int_and_resume" />
+    <testcase name="Fast SMC while TSP preempted" function="test_fast_smc_when_tsp_preempted" />
+    <testcase name="STD SMC resumption while TSP preempted" function="test_std_smc_when_tsp_preempted_resume" />
+    <testcase name="STD SMC abortion while TSP preempted" function="test_std_smc_when_tsp_preempted_abort" />
+    <testcase name="Resume SMC without TSP preemption" function="test_resume_smc_without_preemption" />
+    <testcase name="Stress TSP preemption and resumption" function="tsp_int_and_resume_stress" />
+    <testcase name="Test Secure FIQ while TSP is preempted" function="tsp_fiq_while_int" />
+    <testcase name="Resume preempted STD SMC" function="test_irq_preempted_std_smc" />
+    <testcase name="Resume preempted STD SMC from other CPUs" function="test_resume_preempted_std_smc_other_cpus" />
+    <testcase name="Resume STD SMC from different CPUs" function="test_resume_different_cpu_preempted_std_smc" />
+    <testcase name="Resume preempted STD SMC after PSCI CPU OFF/ON cycle" function="test_psci_cpu_on_off_preempted_std_smc" />
+    <!-- The following test fails on some FVP configs. See GENFW-2230 -->
+    <!-- <testcase name="Resume preempted STD SMC after PSCI CPU SUSPEND" function="test_psci_cpu_suspend_preempted_std_smc" /> -->
+    <testcase name="Resume preempted STD SMC after PSCI SYSTEM SUSPEND" function="test_psci_system_suspend_preempted_std_smc" />
+  </testsuite>
+
+  <testsuite name="TSP handler standard functions result test" description="Validate TSP SMC standard function call">
+     <testcase name="TestSecurePayload standard functions service call" function="test_smc_tsp_std_fns_call" />
+  </testsuite>
+
+  <testsuite name="Stress test TSP functionality" description="Validate TSP functionality">
+     <testcase name="Stress test TSP functionality" function="test_tsp_fast_smc_operations" />
+  </testsuite>
+
+</testsuites>