Aarch32: Add support to ARMv7

Add support to ARMv7 with handling ARMv7 IRQ stack
and replacing ARMv8 specific instructions.

Signed-off-by: Jun Nie <jun.nie@linaro.org>

9 files changed, 75 insertions, 1 deletions

diff --git a/Makefile b/Makefile
index aa4bf4d..6abb10c 100644
--- a/Makefile
+++ b/Makefile
@@ -210,18 +210,24 @@ endif
 ASFLAGS_aarch64		=	-mgeneral-regs-only
 TFTF_CFLAGS_aarch64	=	-mgeneral-regs-only
 
+ifeq (${ARM_ARCH_MAJOR},7)
+ASFLAGS_aarch32		=	-march=armv7-a
+TFTF_CFLAGS_aarch32	=	-march=armv7-a
+else
 ASFLAGS_aarch32		=	-march=armv8-a
 TFTF_CFLAGS_aarch32	=	-march=armv8-a
+endif
 
 ASFLAGS			+=	-nostdinc -ffreestanding -Wa,--fatal-warnings	\
 				-Werror -Wmissing-include-dirs			\
 				-D__ASSEMBLY__ $(ASFLAGS_$(ARCH))		\
+				-D ARM_ARCH_MAJOR=$(ARM_ARCH_MAJOR)		\
 				${DEFINES} ${INCLUDES}
 TFTF_CFLAGS		+=	-nostdinc -pedantic -ffreestanding -Wall\
 				-Werror -Wno-error=unused-function 		\
 				-Wmissing-include-dirs $(TFTF_CFLAGS_$(ARCH))	\
 				-std=c99 -c -Os ${DEFINES} ${INCLUDES}
-TFTF_CFLAGS		+=	-ffunction-sections -fdata-sections
+TFTF_CFLAGS		+=	-ffunction-sections -fdata-sections -D ARM_ARCH_MAJOR=$(ARM_ARCH_MAJOR)
 
 # Get the content of CFLAGS user defined value last so they are appended after
 # the options defined in the Makefile
diff --git a/framework/aarch32/asm_debug.S b/framework/aarch32/asm_debug.S
index ca9f9cb..4a373c5 100644
--- a/framework/aarch32/asm_debug.S
+++ b/framework/aarch32/asm_debug.S
@@ -89,6 +89,8 @@ func asm_assert
 	/* Print line number in decimal */
 	mov	r6, #10			/* Divide by 10 after every loop iteration */
 	ldr	r5, =MAX_DEC_DIVISOR
+	/* TODO: test whether udiv is supported, instead of using ARCH_MAJOR */
+#if ARM_ARCH_MAJOR == 8
 dec_print_loop:
 	udiv	r0, r4, r5			/* Quotient */
 	mls	r4, r0, r5, r4			/* Remainder */
@@ -97,6 +99,14 @@ dec_print_loop:
 	udiv	r5, r5, r6			/* Reduce divisor */
 	cmp	r5, #0
 	bne	dec_print_loop
+#else
+	mov	r0, #'0'
+	bl	plat_crash_console_putc
+	mov	r0, #'x'
+	bl	plat_crash_console_putc
+	mov	r4, r5
+	bl	asm_print_hex
+#endif
 
 	bl	plat_crash_console_flush
 
diff --git a/framework/aarch32/exceptions.S b/framework/aarch32/exceptions.S
index 5dbfa33..00353d7 100644
--- a/framework/aarch32/exceptions.S
+++ b/framework/aarch32/exceptions.S
@@ -50,7 +50,18 @@ vector_base tftf_vector
  */
 func tftf_intr_handle
 	push	{r0 - r3, lr}
+#if ARM_ARCH_MAJOR == 7
+	mrs	lr, spsr
+	push	{lr}
+#endif
 	bl	tftf_irq_handler_dispatcher
+#if ARM_ARCH_MAJOR == 8
 	pop	{r0 - r3, lr}
 	eret
+#else
+	pop	{lr}
+	msr	spsr_cxsf, lr
+	pop	{r0 - r3, lr}
+	subs	pc, lr, #4
+#endif
 endfunc tftf_intr_handle
diff --git a/framework/tftf.ld.S b/framework/tftf.ld.S
index cf97e83..58f4d28 100644
--- a/framework/tftf.ld.S
+++ b/framework/tftf.ld.S
@@ -72,6 +72,14 @@ SECTIONS
         __STACKS_END__ = .;
     } >RAM
 
+#if ARM_ARCH_MAJOR == 7
+    stacks (NOLOAD) : {
+        __IRQ_STACKS_START__ = .;
+        *(irq_stacks)
+        __IRQ_STACKS_END__ = .;
+    } >RAM
+#endif
+
     /*
      * The .bss section gets initialised to 0 at runtime.
      * Its base address must be 16-byte aligned.
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h
index d292537..3b36f1b 100644
--- a/include/lib/aarch32/arch.h
+++ b/include/lib/aarch32/arch.h
@@ -352,6 +352,13 @@
 	((endian) & SPSR_E_MASK) << SPSR_E_SHIFT |	\
 	((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
 
+#define SPSR_ARMV7(mode, aif)			\
+	(MODE_RW_32 << MODE_RW_SHIFT |			\
+	((mode) & MODE32_MASK) << MODE32_SHIFT |	\
+	((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
+
+#define SPSR_ARMV7_IRQ SPSR_ARMV7(MODE32_irq, SPSR_FIQ_BIT | SPSR_IRQ_BIT)
+
 /*******************************************************************************
  * Definitions of register offsets and fields in the CNTBaseN Frame of the
  * system level implementation of the Generic Timer.
diff --git a/lib/locks/aarch32/spinlock.S b/lib/locks/aarch32/spinlock.S
index 1bd052b..bcbfb3b 100644
--- a/lib/locks/aarch32/spinlock.S
+++ b/lib/locks/aarch32/spinlock.S
@@ -56,6 +56,10 @@ endfunc spin_lock
 
 func spin_unlock
 	mov	r1, #0
+#if ARM_ARCH_MAJOR == 8
 	stl	r1, [r0]
+#else
+	str	r1, [r0]
+#endif
 	bx	lr
 endfunc spin_unlock
diff --git a/lib/smc/aarch32/asm_smc.S b/lib/smc/aarch32/asm_smc.S
index 5795da3..9aa71a1 100644
--- a/lib/smc/aarch32/asm_smc.S
+++ b/lib/smc/aarch32/asm_smc.S
@@ -7,6 +7,7 @@
 #include <asm_macros.S>
 
 	.globl	asm_tftf_smc32
+	.arch_extension        sec
 
 /* ---------------------------------------------------------------------------
  * void asm_tftf_smc32(const smc_args *args,
diff --git a/plat/common/aarch32/platform_mp_stack.S b/plat/common/aarch32/platform_mp_stack.S
index 94ef15d..1532f6e 100644
--- a/plat/common/aarch32/platform_mp_stack.S
+++ b/plat/common/aarch32/platform_mp_stack.S
@@ -38,6 +38,7 @@
 	.weak	platform_set_stack
 	.weak	platform_get_stack
 	.weak	platform_set_coherent_stack
+	.weak	irq_set_stack
 
 	/* -----------------------------------------------------
 	 * void platform_set_coherent_stack (unsigned long mpidr)
@@ -79,6 +80,14 @@ func platform_set_stack
 	mov	r9, lr
 	get_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE
 	mov	sp, r0
+
+#if ARM_ARCH_MAJOR == 7
+	mrs	r2, cpsr
+	msr	cpsr, #SPSR_ARMV7_IRQ
+	get_mp_stack irq_stacks, IRQ_STACK_SIZE
+	mov	sp, r0
+	msr	cpsr, r2
+#endif
 	bx	r9
 endfunc platform_set_stack
 
@@ -92,6 +101,18 @@ endfunc platform_set_stack
 declare_stack platform_normal_stacks, tftf_normal_stacks, \
 		PLATFORM_STACK_SIZE, PLATFORM_CORE_COUNT
 
+#if ARM_ARCH_MAJOR == 7
+	/* -----------------------------------------------------
+	 * Per-cpu stacks in normal memory.
+	 * Used for C code during runtime execution (when coherent
+	 * stacks are not required).
+	 * Each cpu gets a stack of IRQ_STACK_SIZE bytes.
+	 * -----------------------------------------------------
+	 */
+declare_stack irq_stacks, tftf_normal_stacks, \
+		IRQ_STACK_SIZE, PLATFORM_CORE_COUNT
+#endif
+
 	/* -----------------------------------------------------
 	 * Per-cpu stacks in device memory.
 	 * Used for C code just before power down or right after
diff --git a/tests/runtime_services/standard_service/psci/api_tests/psci_features/test_psci_features.c b/tests/runtime_services/standard_service/psci/api_tests/psci_features/test_psci_features.c
index 10a4492..9302176 100644
--- a/tests/runtime_services/standard_service/psci/api_tests/psci_features/test_psci_features.c
+++ b/tests/runtime_services/standard_service/psci/api_tests/psci_features/test_psci_features.c
@@ -65,6 +65,12 @@ test_result_t test_psci_features(void)
 				psci_fn->str);
 		} else {
 			/* Check mandatory PSCI call is supported */
+#if ARM_ARCH_MAJOR == 7
+			if (psci_fn->id == SMC_PSCI_CPU_SUSPEND_AARCH64 ||
+			    psci_fn->id == SMC_PSCI_CPU_ON_AARCH64 ||
+			    psci_fn->id == SMC_PSCI_AFFINITY_INFO_AARCH64)
+				continue;
+#endif
 			if (ret_flag == PSCI_E_NOT_SUPPORTED) {
 				result = TEST_RESULT_FAIL;
 				tftf_testcase_printf(