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authorSandrine Bailleux <sandrine.bailleux@arm.com>2018-01-15 14:38:29 +0100
committerSandrine Bailleux <sandrine.bailleux@arm.com>2018-01-15 14:43:07 +0100
commitdb61705a2b60756e4821ba795f31b4a8c1429050 (patch)
treea0f8d65c43635c20927b77cbfb5ccb4979f93634
parent19e55470b449ad71b484ef21051acdbe2567b8be (diff)
Minor modifications around the system timer defs
This patch fixes and adds some comments around the system timer definitions. It also removes the definitions related to CNTNSAR and CNTACR, as they were not used in TFTF. Change-Id: Idffcb614c2125c0f8edd2a4359d66cb374de8a72 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
-rw-r--r--include/lib/aarch32/arch.h20
-rw-r--r--include/lib/aarch64/arch.h16
-rw-r--r--plat/arm/board/fvp/include/platform_def.h7
3 files changed, 14 insertions, 29 deletions
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h
index ea5e585..eb768e3 100644
--- a/include/lib/aarch32/arch.h
+++ b/include/lib/aarch32/arch.h
@@ -344,11 +344,14 @@
((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
/*******************************************************************************
- * Definitions of register offsets and fields in the CNTCTLBase Frame of the
+ * Definitions of register offsets and fields in the CNTBaseN Frame of the
* system level implementation of the Generic Timer.
******************************************************************************/
+/* Physical Count register. */
#define CNTPCT_LO 0x0
+/* Physical Timer CompareValue register. */
#define CNTP_CVAL_LO 0x20
+/* Physical Timer Control register. */
#define CNTP_CTL 0x2c
/* Physical timer control register bit fields shifts and masks */
@@ -373,21 +376,6 @@
#define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT))
#define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT))
-/*******************************************************************************
- * Definitions of register offsets and fields in the CNTCTLBase Frame of the
- * system level implementation of the Generic Timer.
- ******************************************************************************/
-#define CNTNSAR 0x4
-#define CNTNSAR_NS_SHIFT(x) (x)
-
-#define CNTACR_BASE(x) (0x40 + ((x) << 2))
-#define CNTACR_RPCT_SHIFT 0x0
-#define CNTACR_RVCT_SHIFT 0x1
-#define CNTACR_RFRQ_SHIFT 0x2
-#define CNTACR_RVOFF_SHIFT 0x3
-#define CNTACR_RWVT_SHIFT 0x4
-#define CNTACR_RWPT_SHIFT 0x5
-
/* MAIR macros */
#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << 3))
#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - 3) << 3))
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 83394fd..22c8a62 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -363,22 +363,14 @@
#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK
/*******************************************************************************
- * Definitions of register offsets and fields in the CNTCTLBase Frame of the
+ * Definitions of register offsets and fields in the CNTBaseN Frame of the
* system level implementation of the Generic Timer.
******************************************************************************/
+/* Physical Count register. */
#define CNTPCT_LO 0x0
+/* Physical Timer CompareValue register. */
#define CNTP_CVAL_LO 0x20
+/* Physical Timer Control register. */
#define CNTP_CTL 0x2c
-#define CNTNSAR 0x4
-#define CNTNSAR_NS_SHIFT(x) x
-
-#define CNTACR_BASE(x) (0x40 + (x << 2))
-#define CNTACR_RPCT_SHIFT 0x0
-#define CNTACR_RVCT_SHIFT 0x1
-#define CNTACR_RFRQ_SHIFT 0x2
-#define CNTACR_RVOFF_SHIFT 0x3
-#define CNTACR_RWVT_SHIFT 0x4
-#define CNTACR_RWPT_SHIFT 0x5
-
#endif /* __ARCH_H__ */
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index a0a58b7..842efd2 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -132,9 +132,13 @@
#define NS_BL2U_BASE DRAM_BASE
#define NS_BL2U_LIMIT (NS_BL2U_BASE + 0x4C000)
-/* Memory mapped Generic timer interfaces */
+/******************************************************************************
+ * Memory mapped Generic timer interfaces
+ ******************************************************************************/
+/* AP_REFCLK CNTBase1, Generic Timer. */
#define SYS_CNT_BASE1 0x2a830000
+
/* Size of a block as mapped by a second-level translation table */
#define L2_BLOCK_SIZE 0x200000
@@ -244,6 +248,7 @@
*/
#define PLAT_MAX_SPI_OFFSET_ID 107
+/* AP_REFCLK, Generic Timer, CNTPSIRQ1. */
#define IRQ_CNTPSIRQ1 58
/* Per-CPU Hypervisor Timer Interrupt ID */
#define IRQ_PCPU_HP_TIMER 26