AArch32: Add NS_BL1U and NS_BL2U support

Change-Id: Ice09a70a7543ffebbd2cf8c8bed8f96daa25c801
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

13 files changed, 381 insertions, 62 deletions

diff --git a/Makefile b/Makefile
index 776f7b0..b32b696 100644
--- a/Makefile
+++ b/Makefile
@@ -146,16 +146,6 @@ include framework/framework.mk
 include tests/tests.mk
 include ${PLAT_MAKEFILE_FULL}
 
-# Special handling for AArch32 builds
-ifeq (${ARCH},aarch32)
-  # Firmware update images (NS_BL1U and NS_BL2U) are not supported
-  # for AArch32.
-  ifeq (${FIRMWARE_UPDATE},1)
-    $(info Firmware Update images are not supported on AArch32)
-    $(info Forcing FIRMWARE_UPDATE to 0)
-    FIRMWARE_UPDATE := 0
-  endif
-endif
 
 .PHONY:			all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch
 .SUFFIXES:
diff --git a/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S b/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S
new file mode 100644
index 0000000..1a72189
--- /dev/null
+++ b/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <tftf.h>
+
+	.globl	ns_bl1u_entrypoint
+
+vector_base ns_bl1u_vector
+	b	ns_bl1u_entrypoint
+	b	.		/* Undef */
+	b	.		/* Syscall */
+	b	.		/* Prefetch abort */
+	b	.		/* Data abort */
+	b	.		/* Hyp trap */
+	b	.		/* IRQ */
+	b	.		/* FIQ */
+
+/* ----------------------------------------------------------------------------
+ * Cold boot entry point for the primary CPU.
+ * ----------------------------------------------------------------------------
+ */
+func ns_bl1u_entrypoint
+	/* --------------------------------------------------------------------
+	 * Set the exception vectors
+	 * --------------------------------------------------------------------
+	 */
+	ldr	r0, =ns_bl1u_vector
+	stcopr	r0, HVBAR
+
+	/* --------------------------------------------------------------------
+	 * Enable the instruction cache and asynchronous interrupts.
+	 * --------------------------------------------------------------------
+	 */
+	ldcopr	r0, HSCTLR
+	ldr	r1, =(HSCTLR_I_BIT | HSCTLR_A_BIT)
+	orr	r0, r0, r1
+	stcopr	r0, HSCTLR
+	isb
+
+	/* ---------------------------------------------
+	 * Init C runtime environment.
+	 *   - Zero-initialise the NOBITS sections.
+	 *       - the .bss section;
+	 *   - Copy the data section from NS_BL1U image
+	 *     (stored in ROM) to the correct location
+	 *     in RAM.
+	 * ---------------------------------------------
+	 */
+	ldr	r0, =__BSS_START__
+	ldr	r1, =__BSS_SIZE__
+	bl	zeromem
+
+	ldr	r0, =__DATA_RAM_START__
+	ldr	r1, =__DATA_ROM_START__
+	ldr	r2, =__DATA_SIZE__
+	bl	memcpy4
+
+	/* --------------------------------------------------------------------
+	 * Give ourselves a stack allocated in Normal -IS-WBWA memory
+	 * --------------------------------------------------------------------
+	 */
+	ldcopr	r0, MPIDR
+	bl	platform_set_stack
+
+	/* ---------------------------------------------
+	 * Perform early platform setup & platform
+	 * specific early arch. setup e.g. mmu setup
+	 * ---------------------------------------------
+	 */
+	bl	tftf_early_platform_setup
+	bl	tftf_plat_arch_setup
+
+	/* ---------------------------------------------
+	 * Jump to main function.
+	 * ---------------------------------------------
+	 */
+	bl	ns_bl1u_main
+dead:
+	b	dead
+endfunc ns_bl1u_entrypoint
diff --git a/fwu/ns_bl1u/ns_bl1u.mk b/fwu/ns_bl1u/ns_bl1u.mk
index 21d9904..674e1c5 100644
--- a/fwu/ns_bl1u/ns_bl1u.mk
+++ b/fwu/ns_bl1u/ns_bl1u.mk
@@ -30,24 +30,24 @@
 
 NS_BL1U_SOURCES	:=	drivers/io/io_fip.c				\
 			drivers/io/io_memmap.c				\
-			framework/aarch64/arch.c			\
-			framework/aarch64/exceptions.S			\
+			framework/${ARCH}/arch.c			\
+			framework/${ARCH}/exceptions.S			\
 			framework/debug.c				\
-			fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S	\
+			fwu/ns_bl1u/${ARCH}/ns_bl1u_entrypoint.S	\
 			fwu/ns_bl1u/ns_bl1u_main.c			\
-			lib/aarch64/cache_helpers.S			\
-			lib/aarch64/misc_helpers.S			\
-			lib/locks/aarch64/spinlock.S			\
-			lib/smc/aarch64/asm_smc.S			\
-			lib/smc/aarch64/smc.c				\
+			lib/${ARCH}/cache_helpers.S			\
+			lib/${ARCH}/misc_helpers.S			\
+			lib/locks/${ARCH}/spinlock.S			\
+			lib/smc/${ARCH}/asm_smc.S			\
+			lib/smc/${ARCH}/smc.c				\
 			${STD_LIB_SOURCES}				\
 			lib/utils/mp_printf.c				\
 			lib/utils/uuid.c				\
-			lib/xlat_tables/aarch64/xlat_tables.c		\
+			lib/xlat_tables/${ARCH}/xlat_tables.c		\
 			lib/xlat_tables/xlat_tables_common.c		\
 			plat/arm/common/arm_fwu_io_storage.c		\
-			plat/common/aarch64/platform_helpers.S		\
-			plat/common/aarch64/platform_up_stack.S 	\
+			plat/common/${ARCH}/platform_helpers.S		\
+			plat/common/${ARCH}/platform_up_stack.S 	\
 			plat/common/image_loader.c			\
 			plat/common/plat_common.c
 
diff --git a/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S b/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S
new file mode 100644
index 0000000..b770f41
--- /dev/null
+++ b/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <tftf.h>
+
+	.globl	ns_bl2u_entrypoint
+
+vector_base ns_bl2u_vector
+	b	ns_bl2u_entrypoint
+	b	.		/* Undef */
+	b	.		/* Syscall */
+	b	.		/* Prefetch abort */
+	b	.		/* Data abort */
+	b	.		/* Hyp trap */
+	b	.		/* IRQ */
+	b	.		/* FIQ */
+
+/* ----------------------------------------------------------------------------
+ * Cold boot entry point for the primary CPU.
+ * ----------------------------------------------------------------------------
+ */
+func ns_bl2u_entrypoint
+	/* --------------------------------------------------------------------
+	 * Set the exception vectors
+	 * --------------------------------------------------------------------
+	 */
+	ldr	r0, =ns_bl2u_vector
+	stcopr	r0, HVBAR
+
+	/* --------------------------------------------------------------------
+	 * Enable the instruction cache and asynchronous interrupts.
+	 * --------------------------------------------------------------------
+	 */
+	ldcopr	r0, HSCTLR
+	ldr	r1, =(HSCTLR_I_BIT | HSCTLR_A_BIT)
+	orr	r0, r0, r1
+	stcopr	r0, HSCTLR
+	isb
+
+	/* ---------------------------------------------
+	 *   - Zero-initialise the .bss section.
+	 * ---------------------------------------------
+	 */
+	ldr	r0, =__BSS_START__
+	ldr	r1, =__BSS_SIZE__
+	bl	zeromem
+
+	/* --------------------------------------------------------------------
+	 * Give ourselves a stack allocated in Normal -IS-WBWA memory
+	 * --------------------------------------------------------------------
+	 */
+	ldcopr	r0, MPIDR
+	bl	platform_set_stack
+
+	/* ---------------------------------------------
+	 * Perform early platform setup
+	 * ---------------------------------------------
+	 */
+	bl	tftf_early_platform_setup
+
+	/* ---------------------------------------------
+	 * Jump to main function.
+	 * ---------------------------------------------
+	 */
+	bl	ns_bl2u_main
+dead:
+	b	dead
+endfunc ns_bl2u_entrypoint
diff --git a/fwu/ns_bl2u/ns_bl2u.mk b/fwu/ns_bl2u/ns_bl2u.mk
index 18b14c5..2fec571 100644
--- a/fwu/ns_bl2u/ns_bl2u.mk
+++ b/fwu/ns_bl2u/ns_bl2u.mk
@@ -28,24 +28,24 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
-NS_BL2U_SOURCES	:=	framework/aarch64/arch.c			\
-			framework/aarch64/exceptions.S			\
+NS_BL2U_SOURCES	:=	framework/${ARCH}/arch.c			\
+			framework/${ARCH}/exceptions.S			\
 			framework/debug.c				\
-			fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S	\
+			fwu/ns_bl2u/${ARCH}/ns_bl2u_entrypoint.S	\
 			fwu/ns_bl2u/ns_bl2u_main.c			\
-			lib/aarch64/cache_helpers.S			\
-			lib/aarch64/misc_helpers.S			\
-			lib/locks/aarch64/spinlock.S			\
-			lib/smc/aarch64/asm_smc.S			\
-			lib/smc/aarch64/smc.c				\
+			lib/${ARCH}/cache_helpers.S			\
+			lib/${ARCH}/misc_helpers.S			\
+			lib/locks/${ARCH}/spinlock.S			\
+			lib/smc/${ARCH}/asm_smc.S			\
+			lib/smc/${ARCH}/smc.c				\
 			${STD_LIB_SOURCES}				\
 			lib/utils/mp_printf.c				\
 			lib/utils/uuid.c				\
-			lib/xlat_tables/aarch64/xlat_tables.c		\
+			lib/xlat_tables/${ARCH}/xlat_tables.c		\
 			lib/xlat_tables/xlat_tables_common.c		\
 			plat/arm/common/arm_fwu_io_storage.c		\
-			plat/common/aarch64/platform_helpers.S		\
-			plat/common/aarch64/platform_up_stack.S 	\
+			plat/common/${ARCH}/platform_helpers.S		\
+			plat/common/${ARCH}/platform_up_stack.S 	\
 			plat/common/fwu_nvm_accessors.c			\
 			plat/common/plat_common.c			\
 			drivers/io/io_memmap.c				\
diff --git a/include/common/aarch32/asm_macros.S b/include/common/aarch32/asm_macros.S
index ef321ae..5265e8a 100644
--- a/include/common/aarch32/asm_macros.S
+++ b/include/common/aarch32/asm_macros.S
@@ -91,5 +91,14 @@
 	mla r0, r0, r1, r2
 	.endm
 
+	/*
+	 * This macro calculates the base address of a uniprocessor(UP) stack
+	 * using the name of the stack storage and the size of the stack
+	 * Out: r0 = physical address of stack base
+	 */
+	.macro get_up_stack _name, _size
+	ldr	r0, =(\_name + \_size)
+	.endm
+
 #endif /* __ASM_MACROS_S__ */
 
diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h
index a5fd535..cedf0c3 100644
--- a/include/lib/aarch32/arch_helpers.h
+++ b/include/lib/aarch32/arch_helpers.h
@@ -314,4 +314,6 @@ static inline void disable_fiq(void)
 #define read_cntfrq_el0()	read_cntfrq()
 #define read_cntpct_el0()	read64_cntpct()
 
+void disable_mmu_icache(void);
+
 #endif /* __ARCH_HELPERS_H__ */
diff --git a/lib/aarch32/misc_helpers.S b/lib/aarch32/misc_helpers.S
index 63ac1a7..47f533f 100644
--- a/lib/aarch32/misc_helpers.S
+++ b/lib/aarch32/misc_helpers.S
@@ -33,6 +33,8 @@
 #include <assert_macros.S>
 
 	.globl	zeromem
+	.globl	memcpy4
+	.globl  disable_mmu_icache
 
 /* -----------------------------------------------------------------------
  * void zeromem(void *mem, unsigned int length);
@@ -58,3 +60,59 @@ z_loop:
 z_end:
 	bx	lr
 endfunc zeromem
+
+/* --------------------------------------------------------------------------
+ * void memcpy4(void *dest, const void *src, unsigned int length)
+ *
+ * Copy length bytes from memory area src to memory area dest.
+ * The memory areas should not overlap.
+ * Destination and source addresses must be 4-byte aligned.
+ * --------------------------------------------------------------------------
+ */
+func memcpy4
+#if ASM_ASSERTION
+	orr	r3, r0, r1
+	tst	r3, #0x3
+	ASM_ASSERT(eq)
+#endif
+/* copy 4 bytes at a time */
+m_loop4:
+	cmp	r2, #4
+	blt	m_loop1
+	ldr	r3, [r1], #4
+	str	r3, [r0], #4
+	sub	r2, r2, #4
+	b	m_loop4
+/* copy byte per byte */
+m_loop1:
+	cmp	r2,#0
+	beq	m_end
+	ldrb	r3, [r1], #1
+	strb	r3, [r0], #1
+	subs	r2, r2, #1
+	bne	m_loop1
+m_end:
+	bx	lr
+endfunc memcpy4
+
+/* ---------------------------------------------------------------------------
+ * Disable the MMU in Secure State
+ * ---------------------------------------------------------------------------
+ */
+
+func disable_mmu
+	mov	r1, #(HSCTLR_M_BIT | HSCTLR_C_BIT)
+do_disable_mmu:
+	ldcopr	r0, HSCTLR
+	bic	r0, r0, r1
+	stcopr	r0, HSCTLR
+	isb				// ensure MMU is off
+	dsb	sy
+	bx	lr
+endfunc disable_mmu
+
+
+func disable_mmu_icache
+	ldr	r1, =(HSCTLR_M_BIT | HSCTLR_C_BIT | HSCTLR_I_BIT)
+	b	do_disable_mmu
+endfunc disable_mmu_icache
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 217dd02..a318ac1 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -152,11 +152,9 @@
  ******************************************************************************/
 
 /* Size of cacheable stacks */
-#if IMAGE_NS_BL1U
-#define PLATFORM_STACK_SIZE	0x800
-#elif IMAGE_NS_BL2U
+#if IMAGE_NS_BL1U || IMAGE_NS_BL2U
 #define PLATFORM_STACK_SIZE	0x800
-#elif IMAGE_TFTF
+#else
 #define PLATFORM_STACK_SIZE	0xb80
 #endif
 
diff --git a/plat/arm/board/fvp/plat_setup.c b/plat/arm/board/fvp/plat_setup.c
index 7c3f674..14d1305 100644
--- a/plat/arm/board/fvp/plat_setup.c
+++ b/plat/arm/board/fvp/plat_setup.c
@@ -20,16 +20,7 @@
 #define CORE_PRESENT	1
 
 #if IMAGE_NS_BL2U
-/*
- * The next 2 constants identify the extents of the code, RO data region and the
- * limit of the NS_BL2U image.  These addresses are used by the MMU setup code and
- * therefore they must be page-aligned.  It is the responsibility of the linker
- * script to ensure that __RO_START__ & __RO_SIZE__ linker symbols are
- * page-aligned.
- */
-extern unsigned long __RO_START__;
 extern unsigned long __RO_SIZE__;
-#define NS_BL2U_RO_BASE 	(unsigned long)(&__RO_START__)
 #define NS_BL2U_RO_SIZE 	(unsigned long)(&__RO_SIZE__)
 #endif	/* IMAGE_NS_BL2U */
 
@@ -54,7 +45,7 @@ static const mmap_region_t mmap[] = {
 	{ DEVICE1_BASE,	DEVICE1_BASE, DEVICE1_SIZE,	MT_DEVICE | MT_RW | MT_NS },
 	{ FLASH_BASE, FLASH_BASE, FLASH_SIZE, MT_DEVICE | MT_RW | MT_NS },
 	{ DRAM_BASE, DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS },
-	{ NS_BL2U_RO_BASE, NS_BL2U_RO_BASE, NS_BL2U_RO_SIZE, MT_MEMORY | MT_RO | MT_NS },   /* Program text */
+	{ NS_BL2U_BASE, NS_BL2U_BASE, NS_BL2U_RO_SIZE, MT_MEMORY | MT_RO | MT_NS },   /* Program text */
 	{ 0 }
 };
 #elif IMAGE_TFTF
diff --git a/plat/arm/board/juno/plat_setup.c b/plat/arm/board/juno/plat_setup.c
index a26719d..f4c5612 100644
--- a/plat/arm/board/juno/plat_setup.c
+++ b/plat/arm/board/juno/plat_setup.c
@@ -18,16 +18,7 @@
 #include <platform.h>
 
 #if IMAGE_NS_BL2U
-/*
- * The next 2 constants identify the extents of the code, RO data region and the
- * limit of the NS_BL2U image.  These addresses are used by the MMU setup code and
- * therefore they must be page-aligned.  It is the responsibility of the linker
- * script to ensure that __RO_START__ & __RO_SIZE__ linker symbols are
- * page-aligned.
- */
-extern unsigned long __RO_START__;
 extern unsigned long __RO_SIZE__;
-#define NS_BL2U_RO_BASE	(unsigned long)(&__RO_START__)
 #define NS_BL2U_RO_SIZE	(unsigned long)(&__RO_SIZE__)
 #endif	/* IMAGE_NS_BL2U */
 
@@ -56,7 +47,7 @@ static const mmap_region_t mmap[] = {
 				MT_DEVICE | MT_RW | MT_NS },
 	{ FLASH_BASE, FLASH_BASE, FLASH_SIZE, MT_DEVICE | MT_RW | MT_NS },
 	{ DRAM_BASE, DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS },
-	{ NS_BL2U_RO_BASE, NS_BL2U_RO_BASE, NS_BL2U_RO_SIZE, MT_MEMORY | MT_RO | MT_NS },
+	{ NS_BL2U_BASE, NS_BL2U_BASE, NS_BL2U_RO_SIZE, MT_MEMORY | MT_RO | MT_NS },
 	{0}
 };
 #elif IMAGE_TFTF
diff --git a/plat/common/aarch32/platform_up_stack.S b/plat/common/aarch32/platform_up_stack.S
new file mode 100644
index 0000000..6165360
--- /dev/null
+++ b/plat/common/aarch32/platform_up_stack.S
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+
+	.local	platform_normal_stacks
+	.globl	platform_set_stack
+	.globl	platform_get_stack
+
+	/* -----------------------------------------------------
+	 * unsigned long platform_get_stack (unsigned long)
+	 *
+	 * For cold-boot BL images, only the primary CPU needs a
+	 * stack. This function returns the stack pointer for a
+	 * stack allocated in device memory.
+	 * -----------------------------------------------------
+	 */
+func platform_get_stack
+	get_up_stack platform_normal_stacks, PLATFORM_STACK_SIZE
+	bx	lr
+endfunc	platform_get_stack
+
+	/* -----------------------------------------------------
+	 * void platform_set_stack (unsigned long)
+	 *
+	 * For cold-boot BL images, only the primary CPU needs a
+	 * stack. This function sets the stack pointer to a stack
+	 * allocated in normal memory.
+	 * -----------------------------------------------------
+	 */
+func platform_set_stack
+	get_up_stack platform_normal_stacks, PLATFORM_STACK_SIZE
+	mov	sp, r0
+	bx	lr
+endfunc platform_set_stack
+
+	/* -----------------------------------------------------
+	 * Single cpu stack in normal memory.
+	 * Used for C code during boot, PLATFORM_STACK_SIZE bytes
+	 * are allocated
+	 * -----------------------------------------------------
+	 */
+declare_stack platform_normal_stacks, ns_bl_normal_stacks, \
+		PLATFORM_STACK_SIZE, 1
diff --git a/plat/common/image_loader.c b/plat/common/image_loader.c
index 02bd227..e486e0c 100644
--- a/plat/common/image_loader.c
+++ b/plat/common/image_loader.c
@@ -142,7 +142,7 @@ int load_image(unsigned int image_id, uintptr_t image_base)
 		return io_result;
 	}
 
-	INFO("Loading image id=%u at address 0x%lx\n", image_id, image_base);
+	INFO("Loading image id=%u at address %p\n", image_id, (void *)image_base);
 
 	/* Find the size of the image */
 	io_result = io_size(image_handle, &image_size);
@@ -165,8 +165,8 @@ int load_image(unsigned int image_id, uintptr_t image_base)
 	 */
 	flush_dcache_range(image_base, image_size);
 
-	INFO("Image id=%u loaded: 0x%lx - 0x%lx\n", image_id, image_base,
-	     image_base + image_size);
+	INFO("Image id=%u loaded: %p - %p\n", image_id, (void *)image_base,
+	     (void *)(image_base + image_size - 1));
 
 exit:
 	io_close(image_handle);
@@ -204,7 +204,7 @@ int load_partial_image(unsigned int image_id,
 		}
 	}
 
-	INFO("Loading image id=%u at address 0x%lx\n", image_id, image_base);
+	INFO("Loading image id=%u at address %p\n", image_id, (void *)image_base);
 
 	io_result = io_read(image_handle, image_base, image_size, &bytes_read);
 	if ((io_result != IO_SUCCESS) || (bytes_read < image_size)) {
@@ -219,8 +219,8 @@ int load_partial_image(unsigned int image_id,
 	 */
 	flush_dcache_range(image_base, image_size);
 
-	INFO("Image id=%u loaded: 0x%lx - 0x%lx\n", image_id, image_base,
-	     image_base + image_size);
+	INFO("Image id=%u loaded: %p - %p\n", image_id, (void *)image_base,
+	     (void *)(image_base + image_size - 1));
 
 exit: