Rework the GICv2 driver

This patch reworks the gic driver files for:

 - A consistent naming convention for functions
 - Removes accessors to functions which are not available in
   non-secure mode

Change-Id: I28b2e5d6f1a27cec2e1556a1f9935e081a5d6faf

2 files changed, 181 insertions, 274 deletions

diff --git a/drivers/arm/gic/gic_v2.c b/drivers/arm/gic/gic_v2.c
index 4b6ebbe..29d9bf3 100644
--- a/drivers/arm/gic/gic_v2.c
+++ b/drivers/arm/gic/gic_v2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -29,83 +29,83 @@
  */
 
 #include <arch.h>
+#include <arch_helpers.h>
 #include <assert.h>
 #include <gic_v2.h>
 #include <mmio.h>
+#include <platform.h>
+
+static uint64_t gicc_base_addr;
+static uint64_t gicd_base_addr;
+static uint64_t gicr_base_addr;
 
 /*******************************************************************************
  * GIC Distributor interface accessors for reading entire registers
  ******************************************************************************/
 
-unsigned int gicd_read_igroupr(unsigned int base, unsigned int id)
-{
-	unsigned n = id >> IGROUPR_SHIFT;
-	return mmio_read_32(base + GICD_IGROUPR + (n << 2));
-}
-
-unsigned int gicd_read_isenabler(unsigned int base, unsigned int id)
+unsigned int gicd_read_isenabler(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned n = id >> ISENABLER_SHIFT;
+	unsigned n = interrupt_id >> ISENABLER_SHIFT;
 	return mmio_read_32(base + GICD_ISENABLER + (n << 2));
 }
 
-unsigned int gicd_read_icenabler(unsigned int base, unsigned int id)
+unsigned int gicd_read_icenabler(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned n = id >> ICENABLER_SHIFT;
+	unsigned n = interrupt_id >> ICENABLER_SHIFT;
 	return mmio_read_32(base + GICD_ICENABLER + (n << 2));
 }
 
-unsigned int gicd_read_ispendr(unsigned int base, unsigned int id)
+unsigned int gicd_read_ispendr(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned n = id >> ISPENDR_SHIFT;
+	unsigned n = interrupt_id >> ISPENDR_SHIFT;
 	return mmio_read_32(base + GICD_ISPENDR + (n << 2));
 }
 
-unsigned int gicd_read_icpendr(unsigned int base, unsigned int id)
+unsigned int gicd_read_icpendr(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned n = id >> ICPENDR_SHIFT;
+	unsigned n = interrupt_id >> ICPENDR_SHIFT;
 	return mmio_read_32(base + GICD_ICPENDR + (n << 2));
 }
 
-unsigned int gicd_read_isactiver(unsigned int base, unsigned int id)
+unsigned int gicd_read_isactiver(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned n = id >> ISACTIVER_SHIFT;
+	unsigned n = interrupt_id >> ISACTIVER_SHIFT;
 	return mmio_read_32(base + GICD_ISACTIVER + (n << 2));
 }
 
-unsigned int gicd_read_icactiver(unsigned int base, unsigned int id)
+unsigned int gicd_read_icactiver(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned n = id >> ICACTIVER_SHIFT;
+	unsigned n = interrupt_id >> ICACTIVER_SHIFT;
 	return mmio_read_32(base + GICD_ICACTIVER + (n << 2));
 }
 
-unsigned int gicd_read_ipriorityr(unsigned int base, unsigned int id)
+unsigned int gicd_read_ipriorityr(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned n = id >> IPRIORITYR_SHIFT;
+	unsigned n = interrupt_id >> IPRIORITYR_SHIFT;
 	return mmio_read_32(base + GICD_IPRIORITYR + (n << 2));
 }
 
-unsigned int gicd_read_itargetsr(unsigned int base, unsigned int id)
+unsigned int gicd_read_itargetsr(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned n = id >> ITARGETSR_SHIFT;
+	unsigned n = interrupt_id >> ITARGETSR_SHIFT;
 	return mmio_read_32(base + GICD_ITARGETSR + (n << 2));
 }
 
-unsigned int gicd_read_icfgr(unsigned int base, unsigned int id)
+unsigned int gicd_read_icfgr(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned n = id >> ICFGR_SHIFT;
+	unsigned n = interrupt_id >> ICFGR_SHIFT;
 	return mmio_read_32(base + GICD_ICFGR + (n << 2));
 }
 
-unsigned int gicd_read_cpendsgir(unsigned int base, unsigned int id)
+unsigned int gicd_read_cpendsgir(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned n = id >> CPENDSGIR_SHIFT;
+	unsigned n = interrupt_id >> CPENDSGIR_SHIFT;
 	return mmio_read_32(base + GICD_CPENDSGIR + (n << 2));
 }
 
-unsigned int gicd_read_spendsgir(unsigned int base, unsigned int id)
+unsigned int gicd_read_spendsgir(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned n = id >> SPENDSGIR_SHIFT;
+	unsigned n = interrupt_id >> SPENDSGIR_SHIFT;
 	return mmio_read_32(base + GICD_SPENDSGIR + (n << 2));
 }
 
@@ -113,180 +113,246 @@ unsigned int gicd_read_spendsgir(unsigned int base, unsigned int id)
  * GIC Distributor interface accessors for writing entire registers
  ******************************************************************************/
 
-void gicd_write_igroupr(unsigned int base, unsigned int id, unsigned int val)
-{
-	unsigned n = id >> IGROUPR_SHIFT;
-	mmio_write_32(base + GICD_IGROUPR + (n << 2), val);
-}
-
-void gicd_write_isenabler(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_isenabler(unsigned int base,
+				unsigned int interrupt_id, unsigned int val)
 {
-	unsigned n = id >> ISENABLER_SHIFT;
+	unsigned n = interrupt_id >> ISENABLER_SHIFT;
 	mmio_write_32(base + GICD_ISENABLER + (n << 2), val);
 }
 
-void gicd_write_icenabler(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_icenabler(unsigned int base,
+				unsigned int interrupt_id, unsigned int val)
 {
-	unsigned n = id >> ICENABLER_SHIFT;
+	unsigned n = interrupt_id >> ICENABLER_SHIFT;
 	mmio_write_32(base + GICD_ICENABLER + (n << 2), val);
 }
 
-void gicd_write_ispendr(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_ispendr(unsigned int base,
+				unsigned int interrupt_id, unsigned int val)
 {
-	unsigned n = id >> ISPENDR_SHIFT;
+	unsigned n = interrupt_id >> ISPENDR_SHIFT;
 	mmio_write_32(base + GICD_ISPENDR + (n << 2), val);
 }
 
-void gicd_write_icpendr(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_icpendr(unsigned int base,
+				unsigned int interrupt_id, unsigned int val)
 {
-	unsigned n = id >> ICPENDR_SHIFT;
+	unsigned n = interrupt_id >> ICPENDR_SHIFT;
 	mmio_write_32(base + GICD_ICPENDR + (n << 2), val);
 }
 
-void gicd_write_isactiver(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_isactiver(unsigned int base,
+				unsigned int interrupt_id, unsigned int val)
 {
-	unsigned n = id >> ISACTIVER_SHIFT;
+	unsigned n = interrupt_id >> ISACTIVER_SHIFT;
 	mmio_write_32(base + GICD_ISACTIVER + (n << 2), val);
 }
 
-void gicd_write_icactiver(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_icactiver(unsigned int base,
+				unsigned int interrupt_id, unsigned int val)
 {
-	unsigned n = id >> ICACTIVER_SHIFT;
+	unsigned n = interrupt_id >> ICACTIVER_SHIFT;
 	mmio_write_32(base + GICD_ICACTIVER + (n << 2), val);
 }
 
-void gicd_write_ipriorityr(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_ipriorityr(unsigned int base,
+				unsigned int interrupt_id, unsigned int val)
 {
-	unsigned n = id >> IPRIORITYR_SHIFT;
+	unsigned n = interrupt_id >> IPRIORITYR_SHIFT;
 	mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val);
 }
 
-void gicd_write_itargetsr(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_itargetsr(unsigned int base,
+				unsigned int interrupt_id, unsigned int val)
 {
-	unsigned n = id >> ITARGETSR_SHIFT;
+	unsigned n = interrupt_id >> ITARGETSR_SHIFT;
 	mmio_write_32(base + GICD_ITARGETSR + (n << 2), val);
 }
 
-void gicd_write_icfgr(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_icfgr(unsigned int base,
+				unsigned int interrupt_id, unsigned int val)
 {
-	unsigned n = id >> ICFGR_SHIFT;
+	unsigned n = interrupt_id >> ICFGR_SHIFT;
 	mmio_write_32(base + GICD_ICFGR + (n << 2), val);
 }
 
-void gicd_write_cpendsgir(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_cpendsgir(unsigned int base,
+				unsigned int interrupt_id, unsigned int val)
 {
-	unsigned n = id >> CPENDSGIR_SHIFT;
+	unsigned n = interrupt_id >> CPENDSGIR_SHIFT;
 	mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val);
 }
 
-void gicd_write_spendsgir(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_spendsgir(unsigned int base,
+				unsigned int interrupt_id, unsigned int val)
 {
-	unsigned n = id >> SPENDSGIR_SHIFT;
+	unsigned n = interrupt_id >> SPENDSGIR_SHIFT;
 	mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val);
 }
 
 /*******************************************************************************
  * GIC Distributor interface accessors for individual interrupt manipulation
  ******************************************************************************/
-unsigned int gicd_get_igroupr(unsigned int base, unsigned int id)
+void gicd_set_isenabler(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
-	unsigned int reg_val = gicd_read_igroupr(base, id);
+	unsigned bit_num = interrupt_id & ((1 << ISENABLER_SHIFT) - 1);
 
-	return (reg_val >> bit_num) & 0x1;
+	gicd_write_isenabler(base, interrupt_id, (1 << bit_num));
 }
 
-void gicd_set_igroupr(unsigned int base, unsigned int id)
+void gicd_set_icenabler(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
-	unsigned int reg_val = gicd_read_igroupr(base, id);
+	unsigned bit_num = interrupt_id & ((1 << ICENABLER_SHIFT) - 1);
 
-	gicd_write_igroupr(base, id, reg_val | (1 << bit_num));
+	gicd_write_icenabler(base, interrupt_id, (1 << bit_num));
 }
 
-void gicd_clr_igroupr(unsigned int base, unsigned int id)
+void gicd_set_ispendr(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
-	unsigned int reg_val = gicd_read_igroupr(base, id);
+	unsigned bit_num = interrupt_id & ((1 << ISPENDR_SHIFT) - 1);
 
-	gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num));
+	gicd_write_ispendr(base, interrupt_id, (1 << bit_num));
 }
 
-void gicd_set_isenabler(unsigned int base, unsigned int id)
+void gicd_set_icpendr(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1);
+	unsigned bit_num = interrupt_id & ((1 << ICPENDR_SHIFT) - 1);
 
-	gicd_write_isenabler(base, id, (1 << bit_num));
+	gicd_write_icpendr(base, interrupt_id, (1 << bit_num));
 }
 
-void gicd_set_icenabler(unsigned int base, unsigned int id)
+void gicd_set_isactiver(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1);
+	unsigned bit_num = interrupt_id & ((1 << ISACTIVER_SHIFT) - 1);
 
-	gicd_write_icenabler(base, id, (1 << bit_num));
+	gicd_write_isactiver(base, interrupt_id, (1 << bit_num));
 }
 
-void gicd_set_ispendr(unsigned int base, unsigned int id)
+void gicd_set_icactiver(unsigned int base, unsigned int interrupt_id)
 {
-	unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1);
+	unsigned bit_num = interrupt_id & ((1 << ICACTIVER_SHIFT) - 1);
 
-	gicd_write_ispendr(base, id, (1 << bit_num));
+	gicd_write_icactiver(base, interrupt_id, (1 << bit_num));
 }
 
-void gicd_set_icpendr(unsigned int base, unsigned int id)
+void gicd_set_itargetsr(unsigned int base,
+			unsigned int interrupt_id, unsigned int iface)
 {
-	unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1);
+	unsigned byte_off = interrupt_id & ((1 << ITARGETSR_SHIFT) - 1);
+	unsigned int reg_val = gicd_read_itargetsr(base, interrupt_id);
 
-	gicd_write_icpendr(base, id, (1 << bit_num));
+	gicd_write_itargetsr(base, interrupt_id, reg_val |
+			     (1 << iface) << (byte_off << 3));
 }
+/*******************************************************************************
+ * Enable NS interrupts and disable legacy bypass and set the priority mask
+ * register to allow all interrupts to trickle in.
+ ******************************************************************************/
+void arm_gic_cpuif_setup(void)
+{
+	uint32_t gicc_ctlr;
+
+	assert(gicc_base_addr);
 
-void gicd_set_isactiver(unsigned int base, unsigned int id)
+	gicc_write_pmr(gicc_base_addr, GIC_PRI_MASK);
+
+	gicc_ctlr = GICC_CTLR_ENABLE | FIQ_BYP_DIS_GRP1
+					 | IRQ_BYP_DIS_GRP1;
+	gicc_write_ctlr(gicc_base_addr, gicc_ctlr);
+}
+
+/*******************************************************************************
+ * Place the cpu interface in a state where it can never make a cpu exit wfi as
+ * as result of an asserted interrupt. This is critical for powering down a cpu
+ ******************************************************************************/
+void arm_gic_cpuif_deactivate(void)
 {
-	unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
+	uint32_t gicc_ctlr;
+
+	assert(gicc_base_addr);
 
-	gicd_write_isactiver(base, id, (1 << bit_num));
+	/* Disable non-secure interrupts and disable their bypass */
+	gicc_ctlr = gicc_read_ctlr(gicc_base_addr);
+	gicc_ctlr &= ~GICC_CTLR_ENABLE;
+	gicc_ctlr |= FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
+	gicc_write_ctlr(gicc_base_addr, gicc_ctlr);
 }
 
-void gicd_set_icactiver(unsigned int base, unsigned int id)
+/*******************************************************************************
+ * Enables the forwarding of pending interrupts from Distributor to CPU
+ * interface.
+ ******************************************************************************/
+static void arm_gic_distif_setup(void)
 {
-	unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1);
+	uint32_t gicd_ctlr;
+
+	assert(gicd_base_addr);
 
-	gicd_write_icactiver(base, id, (1 << bit_num));
+	/* Enable the forwarding of interrupts to CPU interface */
+	gicd_ctlr = gicd_read_ctlr(gicd_base_addr);
+	gicd_ctlr |= GICD_CTLR_ENABLE;
+	gicd_write_ctlr(gicd_base_addr, gicd_ctlr);
 }
 
-/*
- * Make sure that the interrupt's group is set before expecting
- * this function to do its job correctly.
- */
-void gicd_set_ipriorityr(unsigned int base, unsigned int id, unsigned int pri)
-{
-	unsigned int reg = base + GICD_IPRIORITYR + (id & ~3);
-	unsigned int shift = (id & 3) << 3;
-	unsigned int reg_val = mmio_read_32(reg);
-
-	/*
-	 * Enforce ARM recommendation to manage priority values such
-	 * that group1 interrupts always have a lower priority than
-	 * group0 interrupts.
-	 * Note, lower numerical values are higher priorities so the comparison
-	 * checks below are reversed from what might be expected.
-	 */
-	assert(gicd_get_igroupr(base, id) == GRP1 ?
-		pri >= GIC_HIGHEST_NS_PRIORITY &&
-			pri <= GIC_LOWEST_NS_PRIORITY :
-		pri >= GIC_HIGHEST_SEC_PRIORITY &&
-			pri <= GIC_LOWEST_SEC_PRIORITY);
+/* Sets the priority of the interrupt */
+void arm_gicd_set_ipriorityr(unsigned int interrupt_id, unsigned int pri)
+{
+	uint32_t reg_val;
+	uint32_t shift = (interrupt_id & 3) << 3;
 
+	reg_val = gicd_read_ipriorityr(gicd_base_addr, interrupt_id);
 	reg_val &= ~(GIC_PRI_MASK << shift);
 	reg_val |= (pri & GIC_PRI_MASK) << shift;
-	mmio_write_32(reg, reg_val);
+	gicd_write_ipriorityr(gicd_base_addr, interrupt_id, reg_val);
 }
 
-void gicd_set_itargetsr(unsigned int base, unsigned int id, unsigned int iface)
+void arm_gicd_write_sgir(uint32_t sgir_val)
 {
-	unsigned byte_off = id & ((1 << ITARGETSR_SHIFT) - 1);
-	unsigned int reg_val = gicd_read_itargetsr(base, id);
+	assert(gicd_base_addr);
+	gicd_write_sgir(gicd_base_addr, sgir_val);
+}
 
-	gicd_write_itargetsr(base, id, reg_val |
-			     (1 << iface) << (byte_off << 3));
+void arm_gicd_set_itargetsr(unsigned int num, unsigned int linear_id)
+{
+	assert(gicd_base_addr);
+	gicd_set_itargetsr(gicd_base_addr, num, linear_id);
+}
+
+void arm_gicd_set_isenabler(unsigned int num)
+{
+	assert(gicd_base_addr);
+	gicd_set_isenabler(gicd_base_addr, num);
+}
+
+uint32_t arm_gicc_read_iar(void)
+{
+	assert(gicc_base_addr);
+	return gicc_read_iar(gicc_base_addr);
+}
+
+uint8_t arm_gicd_get_itargetsr(unsigned int interrupt_id)
+{
+	assert(gicd_base_addr);
+	return gicd_read_itargetsr(gicd_base_addr, interrupt_id);
+}
+
+void arm_gicc_write_eoir(uint32_t val)
+{
+	assert(gicc_base_addr);
+	gicc_write_eoir(gicc_base_addr, val);
+}
+
+void arm_gic_setup(void)
+{
+	arm_gic_cpuif_setup();
+	arm_gic_distif_setup();
+}
+
+void arm_gic_init(uint64_t gicc_base,
+		uint64_t gicd_base,
+		uint64_t gicr_base)
+{
+	gicc_base_addr = gicc_base;
+	gicd_base_addr = gicd_base;
+	gicr_base_addr = gicr_base;
 }
diff --git a/drivers/arm/gic/ns_gic_v2.c b/drivers/arm/gic/ns_gic_v2.c
deleted file mode 100644
index 0091c22..0000000
--- a/drivers/arm/gic/ns_gic_v2.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <assert.h>
-#include <gic_v2.h>
-#include <pl011.h>
-#include <platform.h>
-#include <string.h>
-
-static uint64_t gicc_base_addr;
-static uint64_t gicd_base_addr;
-static uint64_t gicr_base_addr;
-
-/*******************************************************************************
- * Enable NS interrupts and disable legacy bypass and set the priority mask
- * register to allow all interrupts to trickle in.
- ******************************************************************************/
-void ns_gic_cpuif_setup(void)
-{
-	uint32_t gicc_ctlr;
-
-	assert(gicc_base_addr);
-
-	gicc_write_pmr(gicc_base_addr, GIC_PRI_MASK);
-
-	gicc_ctlr = NS_ENABLE_GRP1 | NS_FIQ_BYP_DIS_GRP1 | NS_IRQ_BYP_DIS_GRP1;
-	gicc_write_ctlr(gicc_base_addr, gicc_ctlr);
-}
-
-/*******************************************************************************
- * Place the cpu interface in a state where it can never make a cpu exit wfi as
- * as result of an asserted interrupt. This is critical for powering down a cpu
- ******************************************************************************/
-void ns_gic_cpuif_deactivate(void)
-{
-	uint32_t gicc_ctlr;
-
-	assert(gicc_base_addr);
-
-	/* Disable non-secure interrupts and disable their bypass */
-	gicc_ctlr = gicc_read_ctlr(gicc_base_addr);
-	gicc_ctlr &= ~NS_ENABLE_GRP1;
-	gicc_ctlr |= NS_FIQ_BYP_DIS_GRP1 | NS_IRQ_BYP_DIS_GRP1;
-	gicc_write_ctlr(gicc_base_addr, gicc_ctlr);
-}
-
-/*******************************************************************************
- * Global gic distributor setup which will be done by the primary cpu after a
- * cold boot. It marks out the NS SPIs, PPIs & SGIs and enables them. It
- * then enables the NS GIC distributor interface.
- ******************************************************************************/
-static void ns_gic_distif_setup(void)
-{
-	uint32_t gicd_ctlr;
-
-	assert(gicd_base_addr);
-
-	/* Enable the distributor */
-	gicd_ctlr = gicd_read_ctlr(gicd_base_addr);
-	gicd_ctlr |= NS_ENABLE_GRP1;
-	gicd_write_ctlr(gicd_base_addr, gicd_ctlr);
-}
-
-/*
- * The only difference between this function and gicd_set_ipriorityr()
- * is the absence of the assertion. Non-secure software can only configure
- * non-secure interrupts, and the GICD IGROUP register reads as 0 in normal
- * world.
- */
-void arm_gicd_set_ns_ipriorityr(unsigned int id, unsigned int pri)
-{
-	uint64_t reg = gicd_base_addr + GICD_IPRIORITYR + (id & ~3);
-	uint32_t shift = (id & 3) << 3;
-	uint32_t reg_val = mmio_read_32(reg);
-
-	reg_val &= ~(GIC_PRI_MASK << shift);
-	reg_val |= (pri & GIC_PRI_MASK) << shift;
-	mmio_write_32(reg, reg_val);
-}
-
-void arm_gicd_write_sgir(uint32_t sgir_val)
-{
-	assert(gicd_base_addr);
-	gicd_write_sgir(gicd_base_addr, sgir_val);
-}
-
-void arm_gicd_set_itargetsr(unsigned int num, unsigned int linear_id)
-{
-	assert(gicd_base_addr);
-	gicd_set_itargetsr(gicd_base_addr, num, linear_id);
-}
-
-void arm_gicd_set_isenabler(unsigned int num)
-{
-	assert(gicd_base_addr);
-	gicd_set_isenabler(gicd_base_addr, num);
-}
-
-uint32_t arm_gicc_read_IAR(void)
-{
-	assert(gicc_base_addr);
-	return gicc_read_IAR(gicc_base_addr);
-}
-
-uint8_t arm_gicd_get_itargetsr(unsigned int id)
-{
-	assert(gicd_base_addr);
-	return gicd_read_itargetsr(gicd_base_addr, id);
-}
-
-void arm_gicc_write_EOIR(uint32_t val)
-{
-	assert(gicc_base_addr);
-	gicc_write_EOIR(gicc_base_addr, val);
-}
-
-void ns_gic_setup(void)
-{
-	ns_gic_cpuif_setup();
-	ns_gic_distif_setup();
-}
-
-void ns_gic_init(uint64_t gicc_base,
-		uint64_t gicd_base,
-		uint64_t gicr_base)
-{
-	gicc_base_addr = gicc_base;
-	gicd_base_addr = gicd_base;
-	gicr_base_addr = gicr_base;
-}