Implement new timer framework in TFTF

This patch introduces a new timer framework which implements the
following:
    1. Allow the platform to select any timer peripheral for use
       by the timer framework
    2. Removes dependency on primary core as the only one which
       handles SGIs.
    3. Each core can request a timer event for a delay specified
       in milliseconds.

The new framework breaks down the time into slices of `TIMER_STEP_VALUE`
which is specified by the platform. All the requests within a time slice
are grouped into one and they have a single time keeper CPU which
receives the timer interrupt. The time keeper CPU will send IRQ_WAKE_SGI's
to other CPU's which requested a timer event in the time slice. This
framework will simplify the writing of power management test cases as
the test cases will no longer need to keep track of the status of all
the cores.

Also, it removes the verbose printf in `tftf_send_sgi` to avoid deadlock
scenario. The deadlock scenario arises if a CPU has acquired `printf_lock`
and before releasing it a timer interrupt fires to it and timer handler
calls tftf_send_sgi to wake other CPU's.

Change-Id: Iddda2595e8029b992e3470fcd1c5c15c8185177d

1 files changed, 116 insertions, 0 deletions

diff --git a/drivers/arm/timer/system_timer.c b/drivers/arm/timer/system_timer.c
new file mode 100644
index 0000000..cded10e
--- /dev/null
+++ b/drivers/arm/timer/system_timer.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <arm_gic.h>
+#include <assert.h>
+#include <debug.h>
+#include <gic_v2.h>
+#include <irq.h>
+#include <mmio.h>
+#include <system_timer.h>
+
+static uintptr_t g_systimer_base;
+
+int program_systimer(unsigned long time_out_ms)
+{
+	unsigned int cntp_ctl;
+	unsigned long long count_val;
+	unsigned int freq;
+
+	/* Check timer base is initialised */
+	assert(g_systimer_base);
+
+	count_val = mmio_read_64(g_systimer_base + CNTPCT_LO);
+	freq = read_cntfrq_el0();
+	count_val += (freq * time_out_ms) / 1000;
+	mmio_write_64(g_systimer_base + CNTP_CVAL_LO, count_val);
+
+	/* Enable the timer */
+	cntp_ctl = mmio_read_32(g_systimer_base + CNTP_CTL);
+	set_cntp_ctl_enable(cntp_ctl);
+	clr_cntp_ctl_imask(cntp_ctl);
+	mmio_write_32(g_systimer_base + CNTP_CTL, cntp_ctl);
+
+	/*
+	 * Ensure that we have programmed a timer interrupt for a time in
+	 * future. Else we will have to wait for the systimer to rollover
+	 * for the interrupt to fire (which is 64 years).
+	 */
+	if (count_val < mmio_read_64(g_systimer_base + CNTPCT_LO))
+		panic();
+
+	VERBOSE("%s : interrupt requested at sys_counter: %lld "
+		"time_out_ms: %ld\n", __func__, count_val, time_out_ms);
+
+	return 0;
+}
+
+static void disable_systimer(void)
+{
+	uint32_t val;
+
+	/* Check timer base is initialised */
+	assert(g_systimer_base);
+
+	/* Deassert and disable the timer interrupt */
+	val = 0;
+	set_cntp_ctl_imask(val);
+	mmio_write_32(g_systimer_base + CNTP_CTL, val);
+}
+
+int cancel_systimer(void)
+{
+	disable_systimer();
+	return 0;
+}
+
+int handler_systimer(void)
+{
+	disable_systimer();
+	return 0;
+}
+
+int init_systimer(uintptr_t systimer_base)
+{
+	/* Check timer base is not initialised */
+	assert(!g_systimer_base);
+
+	g_systimer_base = systimer_base;
+
+	/* Disable the timer as the reset value is unknown */
+	disable_systimer();
+
+	/* Initialise CVAL to zero */
+	mmio_write_64(g_systimer_base + CNTP_CVAL_LO, 0);
+
+	return 0;
+}