Introduce the ARM GIC layer and refactor GICv2 driver

The TFTF assumed that the GIC driver architecture is v2.0 and made
inherent assumptions about the same in the framework. In order to
add support for GICv3 systems, this assumption needs to be removed
and a new ARM GIC layer is introduced which abstracts the GIC
Architecture details. The `arm_gic.c` and `arm_gic.h` contain the
prototypes and definitions for this new layer. Also the GICv2
driver is refactored such that all the functionality is contained
within the driver and the driver is accessed through well defined
API. This essentially means that the GICv2 specific functionality
present earlier in the interrupt framework and SGI framework is
now removed.

Also certain functionality of GICv2 like clearing the
interrupt target register (GICD_ITARGETSR) to leave an interrupt
untargeted cannot be supported generically in GICv3 and hence it is
removed. The timer framework, which made use of this feature, is
modified to not use it anymore.

All the framework and testcases are modified to use the ARM GIC
layer rather than the GICv2 driver directly. The functionality
common across GICv3 and GICv2 drivers are defined in gic_common.c.

Change-Id: Idf50fa14be42cb4dfb507087e340b0404e681e98

5 files changed, 342 insertions, 130 deletions

diff --git a/include/drivers/arm/arm_gic.h b/include/drivers/arm/arm_gic.h
index d82a6c0..e4930dc 100644
--- a/include/drivers/arm/arm_gic.h
+++ b/include/drivers/arm/arm_gic.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -33,21 +33,111 @@
 
 #include <stdint.h>
 
-void arm_gic_setup(void);
-void arm_gic_cpuif_setup(void);
-void arm_gic_cpuif_deactivate(void);
-void arm_gic_cpuif_enable_interrupts(void);
-void arm_gicd_write_sgir(uint32_t sgir_val);
-void arm_gicd_set_itargetsr(unsigned int num, unsigned int linear_id);
-void arm_gicd_clear_itargetsr(unsigned int num, unsigned int linear_id);
-void arm_gicd_set_ipriorityr(unsigned int num, uint8_t priority);
-void arm_gicd_set_isenabler(unsigned int num);
-void arm_gicd_set_icenabler(unsigned int num);
-uint32_t arm_gicc_read_iar(void);
-void arm_gicc_write_eoir(uint32_t val);
-uint8_t arm_gicd_get_itargetsr(unsigned int id);
-uint32_t arm_gicd_ispend_irq(unsigned int interrupt_id);
-void arm_gicd_set_icpendr(unsigned int interrupt_id);
+/***************************************************************************
+ * Defines and prototypes for ARM GIC driver.
+ **************************************************************************/
+#define MAX_SGIS		16
+#define MIN_SGI_ID		0
+#define MAX_SGI_ID		15
+#define MIN_PPI_ID		16
+#define MAX_PPI_ID		31
+#define MIN_SPI_ID		32
+#define MAX_SPI_ID		1020
 
+#define IS_SGI(irq_num)							\
+	(((irq_num) >= MIN_SGI_ID) && ((irq_num) <= MAX_SGI_ID))
+
+#define IS_PPI(irq_num)							\
+	(((irq_num) >= MIN_PPI_ID) && ((irq_num) <= MAX_PPI_ID))
+
+#define IS_SPI(irq_num)							\
+	(((irq_num) >= MIN_SPI_ID) && ((irq_num) <= MAX_SPI_ID))
+
+#define IS_VALID_INTR_ID(irq_num)					\
+	(((irq_num) >= MIN_SGI_ID) && ((irq_num) <= MAX_SPI_ID))
+
+#define GIC_HIGHEST_NS_PRIORITY	0
+#define GIC_LOWEST_NS_PRIORITY	254 /* 255 would disable an interrupt */
+#define GIC_SPURIOUS_INTERRUPT	1023
+
+/******************************************************************************
+ * Setup the global GIC interface. In case of GICv2, it would be the GIC
+ * Distributor and in case of GICv3 it would be GIC Distributor and
+ * Re-distributor.
+ *****************************************************************************/
+void arm_gic_setup_global(void);
+
+/******************************************************************************
+ * Setup the GIC interface local to the CPU
+ *****************************************************************************/
+void arm_gic_setup_local(void);
+
+/******************************************************************************
+ * Disable interrupts for this local CPU
+ *****************************************************************************/
+void arm_gic_disable_interrupts_local(void);
+
+/******************************************************************************
+ * Enable interrupts for this local CPU
+ *****************************************************************************/
+void arm_gic_enable_interrupts_local(void);
+
+/******************************************************************************
+ * Send SGI with ID `sgi_id` to a core with index `core_pos`.
+ *****************************************************************************/
+void arm_gic_send_sgi(unsigned int sgi_id, unsigned int core_pos);
+
+/******************************************************************************
+ * Set the interrupt target of interrupt ID `num` to a core with index
+ * `core_pos`
+ *****************************************************************************/
+void arm_gic_set_intr_target(unsigned int num, unsigned int core_pos);
+
+/******************************************************************************
+ * Set the priority of the interrupt ID `num` to `priority`.
+ *****************************************************************************/
+void arm_gic_set_intr_priority(unsigned int num, unsigned int priority);
+
+/******************************************************************************
+ * Enable the interrupt ID `num`
+ *****************************************************************************/
+void arm_gic_intr_enable(unsigned int num);
+
+/******************************************************************************
+ * Disable the interrupt ID `num`
+ *****************************************************************************/
+void arm_gic_intr_disable(unsigned int num);
+
+/******************************************************************************
+ * Acknowledge the highest pending interrupt. Return the interrupt ID of the
+ * acknowledged interrupt. The raw interrupt acknowledge register value will
+ * be populated in `raw_iar`.
+ *****************************************************************************/
+unsigned int arm_gic_intr_ack(unsigned int *raw_iar);
+
+/******************************************************************************
+ * Signal the end of interrupt processing of a interrupt. The raw interrupt
+ * acknowledge register value returned by arm_gic_intr_ack() should be passed
+ * as argument to this function.
+ *****************************************************************************/
+void arm_gic_end_of_intr(unsigned int raw_iar);
+
+/******************************************************************************
+ * Check if the interrupt with ID `num` is pending at the GIC. Returns 1 if
+ * interrupt is pending else returns 0.
+ *****************************************************************************/
+unsigned int arm_gic_is_intr_pending(unsigned int num);
+
+/******************************************************************************
+ * Clear the pending status of the interrupt with ID `num` at the GIC.
+ *****************************************************************************/
+void arm_gic_intr_clear(unsigned int num);
+
+/******************************************************************************
+ * Initialize the GIC Driver. This function will detect the GIC Architecture
+ * present on the system and initialize the appropriate driver. The
+ * `gicr_base` argument will be ignored on GICv2 systems.
+ *****************************************************************************/
+void arm_gic_init(uintptr_t gicc_base, uintptr_t gicd_base, uintptr_t gicr_base);
 
 #endif /* __ARM_GIC_H__ */
diff --git a/include/drivers/arm/gic_common.h b/include/drivers/arm/gic_common.h
new file mode 100644
index 0000000..c894424
--- /dev/null
+++ b/include/drivers/arm/gic_common.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __GIC_COMMON_H__
+#define __GIC_COMMON_H__
+
+/***************************************************************************
+ * Defines and prototypes common to GIC v2 and v3 drivers.
+ **************************************************************************/
+/* Distributor interface register offsets */
+#define GICD_CTLR		0x0
+#define GICD_TYPER		0x4
+#define GICD_ISENABLER		0x100
+#define GICD_ICENABLER		0x180
+#define GICD_ISPENDR		0x200
+#define GICD_ICPENDR		0x280
+#define GICD_ISACTIVER		0x300
+#define GICD_ICACTIVER		0x380
+#define GICD_IPRIORITYR		0x400
+#define GICD_ICFGR		0xC00
+
+/* Distributor interface register shifts */
+#define ISENABLER_SHIFT		5
+#define ICENABLER_SHIFT		ISENABLER_SHIFT
+#define ISPENDR_SHIFT		5
+#define ICPENDR_SHIFT		ISPENDR_SHIFT
+#define ISACTIVER_SHIFT		5
+#define ICACTIVER_SHIFT		ISACTIVER_SHIFT
+#define IPRIORITYR_SHIFT	2
+#define ICFGR_SHIFT		4
+
+/* GICD_TYPER bit definitions */
+#define IT_LINES_NO_MASK	0x1f
+
+/* GICD Priority register mask */
+#define GIC_PRI_MASK		0xff
+
+#ifndef __ASSEMBLY__
+
+#include <mmio.h>
+
+/*******************************************************************************
+ * Private GIC Distributor function prototypes for use by GIC drivers
+ ******************************************************************************/
+unsigned int gicd_read_isenabler(unsigned int base, unsigned int interrupt_id);
+unsigned int gicd_read_icenabler(unsigned int base, unsigned int interrupt_id);
+unsigned int gicd_read_ispendr(unsigned int base, unsigned int interrupt_id);
+unsigned int gicd_read_icpendr(unsigned int base, unsigned int interrupt_id);
+unsigned int gicd_read_isactiver(unsigned int base, unsigned int interrupt_id);
+unsigned int gicd_read_icactiver(unsigned int base, unsigned int interrupt_id);
+unsigned int gicd_read_ipriorityr(unsigned int base, unsigned int interrupt_id);
+unsigned int gicd_read_icfgr(unsigned int base, unsigned int interrupt_id);
+void gicd_write_isenabler(unsigned int base, unsigned int interrupt_id,
+					unsigned int val);
+void gicd_write_icenabler(unsigned int base, unsigned int interrupt_id,
+					unsigned int val);
+void gicd_write_ispendr(unsigned int base, unsigned int interrupt_id,
+					unsigned int val);
+void gicd_write_icpendr(unsigned int base, unsigned int interrupt_id,
+					unsigned int val);
+void gicd_write_isactiver(unsigned int base, unsigned int interrupt_id,
+					unsigned int val);
+void gicd_write_icactiver(unsigned int base, unsigned int interrupt_id,
+					unsigned int val);
+void gicd_write_ipriorityr(unsigned int base, unsigned int interrupt_id,
+					unsigned int val);
+void gicd_write_icfgr(unsigned int base, unsigned int interrupt_id,
+					unsigned int val);
+void gicd_set_isenabler(unsigned int base, unsigned int interrupt_id);
+void gicd_set_icenabler(unsigned int base, unsigned int interrupt_id);
+void gicd_set_ispendr(unsigned int base, unsigned int interrupt_id);
+void gicd_set_icpendr(unsigned int base, unsigned int interrupt_id);
+void gicd_set_isactiver(unsigned int base, unsigned int interrupt_id);
+void gicd_set_icactiver(unsigned int base, unsigned int interrupt_id);
+void gicd_set_ipriorityr(unsigned int base, unsigned int interrupt_id,
+					unsigned int priority);
+
+/*******************************************************************************
+ * Private GIC Distributor interface accessors for reading and writing
+ * entire registers
+ ******************************************************************************/
+static inline unsigned int gicd_read_ctlr(unsigned int base)
+{
+	return mmio_read_32(base + GICD_CTLR);
+}
+
+static inline unsigned int gicd_read_typer(unsigned int base)
+{
+	return mmio_read_32(base + GICD_TYPER);
+}
+
+static inline void gicd_write_ctlr(unsigned int base, unsigned int val)
+{
+	mmio_write_32(base + GICD_CTLR, val);
+}
+
+
+#endif /*__ASSEMBLY__*/
+#endif /* __GIC_COMMON_H__ */
diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h
index e375566..271538f 100644
--- a/include/drivers/arm/gic_v2.h
+++ b/include/drivers/arm/gic_v2.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -31,58 +31,29 @@
 #ifndef __GIC_V2_H__
 #define __GIC_V2_H__
 
-#define GIC400_NUM_SPIS		480
-#define MAX_PPIS		14
-#define MAX_SGIS		16
-#define GIC_MAX_CPU_INTERFACES	8
-
-#define MIN_SGI_ID		0
-#define MAX_SGI_ID		15
-#define MIN_PPI_ID		16
-#define MAX_PPI_ID		31
-#define MIN_SPI_ID		32
-
-#define GIC_PRI_MASK		0xff
-#define GIC_HIGHEST_NS_PRIORITY	0
-#define GIC_LOWEST_NS_PRIORITY	254 /* 255 would disable an interrupt */
-#define GIC_SPURIOUS_INTERRUPT	1023
-
-/* Distributor interface definitions */
-#define GICD_CTLR		0x0
-#define GICD_TYPER		0x4
-#define GICD_ISENABLER		0x100
-#define GICD_ICENABLER		0x180
-#define GICD_ISPENDR		0x200
-#define GICD_ICPENDR		0x280
-#define GICD_ISACTIVER		0x300
-#define GICD_ICACTIVER		0x380
-#define GICD_IPRIORITYR		0x400
+/***************************************************************************
+ * Defines and prototypes specific to GIC v2.
+ **************************************************************************/
+
+/* GICD_CTLR bit definitions */
+#define GICD_CTLR_ENABLE	(1 << 0)
+
+/* Distributor interface register offsets */
 #define GICD_ITARGETSR		0x800
-#define GICD_ICFGR		0xC00
 #define GICD_SGIR		0xF00
 #define GICD_CPENDSGIR		0xF10
 #define GICD_SPENDSGIR		0xF20
 
-/* GICD_CTLR bit definitions */
-#define GICD_CTLR_ENABLE	(1 << 0)
-
-#define ISENABLER_SHIFT		5
-#define ICENABLER_SHIFT		ISENABLER_SHIFT
-#define ISPENDR_SHIFT		5
-#define PEND_IRQS_PER_REG	32
-#define ICPENDR_SHIFT		ISPENDR_SHIFT
-#define ISACTIVER_SHIFT		5
-#define ICACTIVER_SHIFT		ISACTIVER_SHIFT
-#define IPRIORITYR_SHIFT	2
+/* GIC Distributor register shifts */
 #define ITARGETSR_SHIFT		2
-#define ICFGR_SHIFT		4
 #define CPENDSGIR_SHIFT		2
 #define SPENDSGIR_SHIFT		CPENDSGIR_SHIFT
 
-/* GICD_TYPER bit definitions */
-#define IT_LINES_NO_MASK	0x1f
+/* GICD_SGIR bit shifts */
+#define GICD_SGIR_INTID_SHIFT		0
+#define GICD_SGIR_CPUTL_SHIFT		16
 
-/* Physical CPU Interface registers */
+/* Physical CPU Interface register offsets */
 #define GICC_CTLR		0x0
 #define GICC_PMR		0x4
 #define GICC_BPR		0x8
@@ -93,7 +64,7 @@
 #define GICC_AHPPIR		0x28
 #define GICC_IIDR		0xFC
 #define GICC_DIR		0x1000
-#define GICC_PRIODROP           GICC_EOIR
+#define GICC_PRIODROP		GICC_EOIR
 
 /* GICC_IIDR bit masks and shifts */
 #define GICC_IIDR_PID_SHIFT	20
@@ -106,7 +77,7 @@
 #define GICC_IIDR_REV_MASK	0xf
 #define GICC_IIDR_IMP_MASK	0xfff
 
-/* HYP view virtual CPU Interface registers */
+/* HYP view virtual CPU Interface register offsets */
 #define GICH_CTL		0x0
 #define GICH_VTR		0x4
 #define GICH_ELRSR0		0x30
@@ -114,7 +85,7 @@
 #define GICH_APR0		0xF0
 #define GICH_LR_BASE		0x100
 
-/* Virtual CPU Interface registers */
+/* Virtual CPU Interface register offsets */
 #define GICV_CTL		0x0
 #define GICV_PRIMASK		0x4
 #define GICV_BP			0x8
@@ -124,10 +95,6 @@
 #define GICV_HIGHESTPEND	0x18
 #define GICV_DEACTIVATE		0x1000
 
-/* GICD_SGIR bit shifts */
-#define GICD_SGIR_INTID_SHIFT		0
-#define GICD_SGIR_CPUTL_SHIFT		16
-
 /* GICC_IAR bit masks and shifts */
 #define GICC_IAR_INTID_SHIFT	0
 #define GICC_IAR_CPUID_SHIFT	10
@@ -155,74 +122,24 @@
 #include <mmio.h>
 
 /*******************************************************************************
- * GIC Distributor function prototypes
+ * Private Interfaces for internal use by the GICv2 driver
  ******************************************************************************/
-unsigned int gicd_read_isenabler(unsigned int, unsigned int);
-unsigned int gicd_read_icenabler(unsigned int, unsigned int);
-unsigned int gicd_read_ispendr(unsigned int, unsigned int);
-unsigned int gicd_read_icpendr(unsigned int, unsigned int);
-unsigned int gicd_read_isactiver(unsigned int, unsigned int);
-unsigned int gicd_read_icactiver(unsigned int, unsigned int);
-unsigned int gicd_read_ipriorityr(unsigned int, unsigned int);
-unsigned int gicd_read_itargetsr(unsigned int, unsigned int);
-unsigned int gicd_read_icfgr(unsigned int, unsigned int);
-unsigned int gicd_read_cpendsgir(unsigned int, unsigned int);
-unsigned int gicd_read_spendsgir(unsigned int, unsigned int);
-void gicd_write_isenabler(unsigned int, unsigned int, unsigned int);
-void gicd_write_icenabler(unsigned int, unsigned int, unsigned int);
-void gicd_write_ispendr(unsigned int, unsigned int, unsigned int);
-void gicd_write_icpendr(unsigned int, unsigned int, unsigned int);
-void gicd_write_isactiver(unsigned int, unsigned int, unsigned int);
-void gicd_write_icactiver(unsigned int, unsigned int, unsigned int);
-void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int);
-void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int);
-void gicd_write_icfgr(unsigned int, unsigned int, unsigned int);
-void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int);
-void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int);
-void gicd_set_isenabler(unsigned int, unsigned int);
-void gicd_set_icenabler(unsigned int, unsigned int);
-void gicd_set_ispendr(unsigned int, unsigned int);
-void gicd_set_icpendr(unsigned int, unsigned int);
-void gicd_set_isactiver(unsigned int, unsigned int);
-void gicd_set_icactiver(unsigned int, unsigned int);
-void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int);
-void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int);
-void gicd_clear_itargetsr(unsigned int, unsigned int, unsigned int);
 
 /*******************************************************************************
- * GIC Distributor interface accessors for reading entire registers
+ * GICv2 Distributor interface accessors for reading/writing entire registers
  ******************************************************************************/
-static inline unsigned int gicd_read_ctlr(unsigned int base)
-{
-	return mmio_read_32(base + GICD_CTLR);
-}
-
-static inline unsigned int gicd_read_typer(unsigned int base)
-{
-	return mmio_read_32(base + GICD_TYPER);
-}
-
 static inline unsigned int gicd_read_sgir(unsigned int base)
 {
 	return mmio_read_32(base + GICD_SGIR);
 }
 
-/*******************************************************************************
- * GIC Distributor interface accessors for writing entire registers
- ******************************************************************************/
-static inline void gicd_write_ctlr(unsigned int base, unsigned int val)
-{
-	mmio_write_32(base + GICD_CTLR, val);
-}
-
 static inline void gicd_write_sgir(unsigned int base, unsigned int val)
 {
 	mmio_write_32(base + GICD_SGIR, val);
 }
 
-
 /*******************************************************************************
- * GIC CPU interface accessors for reading entire registers
+ * GICv2 CPU interface accessors for reading entire registers
  ******************************************************************************/
 
 static inline unsigned int gicc_read_ctlr(unsigned int base)
@@ -272,7 +189,7 @@ static inline unsigned int gicc_read_iidr(unsigned int base)
 
 
 /*******************************************************************************
- * GIC CPU interface accessors for writing entire registers
+ * GICv2 CPU interface accessors for writing entire registers
  ******************************************************************************/
 
 static inline void gicc_write_ctlr(unsigned int base, unsigned int val)
@@ -311,12 +228,91 @@ static inline void gicc_write_dir(unsigned int base, unsigned int val)
 	mmio_write_32(base + GICC_DIR, val);
 }
 
-/*******************************************************************************
- * Prototype of function to map an interrupt type to the interrupt line used to
- * signal it.
- ******************************************************************************/
-uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type);
+/******************************************************************************
+ * GICv2 public driver API
+ *****************************************************************************/
 
-#endif /*__ASSEMBLY__*/
+/*
+ * Initialize the GICv2 driver. The base addresses of GIC CPU interface
+ * `gicc_base` and the Distributor interface `gicd_base` must be provided
+ * as arguments.
+ */
+void gicv2_init(uintptr_t gicc_base, uintptr_t gicd_base);
+
+/*
+ * Write the GICv2 EOIR register with `val` passed as argument. `val`
+ * should be the raw value read from IAR register.
+ */
+void gicv2_gicc_write_eoir(unsigned int val);
 
+/*
+ * Set the bit corresponding to `interrupt_id` in the GICD ICPENDR register.
+ */
+void gicv2_gicd_set_icpendr(unsigned int interrupt_id);
+
+/*
+ * Get the bit corresponding to `interrupt_id` from the GICD ISPENDR register.
+ */
+unsigned int gicv2_gicd_get_ispendr(unsigned int interrupt_id);
+
+/*
+ * Read and return the value in GICC IAR register
+ */
+unsigned int gicv2_gicc_read_iar(void);
+
+/*
+ * Set the bit corresponding to `num` in the GICD ICENABLER register.
+ */
+void gicv2_gicd_set_icenabler(unsigned int num);
+
+/*
+ * Set the bit corresponding to `num` in the GICD ISENABLER register.
+ */
+void gicv2_gicd_set_isenabler(unsigned int num);
+
+/*
+ * Set the target of interrupt ID `num` to core with index `core_pos`.
+ */
+void gicv2_set_itargetsr(unsigned int num, unsigned int core_pos);
+
+/*
+ * Send SGI with ID `sgi_id` to core with index `core_pos`.
+ */
+void gicv2_send_sgi(unsigned int sgi_id, unsigned int core_pos);
+
+/*
+ * Set the priority of the interrupt `interrupt_id` to `priority`.
+ */
+void gicv2_gicd_set_ipriorityr(unsigned int interrupt_id, unsigned int priority);
+
+/*
+ * Setup the GIC Distributor interface.
+ */
+void gicv2_setup_distif(void);
+
+/*
+ * Disable the GIC CPU interface.
+ */
+void gicv2_disable_cpuif(void);
+
+/*
+ * Setup the GIC CPU interface.
+ */
+void gicv2_setup_cpuif(void);
+
+/*
+ * Enable the GIC CPU interface.
+ */
+void gicv2_enable_cpuif(void);
+
+/*
+ * Read the GICD ITARGETR0 to figure out the GIC ID for the current core.
+ * This function is required to be invoked on successful boot of a core.
+ * The GIC ID will be stored internally by the driver to convert core index
+ * to GIC CPU ID when required.
+ */
+void gicv2_probe_gic_cpu_id(void);
+
+
+#endif /*__ASSEMBLY__*/
 #endif /* __GIC_V2_H__ */
diff --git a/include/lib/power_management.h b/include/lib/power_management.h
index d15edab..15d80ae 100644
--- a/include/lib/power_management.h
+++ b/include/lib/power_management.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -175,6 +175,8 @@ void tftf_set_cpu_offline(void);
  */
 unsigned int tftf_is_cpu_online(unsigned int mpid);
 
+unsigned int tftf_is_core_pos_online(unsigned int core_pos);
+
 /* TFTF Suspend helpers */
 static inline int tftf_cpu_suspend(unsigned int pwr_state)
 {
diff --git a/include/lib/sgi.h b/include/lib/sgi.h
index 0b5c779..f8de472 100644
--- a/include/lib/sgi.h
+++ b/include/lib/sgi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -35,8 +35,6 @@
 typedef struct {
 	/* Interrupt ID of the signaled interrupt */
 	unsigned int irq_id;
-	/* Identifies the processor that requested the SGI */
-	unsigned int cpu_id;
 } sgi_data_t;
 
 /*