1 files changed, 74 insertions, 0 deletions
diff --git a/plat/nxp/board/warp7/warp7_pwr_state.c b/plat/nxp/board/warp7/warp7_pwr_state.c
new file mode 100644
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--- /dev/null
+++ b/plat/nxp/board/warp7/warp7_pwr_state.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <arch.h>
+#include <platform.h>
+#include <psci.h>
+#include <stddef.h>
+
+/*
+ * State IDs for local power states on Warp7.
+ */
+#define WARP7_RUN_STATE_ID		0 /* Valid for CPUs and Clusters */
+#define WARP7_RETENTION_STATE_ID		1 /* Valid for only CPUs */
+#define WARP7_OFF_STATE_ID		2 /* Valid for CPUs and Clusters */
+
+/*
+ * Suspend depth definitions for each power state
+ */
+typedef enum {
+	WARP7_RUN_DEPTH = 0,
+	WARP7_RETENTION_DEPTH,
+	WARP7_OFF_DEPTH,
+} suspend_depth_t;
+
+/* The state property array with details of idle state possible for the core */
+static const plat_state_prop_t core_state_prop[] = {
+	{WARP7_RETENTION_DEPTH, WARP7_RETENTION_STATE_ID, PSTATE_TYPE_STANDBY},
+	{WARP7_OFF_DEPTH, WARP7_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+	{0},
+};
+
+static const plat_state_prop_t system_state_prop[] = {
+	{WARP7_RETENTION_DEPTH, WARP7_RETENTION_STATE_ID, PSTATE_TYPE_STANDBY},
+	{WARP7_OFF_DEPTH, WARP7_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+	{0},
+};
+
+const plat_state_prop_t *plat_get_state_prop(unsigned int level)
+{
+	switch (level) {
+	case MPIDR_AFFLVL0:
+		return core_state_prop;
+	case MPIDR_AFFLVL1:
+		return system_state_prop;
+	default:
+		return NULL;
+	}
+}