From 285ff6cc8d01e24940b654c1c67dc38c5ab931b5 Mon Sep 17 00:00:00 2001 From: Antonio Nino Diaz Date: Thu, 26 Jan 2017 17:45:15 +0000 Subject: Allow IRQ handler to handle spurious IRQs Modify the IRQ handler so that tests can specify a spurious IRQ handler. This type of interrupt is only generated by GICv2 implementations when the config registers are set up in certain ways, so this patch also adds new helper functions to access said registers. Change-Id: I81b21651046d2b8c4c069f27aec61a2969441730 Signed-off-by: Antonio Nino Diaz --- include/drivers/arm/gic_v2.h | 10 ++++++++++ include/lib/irq.h | 3 +++ 2 files changed, 13 insertions(+) (limited to 'include') diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h index 2959a99..5752703 100644 --- a/include/drivers/arm/gic_v2.h +++ b/include/drivers/arm/gic_v2.h @@ -245,6 +245,11 @@ void gicv2_init(uintptr_t gicc_base, uintptr_t gicd_base); */ void gicv2_gicc_write_eoir(unsigned int val); +/* + * Set the bit corresponding to `interrupt_id` in the GICD ISPENDR register. + */ +void gicv2_gicd_set_ispendr(unsigned int interrupt_id); + /* * Set the bit corresponding to `interrupt_id` in the GICD ICPENDR register. */ @@ -275,6 +280,11 @@ void gicv2_gicd_set_isenabler(unsigned int num); */ void gicv2_set_itargetsr(unsigned int num, unsigned int core_pos); +/* + * Set the target of interrupt ID `num` to the desired core mask. + */ +void gicv2_set_itargetsr_value(unsigned int num, unsigned int val); + /* * Send SGI with ID `sgi_id` to core with index `core_pos`. */ diff --git a/include/lib/irq.h b/include/lib/irq.h index 2939ec8..60d4fa4 100644 --- a/include/lib/irq.h +++ b/include/lib/irq.h @@ -50,6 +50,9 @@ typedef struct { irq_handler_t handler; } spi_desc; +/* Keep track of the IRQ handler registered for a spurious interrupt */ +typedef irq_handler_t spurious_desc; + /* * PPIs and SGIs are interrupts that are private to a GIC CPU interface. These * interrupts are banked in the GIC Distributor. Therefore, each CPU can -- cgit v1.2.3