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/** @file
*
* Copyright (c) 2013, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <arch_helpers.h>
#include <arm_gic.h>
#include <assert.h>
#include <console.h>
#include <debug.h>
#include <io_storage.h>
#include <irq.h>
#include <nvm.h>
#include <platform.h>
#include <psci.h>
#include <string.h>
#include <tftf.h>
#include "fvp_def.h"
#include "fvp_private.h"
#define CLUSTER_1_MASK 0x100
#define CORE_PRESENT 1
static struct {
unsigned int cluster_id;
unsigned int cpu_id;
} fvp_base_aemv8a_aemv8a_cores[] = {
/* Cluster 0 */
{ 0, 0 },
{ 0, 1 },
{ 0, 2 },
{ 0, 3 },
/* Cluster 1 */
{ 1, 0 },
{ 1, 1 },
{ 1, 2 },
{ 1, 3 },
};
/*
* Table of regions to map using the MMU.
*/
static const mmap_region_t tftf_mmap[] = {
{ DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_NS },
{ DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS },
#if USE_NVM
{ FLASH0_BASE, FLASH0_BASE, FLASH0_SIZE, MT_DEVICE | MT_RW | MT_NS },
{ FLASH1_BASE, FLASH1_BASE, FLASH1_SIZE, MT_DEVICE | MT_RW | MT_NS },
#endif
{ DRAM_BASE, DRAM_BASE, TFTF_BASE - DRAM_BASE, MT_MEMORY | MT_RW | MT_NS },
{ TFTF_BASE, TFTF_BASE, L2_BLOCK_SIZE, MT_MEMORY | MT_RO | MT_NS }, /* Program text */
{ TFTF_BASE + L2_BLOCK_SIZE, TFTF_BASE + L2_BLOCK_SIZE,
( DRAM_BASE + DRAM_SIZE) - (TFTF_BASE + L2_BLOCK_SIZE), MT_MEMORY | MT_RW | MT_NS },
{ 0xFFFFFFFF - DRAM_TZ_SIZE + 1, 0xFFFFFFFF - DRAM_TZ_SIZE + 1, DRAM_TZ_SIZE, MT_MEMORY | MT_RW | MT_NS },
{ 0 }
};
const mmap_region_t *tftf_platform_get_mmap(void)
{
return tftf_mmap;
}
unsigned int tftf_platform_core_pos_to_mpid(const unsigned int core_pos)
{
unsigned int mpid = make_mpid(
fvp_base_aemv8a_aemv8a_cores[core_pos].cluster_id,
fvp_base_aemv8a_aemv8a_cores[core_pos].cpu_id);
return mpid;
}
bool tftf_platform_is_core_pos_present(unsigned int core_pos)
{
unsigned int mpidr;
mpidr = tftf_platform_core_pos_to_mpid(core_pos);
return plat_get_aff_state(MPIDR_AFFLVL0, mpidr) == PSCI_AFF_PRESENT;
}
void tftf_platform_setup(void)
{
#if USE_NVM
int ret;
ret = fvp_io_setup();
if (ret != IO_SUCCESS)
WARN("IO setup failed : 0x%x\n", ret);
#endif
/*
* Hardcodes to base models, TFTF does not support legacy models
* as of now
*/
arm_gic_init(BASE_GICC_BASE, BASE_GICD_BASE, BASE_GICR_BASE);
tftf_register_gic_id();
arm_gic_setup();
fvp_setup_topology();
}
void tftf_early_platform_setup(void)
{
console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
}
void tftf_plat_arch_setup(void)
{
tftf_plat_configure_mmu();
}
/* Terminate the model by sending EOT (End Of Transmission) on the UART */
void tftf_platform_end(void)
{
static const char ascii_eot = 4;
console_putc(ascii_eot);
}
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